/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "df_v1_7.h" #include "df/df_1_7_default.h" #include "df/df_1_7_offset.h" #include "df/df_1_7_sh_mask.h" static u32 df_v1_7_channel_number[] = …; static void df_v1_7_sw_init(struct amdgpu_device *adev) { … } static void df_v1_7_sw_fini(struct amdgpu_device *adev) { … } static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev, bool enable) { … } static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev) { … } static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev) { … } static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { … } static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev, u64 *flags) { … } static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev, bool enable) { … } const struct amdgpu_df_funcs df_v1_7_funcs = …;