/* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __UMC_V12_0_H__ #define __UMC_V12_0_H__ #include "soc15_common.h" #include "amdgpu.h" #define UMC_V12_0_NODE_DIST … #define UMC_V12_0_INST_DIST … /* UMC register per channel offset */ #define UMC_V12_0_PER_CHANNEL_OFFSET … /* UMC cross node offset */ #define UMC_V12_0_CROSS_NODE_OFFSET … /* OdEccErrCnt max value */ #define UMC_V12_0_CE_CNT_MAX … /* umc ce interrupt threshold */ #define UMC_V12_0_CE_INT_THRESHOLD … /* umc ce count initial value */ #define UMC_V12_0_CE_CNT_INIT … /* number of umc channel instance with memory map register access */ #define UMC_V12_0_CHANNEL_INSTANCE_NUM … /* number of umc instance with memory map register access */ #define UMC_V12_0_UMC_INSTANCE_NUM … /* Total channel instances for all available umc nodes */ #define UMC_V12_0_TOTAL_CHANNEL_NUM(adev) … /* one piece of normalized address is mapped to 8 pieces of physical address */ #define UMC_V12_0_NA_MAP_PA_NUM … /* R13 bit shift should be considered, double the number */ #define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL … /* column bits in SOC physical address */ #define UMC_V12_0_PA_C2_BIT … #define UMC_V12_0_PA_C4_BIT … /* row bits in SOC physical address */ #define UMC_V12_0_PA_R13_BIT … #define MCA_UMC_HWID_V12_0 … #define MCA_UMC_MCATYPE_V12_0 … #define MCA_IPID_LO_2_UMC_CH(_ipid_lo) … #define MCA_IPID_LO_2_UMC_INST(_ipid_lo) … #define MCA_IPID_2_DIE_ID(ipid) … #define MCA_IPID_2_UMC_CH(ipid) … #define MCA_IPID_2_UMC_INST(ipid) … #define MCA_IPID_2_SOCKET_ID(ipid) … #define UMC_V12_ADDR_MASK_BAD_COLS(addr) … bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status); bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status); bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status); check_error_type_func; extern struct amdgpu_umc_ras umc_v12_0_ras; #endif
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