// SPDX-License-Identifier: GPL-2.0 /* Atheros AR71xx built-in ethernet mac driver * * Copyright (C) 2019 Oleksij Rempel <[email protected]> * * List of authors contributed to this driver before mainlining: * Alexander Couzens <[email protected]> * Christian Lamparter <[email protected]> * Chuanhong Guo <[email protected]> * Daniel F. Dickinson <[email protected]> * David Bauer <[email protected]> * Felix Fietkau <[email protected]> * Gabor Juhos <[email protected]> * Hauke Mehrtens <[email protected]> * Johann Neuhauser <[email protected]> * John Crispin <[email protected]> * Jo-Philipp Wich <[email protected]> * Koen Vandeputte <[email protected]> * Lucian Cristian <[email protected]> * Matt Merhar <[email protected]> * Milan Krstic <[email protected]> * Petr Štetiar <[email protected]> * Rosen Penev <[email protected]> * Stephen Walker <[email protected]> * Vittorio Gambaletta <[email protected]> * Weijie Gao <[email protected]> * Imre Kaloz <[email protected]> */ #include <linux/if_vlan.h> #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/of_mdio.h> #include <linux/of_net.h> #include <linux/platform_device.h> #include <linux/phylink.h> #include <linux/regmap.h> #include <linux/reset.h> #include <linux/clk.h> #include <linux/io.h> #include <net/selftests.h> /* For our NAPI weight bigger does *NOT* mean better - it means more * D-cache misses and lots more wasted cycles than we'll ever * possibly gain from saving instructions. */ #define AG71XX_NAPI_WEIGHT … #define AG71XX_OOM_REFILL … #define AG71XX_INT_ERR … #define AG71XX_INT_TX … #define AG71XX_INT_RX … #define AG71XX_INT_POLL … #define AG71XX_INT_INIT … #define AG71XX_TX_MTU_LEN … #define AG71XX_TX_RING_SPLIT … #define AG71XX_TX_RING_DS_PER_PKT … #define AG71XX_TX_RING_SIZE_DEFAULT … #define AG71XX_RX_RING_SIZE_DEFAULT … #define AG71XX_MDIO_RETRY … #define AG71XX_MDIO_DELAY … #define AG71XX_MDIO_MAX_CLK … /* Register offsets */ #define AG71XX_REG_MAC_CFG1 … #define MAC_CFG1_TXE … #define MAC_CFG1_STX … #define MAC_CFG1_RXE … #define MAC_CFG1_SRX … #define MAC_CFG1_TFC … #define MAC_CFG1_RFC … #define MAC_CFG1_SR … #define MAC_CFG1_INIT … #define AG71XX_REG_MAC_CFG2 … #define MAC_CFG2_FDX … #define MAC_CFG2_PAD_CRC_EN … #define MAC_CFG2_LEN_CHECK … #define MAC_CFG2_IF_1000 … #define MAC_CFG2_IF_10_100 … #define AG71XX_REG_MAC_MFL … #define AG71XX_REG_MII_CFG … #define MII_CFG_CLK_DIV_4 … #define MII_CFG_CLK_DIV_6 … #define MII_CFG_CLK_DIV_8 … #define MII_CFG_CLK_DIV_10 … #define MII_CFG_CLK_DIV_14 … #define MII_CFG_CLK_DIV_20 … #define MII_CFG_CLK_DIV_28 … #define MII_CFG_CLK_DIV_34 … #define MII_CFG_CLK_DIV_42 … #define MII_CFG_CLK_DIV_50 … #define MII_CFG_CLK_DIV_58 … #define MII_CFG_CLK_DIV_66 … #define MII_CFG_CLK_DIV_74 … #define MII_CFG_CLK_DIV_82 … #define MII_CFG_CLK_DIV_98 … #define MII_CFG_RESET … #define AG71XX_REG_MII_CMD … #define MII_CMD_READ … #define AG71XX_REG_MII_ADDR … #define MII_ADDR_SHIFT … #define AG71XX_REG_MII_CTRL … #define AG71XX_REG_MII_STATUS … #define AG71XX_REG_MII_IND … #define MII_IND_BUSY … #define MII_IND_INVALID … #define AG71XX_REG_MAC_IFCTL … #define MAC_IFCTL_SPEED … #define AG71XX_REG_MAC_ADDR1 … #define AG71XX_REG_MAC_ADDR2 … #define AG71XX_REG_FIFO_CFG0 … #define FIFO_CFG0_WTM … #define FIFO_CFG0_RXS … #define FIFO_CFG0_RXF … #define FIFO_CFG0_TXS … #define FIFO_CFG0_TXF … #define FIFO_CFG0_ALL … #define FIFO_CFG0_INIT … #define FIFO_CFG0_ENABLE_SHIFT … #define AG71XX_REG_FIFO_CFG1 … #define AG71XX_REG_FIFO_CFG2 … #define AG71XX_REG_FIFO_CFG3 … #define AG71XX_REG_FIFO_CFG4 … #define FIFO_CFG4_DE … #define FIFO_CFG4_DV … #define FIFO_CFG4_FC … #define FIFO_CFG4_CE … #define FIFO_CFG4_CR … #define FIFO_CFG4_LM … #define FIFO_CFG4_LO … #define FIFO_CFG4_OK … #define FIFO_CFG4_MC … #define FIFO_CFG4_BC … #define FIFO_CFG4_DR … #define FIFO_CFG4_CF … #define FIFO_CFG4_PF … #define FIFO_CFG4_UO … #define FIFO_CFG4_VT … #define FIFO_CFG4_LE … #define FIFO_CFG4_FT … #define FIFO_CFG4_UC … #define FIFO_CFG4_INIT … #define AG71XX_REG_FIFO_CFG5 … #define FIFO_CFG5_DE … #define FIFO_CFG5_DV … #define FIFO_CFG5_FC … #define FIFO_CFG5_CE … #define FIFO_CFG5_CR … #define FIFO_CFG5_LM … #define FIFO_CFG5_LO … #define FIFO_CFG5_OK … #define FIFO_CFG5_MC … #define FIFO_CFG5_BC … #define FIFO_CFG5_DR … #define FIFO_CFG5_CF … #define FIFO_CFG5_PF … #define FIFO_CFG5_UO … #define FIFO_CFG5_VT … #define FIFO_CFG5_LE … #define FIFO_CFG5_FT … #define FIFO_CFG5_UC … #define FIFO_CFG5_SF … #define FIFO_CFG5_BM … #define FIFO_CFG5_INIT … #define AG71XX_REG_TX_CTRL … #define TX_CTRL_TXE … #define AG71XX_REG_TX_DESC … #define AG71XX_REG_TX_STATUS … #define TX_STATUS_PS … #define TX_STATUS_UR … #define TX_STATUS_BE … #define AG71XX_REG_RX_CTRL … #define RX_CTRL_RXE … #define AG71XX_DMA_RETRY … #define AG71XX_DMA_DELAY … #define AG71XX_REG_RX_DESC … #define AG71XX_REG_RX_STATUS … #define RX_STATUS_PR … #define RX_STATUS_OF … #define RX_STATUS_BE … #define AG71XX_REG_INT_ENABLE … #define AG71XX_REG_INT_STATUS … #define AG71XX_INT_TX_PS … #define AG71XX_INT_TX_UR … #define AG71XX_INT_TX_BE … #define AG71XX_INT_RX_PR … #define AG71XX_INT_RX_OF … #define AG71XX_INT_RX_BE … #define AG71XX_REG_FIFO_DEPTH … #define AG71XX_REG_RX_SM … #define AG71XX_REG_TX_SM … #define AG71XX_DEFAULT_MSG_ENABLE … struct ag71xx_statistic { … }; static const struct ag71xx_statistic ag71xx_statistics[] = …; #define DESC_EMPTY … #define DESC_MORE … #define DESC_PKTLEN_M … struct ag71xx_desc { … } __aligned(…); #define AG71XX_DESC_SIZE … struct ag71xx_buf { … }; struct ag71xx_ring { … }; enum ag71xx_type { … }; struct ag71xx_dcfg { … }; struct ag71xx { … }; static int ag71xx_desc_empty(struct ag71xx_desc *desc) { … } static struct ag71xx_desc *ag71xx_ring_desc(struct ag71xx_ring *ring, int idx) { … } static int ag71xx_ring_size_order(int size) { … } static bool ag71xx_is(struct ag71xx *ag, enum ag71xx_type type) { … } static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value) { … } static u32 ag71xx_rr(struct ag71xx *ag, unsigned int reg) { … } static void ag71xx_sb(struct ag71xx *ag, unsigned int reg, u32 mask) { … } static void ag71xx_cb(struct ag71xx *ag, unsigned int reg, u32 mask) { … } static void ag71xx_int_enable(struct ag71xx *ag, u32 ints) { … } static void ag71xx_int_disable(struct ag71xx *ag, u32 ints) { … } static int ag71xx_do_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) { … } static void ag71xx_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info) { … } static int ag71xx_get_link_ksettings(struct net_device *ndev, struct ethtool_link_ksettings *kset) { … } static int ag71xx_set_link_ksettings(struct net_device *ndev, const struct ethtool_link_ksettings *kset) { … } static int ag71xx_ethtool_nway_reset(struct net_device *ndev) { … } static void ag71xx_ethtool_get_pauseparam(struct net_device *ndev, struct ethtool_pauseparam *pause) { … } static int ag71xx_ethtool_set_pauseparam(struct net_device *ndev, struct ethtool_pauseparam *pause) { … } static void ag71xx_ethtool_get_strings(struct net_device *netdev, u32 sset, u8 *data) { … } static void ag71xx_ethtool_get_stats(struct net_device *ndev, struct ethtool_stats *stats, u64 *data) { … } static int ag71xx_ethtool_get_sset_count(struct net_device *ndev, int sset) { … } static const struct ethtool_ops ag71xx_ethtool_ops = …; static int ag71xx_mdio_wait_busy(struct ag71xx *ag) { … } static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg) { … } static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, u16 val) { … } static const u32 ar71xx_mdio_div_table[] = …; static const u32 ar7240_mdio_div_table[] = …; static const u32 ar933x_mdio_div_table[] = …; static int ag71xx_mdio_get_divider(struct ag71xx *ag, u32 *div) { … } static int ag71xx_mdio_reset(struct mii_bus *bus) { … } static int ag71xx_mdio_probe(struct ag71xx *ag) { … } static void ag71xx_hw_stop(struct ag71xx *ag) { … } static bool ag71xx_check_dma_stuck(struct ag71xx *ag) { … } static int ag71xx_tx_packets(struct ag71xx *ag, bool flush, int budget) { … } static void ag71xx_dma_wait_stop(struct ag71xx *ag) { … } static void ag71xx_dma_reset(struct ag71xx *ag) { … } static void ag71xx_hw_setup(struct ag71xx *ag) { … } static unsigned int ag71xx_max_frame_len(unsigned int mtu) { … } static void ag71xx_hw_set_macaddr(struct ag71xx *ag, const unsigned char *mac) { … } static void ag71xx_fast_reset(struct ag71xx *ag) { … } static void ag71xx_hw_start(struct ag71xx *ag) { … } static void ag71xx_mac_config(struct phylink_config *config, unsigned int mode, const struct phylink_link_state *state) { … } static void ag71xx_mac_link_down(struct phylink_config *config, unsigned int mode, phy_interface_t interface) { … } static void ag71xx_mac_link_up(struct phylink_config *config, struct phy_device *phy, unsigned int mode, phy_interface_t interface, int speed, int duplex, bool tx_pause, bool rx_pause) { … } static const struct phylink_mac_ops ag71xx_phylink_mac_ops = …; static int ag71xx_phylink_setup(struct ag71xx *ag) { … } static void ag71xx_ring_tx_clean(struct ag71xx *ag) { … } static void ag71xx_ring_tx_init(struct ag71xx *ag) { … } static void ag71xx_ring_rx_clean(struct ag71xx *ag) { … } static int ag71xx_buffer_size(struct ag71xx *ag) { … } static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf, int offset, void *(*alloc)(unsigned int size)) { … } static int ag71xx_ring_rx_init(struct ag71xx *ag) { … } static int ag71xx_ring_rx_refill(struct ag71xx *ag) { … } static int ag71xx_rings_init(struct ag71xx *ag) { … } static void ag71xx_rings_free(struct ag71xx *ag) { … } static void ag71xx_rings_cleanup(struct ag71xx *ag) { … } static void ag71xx_hw_init(struct ag71xx *ag) { … } static int ag71xx_hw_enable(struct ag71xx *ag) { … } static void ag71xx_hw_disable(struct ag71xx *ag) { … } static int ag71xx_open(struct net_device *ndev) { … } static int ag71xx_stop(struct net_device *ndev) { … } static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len) { … } static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev) { … } static void ag71xx_oom_timer_handler(struct timer_list *t) { … } static void ag71xx_tx_timeout(struct net_device *ndev, unsigned int txqueue) { … } static void ag71xx_restart_work_func(struct work_struct *work) { … } static int ag71xx_rx_packets(struct ag71xx *ag, int limit) { … } static int ag71xx_poll(struct napi_struct *napi, int limit) { … } static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) { … } static int ag71xx_change_mtu(struct net_device *ndev, int new_mtu) { … } static const struct net_device_ops ag71xx_netdev_ops = …; static const u32 ar71xx_addr_ar7100[] = …; static int ag71xx_probe(struct platform_device *pdev) { … } static const u32 ar71xx_fifo_ar7100[] = …; static const u32 ar71xx_fifo_ar9130[] = …; static const u32 ar71xx_fifo_ar9330[] = …; static const struct ag71xx_dcfg ag71xx_dcfg_ar7100 = …; static const struct ag71xx_dcfg ag71xx_dcfg_ar7240 = …; static const struct ag71xx_dcfg ag71xx_dcfg_ar9130 = …; static const struct ag71xx_dcfg ag71xx_dcfg_ar9330 = …; static const struct ag71xx_dcfg ag71xx_dcfg_ar9340 = …; static const struct ag71xx_dcfg ag71xx_dcfg_qca9530 = …; static const struct ag71xx_dcfg ag71xx_dcfg_qca9550 = …; static const struct of_device_id ag71xx_match[] = …; MODULE_DEVICE_TABLE(of, ag71xx_match); static struct platform_driver ag71xx_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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