// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2024 Nuvoton Technology Corp. * * Author: Shan-Chun Hung <[email protected]> * * Jacky Huang <[email protected]> */ #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/cleanup.h> #include <linux/clk.h> #include <linux/gpio/driver.h> #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include "../core.h" #include "../pinconf.h" #include "pinctrl-ma35.h" #define MA35_MFP_REG_BASE … #define MA35_MFP_REG_SZ_PER_BANK … #define MA35_MFP_BITS_PER_PORT … #define MA35_GPIO_BANK_MAX … #define MA35_GPIO_PORT_MAX … /* GPIO control registers */ #define MA35_GP_REG_MODE … #define MA35_GP_REG_DINOFF … #define MA35_GP_REG_DOUT … #define MA35_GP_REG_DATMSK … #define MA35_GP_REG_PIN … #define MA35_GP_REG_DBEN … #define MA35_GP_REG_INTTYPE … #define MA35_GP_REG_INTEN … #define MA35_GP_REG_INTSRC … #define MA35_GP_REG_SMTEN … #define MA35_GP_REG_SLEWCTL … #define MA35_GP_REG_SPW … #define MA35_GP_REG_PUSEL … #define MA35_GP_REG_DSL … #define MA35_GP_REG_DSH … /* GPIO mode control */ #define MA35_GP_MODE_INPUT … #define MA35_GP_MODE_OUTPUT … #define MA35_GP_MODE_OPEN_DRAIN … #define MA35_GP_MODE_QUASI … #define MA35_GP_MODE_MASK(n) … #define MA35_GP_SLEWCTL_MASK(n) … /* GPIO pull-up and pull-down selection control */ #define MA35_GP_PUSEL_DISABLE … #define MA35_GP_PUSEL_PULL_UP … #define MA35_GP_PUSEL_PULL_DOWN … #define MA35_GP_PUSEL_MASK(n) … /* * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger, * while bits 16 ~ 31 control high-level or rising edge trigger. */ #define MA35_GP_INTEN_L(n) … #define MA35_GP_INTEN_H(n) … #define MA35_GP_INTEN_BOTH(n) … /* * The MA35_GP_REG_DSL register controls ports 0 to 7, while the MA35_GP_REG_DSH * register controls ports 8 to 15. Each port occupies a width of 4 bits, with 3 * bits being effective. */ #define MA35_GP_DS_REG(n) … #define MA35_GP_DS_MASK(n) … #define MVOLT_1800 … #define MVOLT_3300 … /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ #define field_get(_mask, _reg) … #define field_prep(_mask, _val) … static const char * const gpio_group_name[] = …; static const u32 ds_1800mv_tbl[] = …; static const u32 ds_3300mv_tbl[] = …; struct ma35_pin_func { … }; struct ma35_pin_setting { … }; struct ma35_pin_group { … }; struct ma35_pin_bank { … }; struct ma35_pin_ctrl { … }; struct ma35_pinctrl { … }; static DEFINE_RAW_SPINLOCK(ma35_lock); static int ma35_get_groups_count(struct pinctrl_dev *pctldev) { … } static const char *ma35_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) { … } static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, const unsigned int **pins, unsigned int *npins) { … } static struct ma35_pin_group *ma35_pinctrl_find_group_by_name( const struct ma35_pinctrl *npctl, const char *name) { … } static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned int *num_maps) { … } static const struct pinctrl_ops ma35_pctrl_ops = …; static int ma35_pinmux_get_func_count(struct pinctrl_dev *pctldev) { … } static const char *ma35_pinmux_get_func_name(struct pinctrl_dev *pctldev, unsigned int selector) { … } static int ma35_pinmux_get_func_groups(struct pinctrl_dev *pctldev, unsigned int function, const char *const **groups, unsigned int *const num_groups) { … } static int ma35_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, unsigned int group) { … } static const struct pinmux_ops ma35_pmx_ops = …; static void ma35_gpio_set_mode(void __iomem *reg_mode, unsigned int gpio, u32 mode) { … } static u32 ma35_gpio_get_mode(void __iomem *reg_mode, unsigned int gpio) { … } static int ma35_gpio_core_direction_in(struct gpio_chip *gc, unsigned int gpio) { … } static int ma35_gpio_core_direction_out(struct gpio_chip *gc, unsigned int gpio, int val) { … } static int ma35_gpio_core_get(struct gpio_chip *gc, unsigned int gpio) { … } static void ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val) { … } static int ma35_gpio_core_to_request(struct gpio_chip *gc, unsigned int gpio) { … } static void ma35_irq_gpio_ack(struct irq_data *d) { … } static void ma35_irq_gpio_mask(struct irq_data *d) { … } static void ma35_irq_gpio_unmask(struct irq_data *d) { … } static int ma35_irq_irqtype(struct irq_data *d, unsigned int type) { … } static struct irq_chip ma35_gpio_irqchip = …; static void ma35_irq_demux_intgroup(struct irq_desc *desc) { … } static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinctrl *npctl) { … } static int ma35_get_bank_data(struct ma35_pin_bank *bank) { … } static int ma35_pinctrl_get_soc_data(struct ma35_pinctrl *pctl, struct platform_device *pdev) { … } static void ma35_gpio_cla_port(unsigned int gpio_num, unsigned int *group, unsigned int *num) { … } static int ma35_pinconf_set_pull(struct ma35_pinctrl *npctl, unsigned int pin, int pull_up) { … } static int ma35_pinconf_get_output(struct ma35_pinctrl *npctl, unsigned int pin) { … } static int ma35_pinconf_get_pull(struct ma35_pinctrl *npctl, unsigned int pin) { … } static int ma35_pinconf_set_output(struct ma35_pinctrl *npctl, unsigned int pin, bool out) { … } static int ma35_pinconf_get_power_source(struct ma35_pinctrl *npctl, unsigned int pin) { … } static int ma35_pinconf_set_power_source(struct ma35_pinctrl *npctl, unsigned int pin, int arg) { … } static int ma35_pinconf_get_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin, u32 *strength) { … } static int ma35_pinconf_set_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin, int strength) { … } static int ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl *npctl, unsigned int pin) { … } static int ma35_pinconf_set_schmitt(struct ma35_pinctrl *npctl, unsigned int pin, int enable) { … } static int ma35_pinconf_get_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin) { … } static int ma35_pinconf_set_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin, int rate) { … } static int ma35_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { … } static int ma35_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { … } static const struct pinconf_ops ma35_pinconf_ops = …; static int ma35_pinctrl_parse_groups(struct device_node *np, struct ma35_pin_group *grp, struct ma35_pinctrl *npctl, u32 index) { … } static int ma35_pinctrl_parse_functions(struct device_node *np, struct ma35_pinctrl *npctl, u32 index) { … } static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinctrl *npctl) { … } int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info) { … } int ma35_pinctrl_suspend(struct device *dev) { … } int ma35_pinctrl_resume(struct device *dev) { … }
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