#ifndef _sdma3_4_2_2_SH_MASK_HEADER
#define _sdma3_4_2_2_SH_MASK_HEADER
#define SDMA3_UCODE_ADDR__VALUE__SHIFT …
#define SDMA3_UCODE_ADDR__VALUE_MASK …
#define SDMA3_UCODE_DATA__VALUE__SHIFT …
#define SDMA3_UCODE_DATA__VALUE_MASK …
#define SDMA3_VM_CNTL__CMD__SHIFT …
#define SDMA3_VM_CNTL__CMD_MASK …
#define SDMA3_VM_CTX_LO__ADDR__SHIFT …
#define SDMA3_VM_CTX_LO__ADDR_MASK …
#define SDMA3_VM_CTX_HI__ADDR__SHIFT …
#define SDMA3_VM_CTX_HI__ADDR_MASK …
#define SDMA3_ACTIVE_FCN_ID__VFID__SHIFT …
#define SDMA3_ACTIVE_FCN_ID__RESERVED__SHIFT …
#define SDMA3_ACTIVE_FCN_ID__VF__SHIFT …
#define SDMA3_ACTIVE_FCN_ID__VFID_MASK …
#define SDMA3_ACTIVE_FCN_ID__RESERVED_MASK …
#define SDMA3_ACTIVE_FCN_ID__VF_MASK …
#define SDMA3_VM_CTX_CNTL__PRIV__SHIFT …
#define SDMA3_VM_CTX_CNTL__VMID__SHIFT …
#define SDMA3_VM_CTX_CNTL__PRIV_MASK …
#define SDMA3_VM_CTX_CNTL__VMID_MASK …
#define SDMA3_VIRT_RESET_REQ__VF__SHIFT …
#define SDMA3_VIRT_RESET_REQ__PF__SHIFT …
#define SDMA3_VIRT_RESET_REQ__VF_MASK …
#define SDMA3_VIRT_RESET_REQ__PF_MASK …
#define SDMA3_VF_ENABLE__VF_ENABLE__SHIFT …
#define SDMA3_VF_ENABLE__VF_ENABLE_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL_MASK …
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__RESERVED__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE_MASK …
#define SDMA3_CONTEXT_REG_TYPE1__RESERVED_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__RESERVED__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL_MASK …
#define SDMA3_CONTEXT_REG_TYPE2__RESERVED_MASK …
#define SDMA3_CONTEXT_REG_TYPE3__RESERVED__SHIFT …
#define SDMA3_CONTEXT_REG_TYPE3__RESERVED_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA__SHIFT …
#define SDMA3_PUB_REG_TYPE0__RESERVED3__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ__SHIFT …
#define SDMA3_PUB_REG_TYPE0__RESERVED10__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_MMHUB_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_GROUP_BOUNDARY__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ__SHIFT …
#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA_MASK …
#define SDMA3_PUB_REG_TYPE0__RESERVED3_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ_MASK …
#define SDMA3_PUB_REG_TYPE0__RESERVED10_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_MMHUB_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_GROUP_BOUNDARY_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_MASK …
#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_ID__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS__SHIFT …
#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_ID_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS_MASK …
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_POWER_CNTL_IDLE__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UNBREAKABLE__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFMON_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER0_RESULT__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER1_RESULT__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE2__RESERVED28__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_GPU_IOV_VIOLATION_LOG__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_ULV_CNTL__SHIFT …
#define SDMA3_PUB_REG_TYPE2__RESERVED__SHIFT …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_POWER_CNTL_IDLE_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_UNBREAKABLE_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFMON_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER0_RESULT_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER1_RESULT_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER_TAG_DELAY_RANGE_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE2__RESERVED28_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_GPU_IOV_VIOLATION_LOG_MASK …
#define SDMA3_PUB_REG_TYPE2__SDMA3_ULV_CNTL_MASK …
#define SDMA3_PUB_REG_TYPE2__RESERVED_MASK …
#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA__SHIFT …
#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX__SHIFT …
#define SDMA3_PUB_REG_TYPE3__SDMA3_GPU_IOV_VIOLATION_LOG2__SHIFT …
#define SDMA3_PUB_REG_TYPE3__RESERVED__SHIFT …
#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA_MASK …
#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX_MASK …
#define SDMA3_PUB_REG_TYPE3__SDMA3_GPU_IOV_VIOLATION_LOG2_MASK …
#define SDMA3_PUB_REG_TYPE3__RESERVED_MASK …
#define SDMA3_MMHUB_CNTL__UNIT_ID__SHIFT …
#define SDMA3_MMHUB_CNTL__UNIT_ID_MASK …
#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT …
#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK …
#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT …
#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN__SHIFT …
#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN__SHIFT …
#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN__SHIFT …
#define SDMA3_POWER_CNTL__MEM_POWER_DELAY__SHIFT …
#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE_MASK …
#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN_MASK …
#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN_MASK …
#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN_MASK …
#define SDMA3_POWER_CNTL__MEM_POWER_DELAY_MASK …
#define SDMA3_CLK_CTRL__ON_DELAY__SHIFT …
#define SDMA3_CLK_CTRL__OFF_HYSTERESIS__SHIFT …
#define SDMA3_CLK_CTRL__RESERVED__SHIFT …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7__SHIFT …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6__SHIFT …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5__SHIFT …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4__SHIFT …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3__SHIFT …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1__SHIFT …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0__SHIFT …
#define SDMA3_CLK_CTRL__ON_DELAY_MASK …
#define SDMA3_CLK_CTRL__OFF_HYSTERESIS_MASK …
#define SDMA3_CLK_CTRL__RESERVED_MASK …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7_MASK …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6_MASK …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5_MASK …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4_MASK …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3_MASK …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2_MASK …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1_MASK …
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0_MASK …
#define SDMA3_CNTL__TRAP_ENABLE__SHIFT …
#define SDMA3_CNTL__UTC_L1_ENABLE__SHIFT …
#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE__SHIFT …
#define SDMA3_CNTL__DATA_SWAP_ENABLE__SHIFT …
#define SDMA3_CNTL__FENCE_SWAP_ENABLE__SHIFT …
#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT …
#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT …
#define SDMA3_CNTL__AUTO_CTXSW_ENABLE__SHIFT …
#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE__SHIFT …
#define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT …
#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT …
#define SDMA3_CNTL__TRAP_ENABLE_MASK …
#define SDMA3_CNTL__UTC_L1_ENABLE_MASK …
#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE_MASK …
#define SDMA3_CNTL__DATA_SWAP_ENABLE_MASK …
#define SDMA3_CNTL__FENCE_SWAP_ENABLE_MASK …
#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE_MASK …
#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK …
#define SDMA3_CNTL__AUTO_CTXSW_ENABLE_MASK …
#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE_MASK …
#define SDMA3_CNTL__FROZEN_INT_ENABLE_MASK …
#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE_MASK …
#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT …
#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT …
#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT …
#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT …
#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT …
#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT …
#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT …
#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT …
#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT …
#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS__SHIFT …
#define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT …
#define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT …
#define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT …
#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK …
#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK …
#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK …
#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK …
#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK …
#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK …
#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK …
#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK …
#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK …
#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS_MASK …
#define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK …
#define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK …
#define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK …
#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES__SHIFT …
#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT …
#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT …
#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS__SHIFT …
#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT …
#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES_MASK …
#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK …
#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK …
#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS_MASK …
#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK …
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT …
#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT …
#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT …
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT …
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT …
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK …
#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK …
#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK …
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK …
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK …
#define SDMA3_RB_RPTR_FETCH_HI__OFFSET__SHIFT …
#define SDMA3_RB_RPTR_FETCH_HI__OFFSET_MASK …
#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT …
#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK …
#define SDMA3_RB_RPTR_FETCH__OFFSET__SHIFT …
#define SDMA3_RB_RPTR_FETCH__OFFSET_MASK …
#define SDMA3_IB_OFFSET_FETCH__OFFSET__SHIFT …
#define SDMA3_IB_OFFSET_FETCH__OFFSET_MASK …
#define SDMA3_PROGRAM__STREAM__SHIFT …
#define SDMA3_PROGRAM__STREAM_MASK …
#define SDMA3_STATUS_REG__IDLE__SHIFT …
#define SDMA3_STATUS_REG__REG_IDLE__SHIFT …
#define SDMA3_STATUS_REG__RB_EMPTY__SHIFT …
#define SDMA3_STATUS_REG__RB_FULL__SHIFT …
#define SDMA3_STATUS_REG__RB_CMD_IDLE__SHIFT …
#define SDMA3_STATUS_REG__RB_CMD_FULL__SHIFT …
#define SDMA3_STATUS_REG__IB_CMD_IDLE__SHIFT …
#define SDMA3_STATUS_REG__IB_CMD_FULL__SHIFT …
#define SDMA3_STATUS_REG__BLOCK_IDLE__SHIFT …
#define SDMA3_STATUS_REG__INSIDE_IB__SHIFT …
#define SDMA3_STATUS_REG__EX_IDLE__SHIFT …
#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT …
#define SDMA3_STATUS_REG__PACKET_READY__SHIFT …
#define SDMA3_STATUS_REG__MC_WR_IDLE__SHIFT …
#define SDMA3_STATUS_REG__SRBM_IDLE__SHIFT …
#define SDMA3_STATUS_REG__CONTEXT_EMPTY__SHIFT …
#define SDMA3_STATUS_REG__DELTA_RPTR_FULL__SHIFT …
#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT …
#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT …
#define SDMA3_STATUS_REG__MC_RD_IDLE__SHIFT …
#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT …
#define SDMA3_STATUS_REG__MC_RD_RET_STALL__SHIFT …
#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT …
#define SDMA3_STATUS_REG__PREV_CMD_IDLE__SHIFT …
#define SDMA3_STATUS_REG__SEM_IDLE__SHIFT …
#define SDMA3_STATUS_REG__SEM_REQ_STALL__SHIFT …
#define SDMA3_STATUS_REG__SEM_RESP_STATE__SHIFT …
#define SDMA3_STATUS_REG__INT_IDLE__SHIFT …
#define SDMA3_STATUS_REG__INT_REQ_STALL__SHIFT …
#define SDMA3_STATUS_REG__IDLE_MASK …
#define SDMA3_STATUS_REG__REG_IDLE_MASK …
#define SDMA3_STATUS_REG__RB_EMPTY_MASK …
#define SDMA3_STATUS_REG__RB_FULL_MASK …
#define SDMA3_STATUS_REG__RB_CMD_IDLE_MASK …
#define SDMA3_STATUS_REG__RB_CMD_FULL_MASK …
#define SDMA3_STATUS_REG__IB_CMD_IDLE_MASK …
#define SDMA3_STATUS_REG__IB_CMD_FULL_MASK …
#define SDMA3_STATUS_REG__BLOCK_IDLE_MASK …
#define SDMA3_STATUS_REG__INSIDE_IB_MASK …
#define SDMA3_STATUS_REG__EX_IDLE_MASK …
#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK …
#define SDMA3_STATUS_REG__PACKET_READY_MASK …
#define SDMA3_STATUS_REG__MC_WR_IDLE_MASK …
#define SDMA3_STATUS_REG__SRBM_IDLE_MASK …
#define SDMA3_STATUS_REG__CONTEXT_EMPTY_MASK …
#define SDMA3_STATUS_REG__DELTA_RPTR_FULL_MASK …
#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE_MASK …
#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE_MASK …
#define SDMA3_STATUS_REG__MC_RD_IDLE_MASK …
#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY_MASK …
#define SDMA3_STATUS_REG__MC_RD_RET_STALL_MASK …
#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK …
#define SDMA3_STATUS_REG__PREV_CMD_IDLE_MASK …
#define SDMA3_STATUS_REG__SEM_IDLE_MASK …
#define SDMA3_STATUS_REG__SEM_REQ_STALL_MASK …
#define SDMA3_STATUS_REG__SEM_RESP_STATE_MASK …
#define SDMA3_STATUS_REG__INT_IDLE_MASK …
#define SDMA3_STATUS_REG__INT_REQ_STALL_MASK …
#define SDMA3_STATUS1_REG__CE_WREQ_IDLE__SHIFT …
#define SDMA3_STATUS1_REG__CE_WR_IDLE__SHIFT …
#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE__SHIFT …
#define SDMA3_STATUS1_REG__CE_RREQ_IDLE__SHIFT …
#define SDMA3_STATUS1_REG__CE_OUT_IDLE__SHIFT …
#define SDMA3_STATUS1_REG__CE_IN_IDLE__SHIFT …
#define SDMA3_STATUS1_REG__CE_DST_IDLE__SHIFT …
#define SDMA3_STATUS1_REG__CE_CMD_IDLE__SHIFT …
#define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT …
#define SDMA3_STATUS1_REG__CE_INFO_FULL__SHIFT …
#define SDMA3_STATUS1_REG__CE_INFO1_FULL__SHIFT …
#define SDMA3_STATUS1_REG__EX_START__SHIFT …
#define SDMA3_STATUS1_REG__CE_RD_STALL__SHIFT …
#define SDMA3_STATUS1_REG__CE_WR_STALL__SHIFT …
#define SDMA3_STATUS1_REG__CE_WREQ_IDLE_MASK …
#define SDMA3_STATUS1_REG__CE_WR_IDLE_MASK …
#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE_MASK …
#define SDMA3_STATUS1_REG__CE_RREQ_IDLE_MASK …
#define SDMA3_STATUS1_REG__CE_OUT_IDLE_MASK …
#define SDMA3_STATUS1_REG__CE_IN_IDLE_MASK …
#define SDMA3_STATUS1_REG__CE_DST_IDLE_MASK …
#define SDMA3_STATUS1_REG__CE_CMD_IDLE_MASK …
#define SDMA3_STATUS1_REG__CE_AFIFO_FULL_MASK …
#define SDMA3_STATUS1_REG__CE_INFO_FULL_MASK …
#define SDMA3_STATUS1_REG__CE_INFO1_FULL_MASK …
#define SDMA3_STATUS1_REG__EX_START_MASK …
#define SDMA3_STATUS1_REG__CE_RD_STALL_MASK …
#define SDMA3_STATUS1_REG__CE_WR_STALL_MASK …
#define SDMA3_RD_BURST_CNTL__RD_BURST__SHIFT …
#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT …
#define SDMA3_RD_BURST_CNTL__RD_BURST_MASK …
#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK …
#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT …
#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK …
#define SDMA3_UCODE_CHECKSUM__DATA__SHIFT …
#define SDMA3_UCODE_CHECKSUM__DATA_MASK …
#define SDMA3_F32_CNTL__HALT__SHIFT …
#define SDMA3_F32_CNTL__STEP__SHIFT …
#define SDMA3_F32_CNTL__HALT_MASK …
#define SDMA3_F32_CNTL__STEP_MASK …
#define SDMA3_FREEZE__PREEMPT__SHIFT …
#define SDMA3_FREEZE__FREEZE__SHIFT …
#define SDMA3_FREEZE__FROZEN__SHIFT …
#define SDMA3_FREEZE__F32_FREEZE__SHIFT …
#define SDMA3_FREEZE__PREEMPT_MASK …
#define SDMA3_FREEZE__FREEZE_MASK …
#define SDMA3_FREEZE__FROZEN_MASK …
#define SDMA3_FREEZE__F32_FREEZE_MASK …
#define SDMA3_PHASE0_QUANTUM__UNIT__SHIFT …
#define SDMA3_PHASE0_QUANTUM__VALUE__SHIFT …
#define SDMA3_PHASE0_QUANTUM__PREFER__SHIFT …
#define SDMA3_PHASE0_QUANTUM__UNIT_MASK …
#define SDMA3_PHASE0_QUANTUM__VALUE_MASK …
#define SDMA3_PHASE0_QUANTUM__PREFER_MASK …
#define SDMA3_PHASE1_QUANTUM__UNIT__SHIFT …
#define SDMA3_PHASE1_QUANTUM__VALUE__SHIFT …
#define SDMA3_PHASE1_QUANTUM__PREFER__SHIFT …
#define SDMA3_PHASE1_QUANTUM__UNIT_MASK …
#define SDMA3_PHASE1_QUANTUM__VALUE_MASK …
#define SDMA3_PHASE1_QUANTUM__PREFER_MASK …
#define SDMA3_EDC_CONFIG__DIS_EDC__SHIFT …
#define SDMA3_EDC_CONFIG__ECC_INT_ENABLE__SHIFT …
#define SDMA3_EDC_CONFIG__DIS_EDC_MASK …
#define SDMA3_EDC_CONFIG__ECC_INT_ENABLE_MASK …
#define SDMA3_BA_THRESHOLD__READ_THRES__SHIFT …
#define SDMA3_BA_THRESHOLD__WRITE_THRES__SHIFT …
#define SDMA3_BA_THRESHOLD__READ_THRES_MASK …
#define SDMA3_BA_THRESHOLD__WRITE_THRES_MASK …
#define SDMA3_ID__DEVICE_ID__SHIFT …
#define SDMA3_ID__DEVICE_ID_MASK …
#define SDMA3_VERSION__MINVER__SHIFT …
#define SDMA3_VERSION__MAJVER__SHIFT …
#define SDMA3_VERSION__REV__SHIFT …
#define SDMA3_VERSION__MINVER_MASK …
#define SDMA3_VERSION__MAJVER_MASK …
#define SDMA3_VERSION__REV_MASK …
#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT …
#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK …
#define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK …
#define SDMA3_EDC_COUNTER_CLEAR__DUMMY__SHIFT …
#define SDMA3_EDC_COUNTER_CLEAR__DUMMY_MASK …
#define SDMA3_STATUS2_REG__ID__SHIFT …
#define SDMA3_STATUS2_REG__F32_INSTR_PTR__SHIFT …
#define SDMA3_STATUS2_REG__CMD_OP__SHIFT …
#define SDMA3_STATUS2_REG__ID_MASK …
#define SDMA3_STATUS2_REG__F32_INSTR_PTR_MASK …
#define SDMA3_STATUS2_REG__CMD_OP_MASK …
#define SDMA3_ATOMIC_CNTL__LOOP_TIMER__SHIFT …
#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT …
#define SDMA3_ATOMIC_CNTL__LOOP_TIMER_MASK …
#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK …
#define SDMA3_ATOMIC_PREOP_LO__DATA__SHIFT …
#define SDMA3_ATOMIC_PREOP_LO__DATA_MASK …
#define SDMA3_ATOMIC_PREOP_HI__DATA__SHIFT …
#define SDMA3_ATOMIC_PREOP_HI__DATA_MASK …
#define SDMA3_UTCL1_CNTL__REDO_ENABLE__SHIFT …
#define SDMA3_UTCL1_CNTL__REDO_DELAY__SHIFT …
#define SDMA3_UTCL1_CNTL__REDO_WATERMK__SHIFT …
#define SDMA3_UTCL1_CNTL__INVACK_DELAY__SHIFT …
#define SDMA3_UTCL1_CNTL__REQL2_CREDIT__SHIFT …
#define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT …
#define SDMA3_UTCL1_CNTL__REDO_ENABLE_MASK …
#define SDMA3_UTCL1_CNTL__REDO_DELAY_MASK …
#define SDMA3_UTCL1_CNTL__REDO_WATERMK_MASK …
#define SDMA3_UTCL1_CNTL__INVACK_DELAY_MASK …
#define SDMA3_UTCL1_CNTL__REQL2_CREDIT_MASK …
#define SDMA3_UTCL1_CNTL__VADDR_WATERMK_MASK …
#define SDMA3_UTCL1_WATERMK__REQMC_WATERMK__SHIFT …
#define SDMA3_UTCL1_WATERMK__REQPG_WATERMK__SHIFT …
#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT …
#define SDMA3_UTCL1_WATERMK__XNACK_WATERMK__SHIFT …
#define SDMA3_UTCL1_WATERMK__REQMC_WATERMK_MASK …
#define SDMA3_UTCL1_WATERMK__REQPG_WATERMK_MASK …
#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK_MASK …
#define SDMA3_UTCL1_WATERMK__XNACK_WATERMK_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT …
#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK …
#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK …
#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK …
#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK …
#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK …
#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT_MASK …
#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_MASK …
#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE_MASK …
#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL_MASK …
#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK …
#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE_MASK …
#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK …
#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING_MASK …
#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT …
#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT_MASK …
#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE_MASK …
#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR_MASK …
#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK …
#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE_MASK …
#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK …
#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK …
#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK …
#define SDMA3_UTCL1_INV0__INV_MIDDLE__SHIFT …
#define SDMA3_UTCL1_INV0__RD_TIMEOUT__SHIFT …
#define SDMA3_UTCL1_INV0__WR_TIMEOUT__SHIFT …
#define SDMA3_UTCL1_INV0__RD_IN_INVADR__SHIFT …
#define SDMA3_UTCL1_INV0__WR_IN_INVADR__SHIFT …
#define SDMA3_UTCL1_INV0__PAGE_NULL_SW__SHIFT …
#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR__SHIFT …
#define SDMA3_UTCL1_INV0__INVREQ_ENABLE__SHIFT …
#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT …
#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT …
#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT …
#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE__SHIFT …
#define SDMA3_UTCL1_INV0__INV_VMID_VEC__SHIFT …
#define SDMA3_UTCL1_INV0__INV_ADDR_HI__SHIFT …
#define SDMA3_UTCL1_INV0__INV_MIDDLE_MASK …
#define SDMA3_UTCL1_INV0__RD_TIMEOUT_MASK …
#define SDMA3_UTCL1_INV0__WR_TIMEOUT_MASK …
#define SDMA3_UTCL1_INV0__RD_IN_INVADR_MASK …
#define SDMA3_UTCL1_INV0__WR_IN_INVADR_MASK …
#define SDMA3_UTCL1_INV0__PAGE_NULL_SW_MASK …
#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR_MASK …
#define SDMA3_UTCL1_INV0__INVREQ_ENABLE_MASK …
#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW_MASK …
#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE_MASK …
#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE_MASK …
#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE_MASK …
#define SDMA3_UTCL1_INV0__INV_VMID_VEC_MASK …
#define SDMA3_UTCL1_INV0__INV_ADDR_HI_MASK …
#define SDMA3_UTCL1_INV1__INV_ADDR_LO__SHIFT …
#define SDMA3_UTCL1_INV1__INV_ADDR_LO_MASK …
#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT …
#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK …
#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT …
#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK …
#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT …
#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT …
#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT …
#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK__SHIFT …
#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK …
#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID_MASK …
#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK …
#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK_MASK …
#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT …
#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK …
#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT …
#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT …
#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT …
#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK__SHIFT …
#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK …
#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID_MASK …
#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK …
#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK_MASK …
#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT …
#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT …
#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK …
#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK …
#define SDMA3_UTCL1_PAGE__VM_HOLE__SHIFT …
#define SDMA3_UTCL1_PAGE__REQ_TYPE__SHIFT …
#define SDMA3_UTCL1_PAGE__USE_MTYPE__SHIFT …
#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP__SHIFT …
#define SDMA3_UTCL1_PAGE__VM_HOLE_MASK …
#define SDMA3_UTCL1_PAGE__REQ_TYPE_MASK …
#define SDMA3_UTCL1_PAGE__USE_MTYPE_MASK …
#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP_MASK …
#define SDMA3_POWER_CNTL_IDLE__DELAY0__SHIFT …
#define SDMA3_POWER_CNTL_IDLE__DELAY1__SHIFT …
#define SDMA3_POWER_CNTL_IDLE__DELAY2__SHIFT …
#define SDMA3_POWER_CNTL_IDLE__DELAY0_MASK …
#define SDMA3_POWER_CNTL_IDLE__DELAY1_MASK …
#define SDMA3_POWER_CNTL_IDLE__DELAY2_MASK …
#define SDMA3_RELAX_ORDERING_LUT__RESERVED0__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__COPY__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__WRITE__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__RESERVED3__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__RESERVED4__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__FENCE__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__RESERVED76__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__COND_EXE__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__ATOMIC__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__PTEPDE__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__RESERVED__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH__SHIFT …
#define SDMA3_RELAX_ORDERING_LUT__RESERVED0_MASK …
#define SDMA3_RELAX_ORDERING_LUT__COPY_MASK …
#define SDMA3_RELAX_ORDERING_LUT__WRITE_MASK …
#define SDMA3_RELAX_ORDERING_LUT__RESERVED3_MASK …
#define SDMA3_RELAX_ORDERING_LUT__RESERVED4_MASK …
#define SDMA3_RELAX_ORDERING_LUT__FENCE_MASK …
#define SDMA3_RELAX_ORDERING_LUT__RESERVED76_MASK …
#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM_MASK …
#define SDMA3_RELAX_ORDERING_LUT__COND_EXE_MASK …
#define SDMA3_RELAX_ORDERING_LUT__ATOMIC_MASK …
#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL_MASK …
#define SDMA3_RELAX_ORDERING_LUT__PTEPDE_MASK …
#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP_MASK …
#define SDMA3_RELAX_ORDERING_LUT__RESERVED_MASK …
#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK …
#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB_MASK …
#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL_MASK …
#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH_MASK …
#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH_MASK …
#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT …
#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK …
#define SDMA3_STATUS3_REG__CMD_OP_STATUS__SHIFT …
#define SDMA3_STATUS3_REG__PREV_VM_CMD__SHIFT …
#define SDMA3_STATUS3_REG__EXCEPTION_IDLE__SHIFT …
#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH__SHIFT …
#define SDMA3_STATUS3_REG__INT_QUEUE_ID__SHIFT …
#define SDMA3_STATUS3_REG__CMD_OP_STATUS_MASK …
#define SDMA3_STATUS3_REG__PREV_VM_CMD_MASK …
#define SDMA3_STATUS3_REG__EXCEPTION_IDLE_MASK …
#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH_MASK …
#define SDMA3_STATUS3_REG__INT_QUEUE_ID_MASK …
#define SDMA3_PHYSICAL_ADDR_LO__D_VALID__SHIFT …
#define SDMA3_PHYSICAL_ADDR_LO__DIRTY__SHIFT …
#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT …
#define SDMA3_PHYSICAL_ADDR_LO__ADDR__SHIFT …
#define SDMA3_PHYSICAL_ADDR_LO__D_VALID_MASK …
#define SDMA3_PHYSICAL_ADDR_LO__DIRTY_MASK …
#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID_MASK …
#define SDMA3_PHYSICAL_ADDR_LO__ADDR_MASK …
#define SDMA3_PHYSICAL_ADDR_HI__ADDR__SHIFT …
#define SDMA3_PHYSICAL_ADDR_HI__ADDR_MASK …
#define SDMA3_PHASE2_QUANTUM__UNIT__SHIFT …
#define SDMA3_PHASE2_QUANTUM__VALUE__SHIFT …
#define SDMA3_PHASE2_QUANTUM__PREFER__SHIFT …
#define SDMA3_PHASE2_QUANTUM__UNIT_MASK …
#define SDMA3_PHASE2_QUANTUM__VALUE_MASK …
#define SDMA3_PHASE2_QUANTUM__PREFER_MASK …
#define SDMA3_ERROR_LOG__OVERRIDE__SHIFT …
#define SDMA3_ERROR_LOG__STATUS__SHIFT …
#define SDMA3_ERROR_LOG__OVERRIDE_MASK …
#define SDMA3_ERROR_LOG__STATUS_MASK …
#define SDMA3_PUB_DUMMY_REG0__VALUE__SHIFT …
#define SDMA3_PUB_DUMMY_REG0__VALUE_MASK …
#define SDMA3_PUB_DUMMY_REG1__VALUE__SHIFT …
#define SDMA3_PUB_DUMMY_REG1__VALUE_MASK …
#define SDMA3_PUB_DUMMY_REG2__VALUE__SHIFT …
#define SDMA3_PUB_DUMMY_REG2__VALUE_MASK …
#define SDMA3_PUB_DUMMY_REG3__VALUE__SHIFT …
#define SDMA3_PUB_DUMMY_REG3__VALUE_MASK …
#define SDMA3_F32_COUNTER__VALUE__SHIFT …
#define SDMA3_F32_COUNTER__VALUE_MASK …
#define SDMA3_UNBREAKABLE__VALUE__SHIFT …
#define SDMA3_UNBREAKABLE__VALUE_MASK …
#define SDMA3_PERFMON_CNTL__PERF_ENABLE0__SHIFT …
#define SDMA3_PERFMON_CNTL__PERF_CLEAR0__SHIFT …
#define SDMA3_PERFMON_CNTL__PERF_SEL0__SHIFT …
#define SDMA3_PERFMON_CNTL__PERF_ENABLE1__SHIFT …
#define SDMA3_PERFMON_CNTL__PERF_CLEAR1__SHIFT …
#define SDMA3_PERFMON_CNTL__PERF_SEL1__SHIFT …
#define SDMA3_PERFMON_CNTL__PERF_ENABLE0_MASK …
#define SDMA3_PERFMON_CNTL__PERF_CLEAR0_MASK …
#define SDMA3_PERFMON_CNTL__PERF_SEL0_MASK …
#define SDMA3_PERFMON_CNTL__PERF_ENABLE1_MASK …
#define SDMA3_PERFMON_CNTL__PERF_CLEAR1_MASK …
#define SDMA3_PERFMON_CNTL__PERF_SEL1_MASK …
#define SDMA3_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT …
#define SDMA3_PERFCOUNTER0_RESULT__PERF_COUNT_MASK …
#define SDMA3_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT …
#define SDMA3_PERFCOUNTER1_RESULT__PERF_COUNT_MASK …
#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT …
#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT …
#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT …
#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK …
#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK …
#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK …
#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT …
#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT …
#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT_MASK …
#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT_MASK …
#define SDMA3_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT …
#define SDMA3_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT …
#define SDMA3_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT …
#define SDMA3_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT …
#define SDMA3_GPU_IOV_VIOLATION_LOG__VF__SHIFT …
#define SDMA3_GPU_IOV_VIOLATION_LOG__VFID__SHIFT …
#define SDMA3_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK …
#define SDMA3_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK …
#define SDMA3_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK …
#define SDMA3_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK …
#define SDMA3_GPU_IOV_VIOLATION_LOG__VF_MASK …
#define SDMA3_GPU_IOV_VIOLATION_LOG__VFID_MASK …
#define SDMA3_ULV_CNTL__HYSTERESIS__SHIFT …
#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT …
#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT …
#define SDMA3_ULV_CNTL__ENTER_ULV_INT__SHIFT …
#define SDMA3_ULV_CNTL__EXIT_ULV_INT__SHIFT …
#define SDMA3_ULV_CNTL__ULV_STATUS__SHIFT …
#define SDMA3_ULV_CNTL__HYSTERESIS_MASK …
#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR_MASK …
#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR_MASK …
#define SDMA3_ULV_CNTL__ENTER_ULV_INT_MASK …
#define SDMA3_ULV_CNTL__EXIT_ULV_INT_MASK …
#define SDMA3_ULV_CNTL__ULV_STATUS_MASK …
#define SDMA3_EA_DBIT_ADDR_DATA__VALUE__SHIFT …
#define SDMA3_EA_DBIT_ADDR_DATA__VALUE_MASK …
#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE__SHIFT …
#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE_MASK …
#define SDMA3_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT …
#define SDMA3_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK …
#define SDMA3_GFX_RB_CNTL__RB_ENABLE__SHIFT …
#define SDMA3_GFX_RB_CNTL__RB_SIZE__SHIFT …
#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT …
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT …
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT …
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT …
#define SDMA3_GFX_RB_CNTL__RB_PRIV__SHIFT …
#define SDMA3_GFX_RB_CNTL__RB_VMID__SHIFT …
#define SDMA3_GFX_RB_CNTL__RB_ENABLE_MASK …
#define SDMA3_GFX_RB_CNTL__RB_SIZE_MASK …
#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK …
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK …
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK …
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK …
#define SDMA3_GFX_RB_CNTL__RB_PRIV_MASK …
#define SDMA3_GFX_RB_CNTL__RB_VMID_MASK …
#define SDMA3_GFX_RB_BASE__ADDR__SHIFT …
#define SDMA3_GFX_RB_BASE__ADDR_MASK …
#define SDMA3_GFX_RB_BASE_HI__ADDR__SHIFT …
#define SDMA3_GFX_RB_BASE_HI__ADDR_MASK …
#define SDMA3_GFX_RB_RPTR__OFFSET__SHIFT …
#define SDMA3_GFX_RB_RPTR__OFFSET_MASK …
#define SDMA3_GFX_RB_RPTR_HI__OFFSET__SHIFT …
#define SDMA3_GFX_RB_RPTR_HI__OFFSET_MASK …
#define SDMA3_GFX_RB_WPTR__OFFSET__SHIFT …
#define SDMA3_GFX_RB_WPTR__OFFSET_MASK …
#define SDMA3_GFX_RB_WPTR_HI__OFFSET__SHIFT …
#define SDMA3_GFX_RB_WPTR_HI__OFFSET_MASK …
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT …
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT …
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT …
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT …
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT …
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK …
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK …
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK …
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK …
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK …
#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT …
#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR_MASK …
#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT …
#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT …
#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK …
#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR_MASK …
#define SDMA3_GFX_IB_CNTL__IB_ENABLE__SHIFT …
#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT