linux/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

/*
 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef _vcn_3_0_0_SH_MASK_HEADER
#define _vcn_3_0_0_SH_MASK_HEADER

// addressBlock: uvd0_mmsch_dec
//MMSCH_UCODE_ADDR
#define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT
#define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT
#define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK
#define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK
//MMSCH_UCODE_DATA
#define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT
#define MMSCH_UCODE_DATA__UCODE_DATA_MASK
//MMSCH_SRAM_ADDR
#define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT
#define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT
#define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK
#define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK
//MMSCH_SRAM_DATA
#define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT
#define MMSCH_SRAM_DATA__SRAM_DATA_MASK
//MMSCH_VF_SRAM_OFFSET
#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT
#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT
#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK
#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK
//MMSCH_DB_SRAM_OFFSET
#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT
#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT
#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT
#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK
#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK
#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK
//MMSCH_CTX_SRAM_OFFSET
#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT
#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT
#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK
#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK
//MMSCH_CTL
#define MMSCH_CTL__P_RUNSTALL__SHIFT
#define MMSCH_CTL__P_RESET__SHIFT
#define MMSCH_CTL__VFID_FIFO_EN__SHIFT
#define MMSCH_CTL__P_LOCK__SHIFT
#define MMSCH_CTL__P_RUNSTALL_MASK
#define MMSCH_CTL__P_RESET_MASK
#define MMSCH_CTL__VFID_FIFO_EN_MASK
#define MMSCH_CTL__P_LOCK_MASK
//MMSCH_INTR
#define MMSCH_INTR__INTR__SHIFT
#define MMSCH_INTR__INTR_MASK
//MMSCH_INTR_ACK
#define MMSCH_INTR_ACK__INTR__SHIFT
#define MMSCH_INTR_ACK__INTR_MASK
//MMSCH_INTR_STATUS
#define MMSCH_INTR_STATUS__INTR__SHIFT
#define MMSCH_INTR_STATUS__INTR_MASK
//MMSCH_VF_VMID
#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT
#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT
#define MMSCH_VF_VMID__VF_CTX_VMID_MASK
#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK
//MMSCH_VF_CTX_ADDR_LO
#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT
#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK
//MMSCH_VF_CTX_ADDR_HI
#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT
#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK
//MMSCH_VF_CTX_SIZE
#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT
#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK
//MMSCH_VF_GPCOM_ADDR_LO
#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT
#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK
//MMSCH_VF_GPCOM_ADDR_HI
#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT
#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK
//MMSCH_VF_GPCOM_SIZE
#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT
#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK
//MMSCH_VF_MAILBOX_HOST
#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT
#define MMSCH_VF_MAILBOX_HOST__DATA_MASK
//MMSCH_VF_MAILBOX_RESP
#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT
#define MMSCH_VF_MAILBOX_RESP__RESP_MASK
//MMSCH_VF_MAILBOX_0
#define MMSCH_VF_MAILBOX_0__DATA__SHIFT
#define MMSCH_VF_MAILBOX_0__DATA_MASK
//MMSCH_VF_MAILBOX_0_RESP
#define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT
#define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK
//MMSCH_VF_MAILBOX_1
#define MMSCH_VF_MAILBOX_1__DATA__SHIFT
#define MMSCH_VF_MAILBOX_1__DATA_MASK
//MMSCH_VF_MAILBOX_1_RESP
#define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT
#define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK
//MMSCH_CNTL
#define MMSCH_CNTL__CLK_EN__SHIFT
#define MMSCH_CNTL__ED_ENABLE__SHIFT
#define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT
#define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT
#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT
#define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT
#define MMSCH_CNTL__TIMEOUT_DIS__SHIFT
#define MMSCH_CNTL__CLK_EN_MASK
#define MMSCH_CNTL__ED_ENABLE_MASK
#define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK
#define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK
#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK
#define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK
#define MMSCH_CNTL__TIMEOUT_DIS_MASK
//MMSCH_NONCACHE_OFFSET0
#define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT
#define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK
//MMSCH_NONCACHE_SIZE0
#define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT
#define MMSCH_NONCACHE_SIZE0__SIZE_MASK
//MMSCH_NONCACHE_OFFSET1
#define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT
#define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK
//MMSCH_NONCACHE_SIZE1
#define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT
#define MMSCH_NONCACHE_SIZE1__SIZE_MASK
//MMSCH_PROC_STATE1
#define MMSCH_PROC_STATE1__PC__SHIFT
#define MMSCH_PROC_STATE1__PC_MASK
//MMSCH_LAST_MC_ADDR
#define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT
#define MMSCH_LAST_MC_ADDR__RW__SHIFT
#define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK
#define MMSCH_LAST_MC_ADDR__RW_MASK
//MMSCH_LAST_MEM_ACCESS_HI
#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT
#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT
#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT
#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK
#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK
#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK
//MMSCH_LAST_MEM_ACCESS_LO
#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT
#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK
//MMSCH_IOV_ACTIVE_FCN_ID
#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT
#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT
#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK
#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK
//MMSCH_SCRATCH_0
#define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT
#define MMSCH_SCRATCH_0__SCRATCH_0_MASK
//MMSCH_SCRATCH_1
#define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT
#define MMSCH_SCRATCH_1__SCRATCH_1_MASK
//MMSCH_GPUIOV_SCH_BLOCK_0
#define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK
//MMSCH_GPUIOV_CMD_CONTROL_0
#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK
//MMSCH_GPUIOV_CMD_STATUS_0
#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT
#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK
//MMSCH_GPUIOV_VM_BUSY_STATUS_0
#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT
#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK
//MMSCH_GPUIOV_ACTIVE_FCNS_0
#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK
//MMSCH_GPUIOV_ACTIVE_FCN_ID_0
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK
//MMSCH_GPUIOV_DW6_0
#define MMSCH_GPUIOV_DW6_0__DATA__SHIFT
#define MMSCH_GPUIOV_DW6_0__DATA_MASK
//MMSCH_GPUIOV_DW7_0
#define MMSCH_GPUIOV_DW7_0__DATA__SHIFT
#define MMSCH_GPUIOV_DW7_0__DATA_MASK
//MMSCH_GPUIOV_DW8_0
#define MMSCH_GPUIOV_DW8_0__DATA__SHIFT
#define MMSCH_GPUIOV_DW8_0__DATA_MASK
//MMSCH_GPUIOV_SCH_BLOCK_1
#define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK
//MMSCH_GPUIOV_CMD_CONTROL_1
#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK
//MMSCH_GPUIOV_CMD_STATUS_1
#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT
#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK
//MMSCH_GPUIOV_VM_BUSY_STATUS_1
#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT
#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK
//MMSCH_GPUIOV_ACTIVE_FCNS_1
#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK
//MMSCH_GPUIOV_ACTIVE_FCN_ID_1
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK
//MMSCH_GPUIOV_DW6_1
#define MMSCH_GPUIOV_DW6_1__DATA__SHIFT
#define MMSCH_GPUIOV_DW6_1__DATA_MASK
//MMSCH_GPUIOV_DW7_1
#define MMSCH_GPUIOV_DW7_1__DATA__SHIFT
#define MMSCH_GPUIOV_DW7_1__DATA_MASK
//MMSCH_GPUIOV_DW8_1
#define MMSCH_GPUIOV_DW8_1__DATA__SHIFT
#define MMSCH_GPUIOV_DW8_1__DATA_MASK
//MMSCH_GPUIOV_CNTXT
#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT
#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT
#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT
#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK
#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK
#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK
//MMSCH_SCRATCH_2
#define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT
#define MMSCH_SCRATCH_2__SCRATCH_2_MASK
//MMSCH_SCRATCH_3
#define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT
#define MMSCH_SCRATCH_3__SCRATCH_3_MASK
//MMSCH_SCRATCH_4
#define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT
#define MMSCH_SCRATCH_4__SCRATCH_4_MASK
//MMSCH_SCRATCH_5
#define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT
#define MMSCH_SCRATCH_5__SCRATCH_5_MASK
//MMSCH_SCRATCH_6
#define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT
#define MMSCH_SCRATCH_6__SCRATCH_6_MASK
//MMSCH_SCRATCH_7
#define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT
#define MMSCH_SCRATCH_7__SCRATCH_7_MASK
//MMSCH_VFID_FIFO_HEAD_0
#define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT
#define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK
//MMSCH_VFID_FIFO_TAIL_0
#define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT
#define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK
//MMSCH_VFID_FIFO_HEAD_1
#define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT
#define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK
//MMSCH_VFID_FIFO_TAIL_1
#define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT
#define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK
//MMSCH_NACK_STATUS
#define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT
#define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT
#define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK
#define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK
//MMSCH_VF_MAILBOX0_DATA
#define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT
#define MMSCH_VF_MAILBOX0_DATA__DATA_MASK
//MMSCH_VF_MAILBOX1_DATA
#define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT
#define MMSCH_VF_MAILBOX1_DATA__DATA_MASK
//MMSCH_GPUIOV_SCH_BLOCK_IP_0
#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK
//MMSCH_GPUIOV_CMD_STATUS_IP_0
#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT
#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK
//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK
//MMSCH_GPUIOV_SCH_BLOCK_IP_1
#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK
//MMSCH_GPUIOV_CMD_STATUS_IP_1
#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT
#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK
//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK
//MMSCH_GPUIOV_CNTXT_IP
#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT
#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT
#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK
#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK
//MMSCH_GPUIOV_SCH_BLOCK_2
#define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK
//MMSCH_GPUIOV_CMD_CONTROL_2
#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT
#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK
#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK
//MMSCH_GPUIOV_CMD_STATUS_2
#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT
#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK
//MMSCH_GPUIOV_VM_BUSY_STATUS_2
#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT
#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK
//MMSCH_GPUIOV_ACTIVE_FCNS_2
#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK
//MMSCH_GPUIOV_ACTIVE_FCN_ID_2
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK
//MMSCH_GPUIOV_DW6_2
#define MMSCH_GPUIOV_DW6_2__DATA__SHIFT
#define MMSCH_GPUIOV_DW6_2__DATA_MASK
//MMSCH_GPUIOV_DW7_2
#define MMSCH_GPUIOV_DW7_2__DATA__SHIFT
#define MMSCH_GPUIOV_DW7_2__DATA_MASK
//MMSCH_GPUIOV_DW8_2
#define MMSCH_GPUIOV_DW8_2__DATA__SHIFT
#define MMSCH_GPUIOV_DW8_2__DATA_MASK
//MMSCH_GPUIOV_SCH_BLOCK_IP_2
#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT
#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK
#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK
//MMSCH_GPUIOV_CMD_STATUS_IP_2
#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT
#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK
//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK
#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK
//MMSCH_VFID_FIFO_HEAD_2
#define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT
#define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK
//MMSCH_VFID_FIFO_TAIL_2
#define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT
#define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK
//MMSCH_VM_BUSY_STATUS_0
#define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT
#define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK
//MMSCH_VM_BUSY_STATUS_1
#define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT
#define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK
//MMSCH_VM_BUSY_STATUS_2
#define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT
#define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK


// addressBlock: uvd0_jpegnpdec
//UVD_JPEG_CNTL
#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT
#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT
#define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT
#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT
#define UVD_JPEG_CNTL__REQUEST_EN_MASK
#define UVD_JPEG_CNTL__ERR_RST_EN_MASK
#define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK
#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK
//UVD_JPEG_RB_BASE
#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT
#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT
#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK
#define UVD_JPEG_RB_BASE__RB_BASE_MASK
//UVD_JPEG_RB_WPTR
#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT
#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK
//UVD_JPEG_RB_RPTR
#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT
#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK
//UVD_JPEG_RB_SIZE
#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT
#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK
//UVD_JPEG_DEC_CNT
#define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT
#define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK
//UVD_JPEG_SPS_INFO
#define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT
#define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT
#define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK
#define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK
//UVD_JPEG_SPS1_INFO
#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT
#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT
#define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT
#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK
#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK
#define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK
//UVD_JPEG_RE_TIMER
#define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT
#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT
#define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK
#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK
//UVD_JPEG_DEC_SCRATCH0
#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT
#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK
//UVD_JPEG_INT_EN
#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT
#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT
#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT
#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT
#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT
#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT
#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT
#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT
#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT
#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT
#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT
#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT
#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT
#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK
#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK
#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK
#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK
#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK
#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK
#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK
#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK
#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK
#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK
#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK
#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK
#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK
//UVD_JPEG_INT_STAT
#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT
#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT
#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT
#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT
#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT
#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT
#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT
#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT
#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT
#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT
#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT
#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT
#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT
#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK
#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK
#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK
#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK
#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK
#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK
#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK
#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK
#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK
#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK
#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK
#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK
#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK
//UVD_JPEG_TIER_CNTL0
#define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT
#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT
#define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT
#define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT
#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT
#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT
#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT
#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT
#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT
#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT
#define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT
#define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT
#define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT
#define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK
#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK
#define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK
#define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK
#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK
#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK
#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK
#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK
#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK
#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK
#define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK
#define UVD_JPEG_TIER_CNTL0__U_TQ_MASK
#define UVD_JPEG_TIER_CNTL0__V_TQ_MASK
//UVD_JPEG_TIER_CNTL1
#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT
#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT
#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK
#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK
//UVD_JPEG_TIER_CNTL2
#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT
#define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT
#define UVD_JPEG_TIER_CNTL2__TQ__SHIFT
#define UVD_JPEG_TIER_CNTL2__TH__SHIFT
#define UVD_JPEG_TIER_CNTL2__TC__SHIFT
#define UVD_JPEG_TIER_CNTL2__TD__SHIFT
#define UVD_JPEG_TIER_CNTL2__TA__SHIFT
#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT
#define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT
#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK
#define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK
#define UVD_JPEG_TIER_CNTL2__TQ_MASK
#define UVD_JPEG_TIER_CNTL2__TH_MASK
#define UVD_JPEG_TIER_CNTL2__TC_MASK
#define UVD_JPEG_TIER_CNTL2__TD_MASK
#define UVD_JPEG_TIER_CNTL2__TA_MASK
#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK
#define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK
//UVD_JPEG_TIER_STATUS
#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT
#define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT
#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK
#define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK
//UVD_JPEG_OUTBUF_CNTL
#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT
#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT
#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT
#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT
#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT
#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK
#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK
#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK
#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK
#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK
//UVD_JPEG_OUTBUF_WPTR
#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT
#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK
//UVD_JPEG_OUTBUF_RPTR
#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT
#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK
//UVD_JPEG_PITCH
#define UVD_JPEG_PITCH__PITCH__SHIFT
#define UVD_JPEG_PITCH__PITCH_MASK
//UVD_JPEG_UV_PITCH
#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT
#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK
//JPEG_DEC_Y_GFX10_TILING_SURFACE
#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT
#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK
//JPEG_DEC_UV_GFX10_TILING_SURFACE
#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT
#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK
//JPEG_DEC_GFX10_ADDR_CONFIG
#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT
#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT
#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT
#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK
#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK
#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK
#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
//JPEG_DEC_ADDR_MODE
#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT
#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT
#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT
#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK
#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK
#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK
//UVD_JPEG_OUTPUT_XY
#define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT
#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT
#define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK
#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK
//UVD_JPEG_GPCOM_CMD
#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT
#define UVD_JPEG_GPCOM_CMD__CMD_MASK
//UVD_JPEG_GPCOM_DATA0
#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT
#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK
//UVD_JPEG_GPCOM_DATA1
#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT
#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK
//UVD_JPEG_INDEX
#define UVD_JPEG_INDEX__INDEX__SHIFT
#define UVD_JPEG_INDEX__INDEX_MASK
//UVD_JPEG_DATA
#define UVD_JPEG_DATA__DATA__SHIFT
#define UVD_JPEG_DATA__DATA_MASK
//UVD_JPEG_SCRATCH1
#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT
#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK
//UVD_JPEG_DEC_SOFT_RST
#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT
#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT
#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK
#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK


// addressBlock: uvd0_uvd_jpeg_enc_dec
//UVD_JPEG_ENC_ECS_VALID_BYTES
#define UVD_JPEG_ENC_ECS_VALID_BYTES__TOTAL_NUM_BYTES__SHIFT
#define UVD_JPEG_ENC_ECS_VALID_BYTES__TOTAL_NUM_BYTES_MASK
//UVD_JPEG_ENC_INT_EN
#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT
#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT
#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT
#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT
#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT
#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT
#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT
#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK
#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK
#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK
#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK
#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK
#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK
#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK
//UVD_JPEG_ENC_INT_STATUS
#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT
#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT
#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT
#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT
#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT
#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT
#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT
#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK
#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK
#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK
#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK
#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK
#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK
#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK
//UVD_JPEG_ENC_PEL_CNTL
#define UVD_JPEG_ENC_PEL_CNTL__LUMA_PAD_DATA__SHIFT
#define UVD_JPEG_ENC_PEL_CNTL__CHROMAU_PAD_DATA__SHIFT
#define UVD_JPEG_ENC_PEL_CNTL__CHROMAV_PAD_DATA__SHIFT
#define UVD_JPEG_ENC_PEL_CNTL__USER_MODE_SEL__SHIFT
#define UVD_JPEG_ENC_PEL_CNTL__LUMA_PAD_DATA_MASK
#define UVD_JPEG_ENC_PEL_CNTL__CHROMAU_PAD_DATA_MASK
#define UVD_JPEG_ENC_PEL_CNTL__CHROMAV_PAD_DATA_MASK
#define UVD_JPEG_ENC_PEL_CNTL__USER_MODE_SEL_MASK
//UVD_JPEG_ENC_RESTART_MARKER_CNTL
#define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_INTERVAL__SHIFT
#define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_MARKER_ENABLE__SHIFT
#define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_INTERVAL_MASK
#define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_MARKER_ENABLE_MASK
//UVD_JPEG_ENC_ENGINE_CNTL
#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT
#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT
#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT
#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT
#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT
#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT
#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK
#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK
#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK
#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK
#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK
#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK
//UVD_JPEG_ENC_SCALAR_DST_IMG_INFO
#define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_WIDTH__SHIFT
#define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_HEIGHT__SHIFT
#define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_WIDTH_MASK
#define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_HEIGHT_MASK
//UVD_JPEG_ENC_HUFF_TBL
#define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_DATA__SHIFT
#define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_ADDR__SHIFT
#define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_WRITE__SHIFT
#define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_DATA_MASK
#define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_ADDR_MASK
#define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_WRITE_MASK
//UVD_JPEG_ENC_HUFF_TBL_RDATA
#define UVD_JPEG_ENC_HUFF_TBL_RDATA__HUFF_TBL_RDATA__SHIFT
#define UVD_JPEG_ENC_HUFF_TBL_RDATA__HUFF_TBL_RDATA_MASK
//UVD_JPEG_ENC_QUANT_TBL
#define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_READ__SHIFT
#define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_ADDR__SHIFT
#define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_IDX__SHIFT
#define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_READ_MASK
#define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_ADDR_MASK
#define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_IDX_MASK
//UVD_JPEG_ENC_QUANT_TBL_RDATA
#define UVD_JPEG_ENC_QUANT_TBL_RDATA__QUANT_TBL_RDATA__SHIFT
#define UVD_JPEG_ENC_QUANT_TBL_RDATA__QUANT_TBL_RDATA_MASK
//UVD_JPEG_ENC_SCLR_CHROMAU_OFFSET
#define UVD_JPEG_ENC_SCLR_CHROMAU_OFFSET__SCLR_CHROMAU_OFFSET__SHIFT
#define UVD_JPEG_ENC_SCLR_CHROMAU_OFFSET__SCLR_CHROMAU_OFFSET_MASK
//UVD_JPEG_ENC_SCLR_CHROMAV_OFFSET
#define UVD_JPEG_ENC_SCLR_CHROMAV_OFFSET__SCLR_CHROMAV_OFFSET__SHIFT
#define UVD_JPEG_ENC_SCLR_CHROMAV_OFFSET__SCLR_CHROMAV_OFFSET_MASK
//UVD_JPEG_ENC_SCLR_PITCH
#define UVD_JPEG_ENC_SCLR_PITCH__PITCH__SHIFT
#define UVD_JPEG_ENC_SCLR_PITCH__PITCH_MASK
//UVD_JPEG_ENC_SCRATCH1
#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT
#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK


// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
//UVD_JPEG_ENC_SPS_INFO
#define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT__SHIFT
#define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT__SHIFT
#define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422__SHIFT
#define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT_MASK
#define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT_MASK
#define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422_MASK
//UVD_JPEG_ENC_SPS_INFO1
#define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH__SHIFT
#define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT__SHIFT
#define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH_MASK
#define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT_MASK
//UVD_JPEG_ENC_TBL_SIZE
#define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE__SHIFT
#define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE_MASK
//UVD_JPEG_ENC_TBL_CNTL
#define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL__SHIFT
#define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE__SHIFT
#define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE__SHIFT
#define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN__SHIFT
#define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL_MASK
#define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE_MASK
#define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE_MASK
#define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN_MASK
//UVD_JPEG_ENC_MC_REQ_CNTL
#define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK__SHIFT
#define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK_MASK
//UVD_JPEG_ENC_STATUS
#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT
#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT
#define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT
#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT
#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK
#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK
#define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK
#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK
//UVD_JPEG_ENC_PITCH
#define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT
#define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT
#define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK
#define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK
//UVD_JPEG_ENC_LUMA_BASE
#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT
#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK
//UVD_JPEG_ENC_CHROMAU_BASE
#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT
#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK
//UVD_JPEG_ENC_CHROMAV_BASE
#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT
#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK
//JPEG_ENC_Y_GFX10_TILING_SURFACE
#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT
#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK
//JPEG_ENC_UV_GFX10_TILING_SURFACE
#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT
#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK
//JPEG_ENC_GFX10_ADDR_CONFIG
#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT
#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT
#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT
#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK
#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK
#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK
#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
//JPEG_ENC_ADDR_MODE
#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT
#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT
#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT
#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK
#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK
#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK
//UVD_JPEG_ENC_GPCOM_CMD
#define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT
#define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK
//UVD_JPEG_ENC_GPCOM_DATA0
#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT
#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK
//UVD_JPEG_ENC_GPCOM_DATA1
#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT
#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK
//UVD_JPEG_TBL_DAT0
#define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0__SHIFT
#define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0_MASK
//UVD_JPEG_TBL_DAT1
#define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32__SHIFT
#define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32_MASK
//UVD_JPEG_TBL_IDX
#define UVD_JPEG_TBL_IDX__TBL_IDX__SHIFT
#define UVD_JPEG_TBL_IDX__TBL_IDX_MASK
//UVD_JPEG_ENC_CGC_CNTL
#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT
#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK
//UVD_JPEG_ENC_SCRATCH0
#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT
#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK
//UVD_JPEG_ENC_SOFT_RST
#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT
#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT
#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK
#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK


// addressBlock: uvd0_uvd_jrbc_dec
//UVD_JRBC_RB_WPTR
#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT
#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK
//UVD_JRBC_RB_CNTL
#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT
#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT
#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT
#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK
#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK
#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK
//UVD_JRBC_IB_SIZE
#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT
#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK
//UVD_JRBC_URGENT_CNTL
#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT
#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK
//UVD_JRBC_RB_REF_DATA
#define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT
#define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK
//UVD_JRBC_RB_COND_RD_TIMER
#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT
#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT
#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT
#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT
#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK
#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK
#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK
#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK
//UVD_JRBC_SOFT_RESET
#define UVD_JRBC_SOFT_RESET__RESET__SHIFT
#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT
#define UVD_JRBC_SOFT_RESET__RESET_MASK
#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK
//UVD_JRBC_STATUS
#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT
#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT
#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT
#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT
#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT
#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT
#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT
#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT
#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT
#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT
#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT
#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT
#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT
#define UVD_JRBC_STATUS__INT_EN__SHIFT
#define UVD_JRBC_STATUS__INT_ACK__SHIFT
#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK
#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK
#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK
#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK
#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK
#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK
#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK
#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK
#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK
#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK
#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK
#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK
#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK
#define UVD_JRBC_STATUS__INT_EN_MASK
#define UVD_JRBC_STATUS__INT_ACK_MASK
//UVD_JRBC_RB_RPTR
#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT
#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK
//UVD_JRBC_RB_BUF_STATUS
#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT
#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT
#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT
#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK
#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK
#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK
//UVD_JRBC_IB_BUF_STATUS
#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT
#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT
#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT
#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK
#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK
#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK
//UVD_JRBC_IB_SIZE_UPDATE
#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT
#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK
//UVD_JRBC_IB_COND_RD_TIMER
#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT
#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT
#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT
#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT
#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK
#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK
#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK
#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK
//UVD_JRBC_IB_REF_DATA
#define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT
#define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK
//UVD_JPEG_PREEMPT_CMD
#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT
#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT
#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT
#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK
#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK
#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK
//UVD_JPEG_PREEMPT_FENCE_DATA0
#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT
#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK
//UVD_JPEG_PREEMPT_FENCE_DATA1
#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT
#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK
//UVD_JRBC_RB_SIZE
#define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT
#define UVD_JRBC_RB_SIZE__RB_SIZE_MASK
//UVD_JRBC_SCRATCH0
#define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT
#define UVD_JRBC_SCRATCH0__SCRATCH0_MASK


// addressBlock: uvd0_uvd_jrbc_enc_dec
//UVD_JRBC_ENC_RB_WPTR
#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT
#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK
//UVD_JRBC_ENC_RB_CNTL
#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT
#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT
#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT
#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK
#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK
#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK
//UVD_JRBC_ENC_IB_SIZE
#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT
#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK
//UVD_JRBC_ENC_URGENT_CNTL
#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT
#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK
//UVD_JRBC_ENC_RB_REF_DATA
#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT
#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK
//UVD_JRBC_ENC_RB_COND_RD_TIMER
#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT
#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT
#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT
#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT
#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK
#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK
#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK
#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK
//UVD_JRBC_ENC_SOFT_RESET
#define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT
#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT
#define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK
#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK
//UVD_JRBC_ENC_STATUS
#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT
#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT
#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT
#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT
#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT
#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT
#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT
#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT
#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT
#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT
#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT
#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT
#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT
#define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT
#define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT
#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK
#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK
#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK
#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK
#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK
#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK
#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK
#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK
#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK
#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK
#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK
#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK
#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK
#define UVD_JRBC_ENC_STATUS__INT_EN_MASK
#define UVD_JRBC_ENC_STATUS__INT_ACK_MASK
//UVD_JRBC_ENC_RB_RPTR
#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT
#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK
//UVD_JRBC_ENC_RB_BUF_STATUS
#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT
#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT
#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT
#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK
#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK
#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK
//UVD_JRBC_ENC_IB_BUF_STATUS
#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT
#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT
#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT
#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK
#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK
#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK
//UVD_JRBC_ENC_IB_SIZE_UPDATE
#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT
#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK
//UVD_JRBC_ENC_IB_COND_RD_TIMER
#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT
#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT
#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT
#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT
#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK
#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK
#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK
#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK
//UVD_JRBC_ENC_IB_REF_DATA
#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT
#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK
//UVD_JPEG_ENC_PREEMPT_CMD
#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT
#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT
#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT
#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK
#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK
#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK
//UVD_JPEG_ENC_PREEMPT_FENCE_DATA0
#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT
#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK
//UVD_JPEG_ENC_PREEMPT_FENCE_DATA1
#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT
#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK
//UVD_JRBC_ENC_RB_SIZE
#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT
#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK
//UVD_JRBC_ENC_SCRATCH0
#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT
#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK


// addressBlock: uvd0_uvd_jmi_dec
//UVD_JADP_MCIF_URGENT_CTRL
#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT
#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT
#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT
#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT
#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT
#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT
#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT
#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK
#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK
#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK
#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK
#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK
#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK
#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK
//UVD_JMI_URGENT_CTRL
#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT
#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT
#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT
#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT
#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK
#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK
#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK
#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK
//UVD_JPEG_DEC_PF_CTRL
#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT
#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT
#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK
#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK
//UVD_JPEG_ENC_PF_CTRL
#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS__SHIFT
#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING__SHIFT
#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS_MASK
#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING_MASK
//UVD_JMI_CTRL
#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT
#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT
#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT
#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT
#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT
#define UVD_JMI_CTRL__CRC_RESET__SHIFT
#define UVD_JMI_CTRL__CRC_SEL__SHIFT
#define UVD_JMI_CTRL__STALL_MC_ARB_MASK
#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK
#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK
#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK
#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK
#define UVD_JMI_CTRL__CRC_RESET_MASK
#define UVD_JMI_CTRL__CRC_SEL_MASK
//UVD_LMI_JRBC_CTRL
#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT
#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT
#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT
#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT
#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT
#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT
#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK
#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK
#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK
#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK
#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK
#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK
//UVD_LMI_JPEG_CTRL
#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT
#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT
#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT
#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT
#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT
#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT
#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK
#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK
#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK
#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK
#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK
#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK
//UVD_JMI_EJRBC_CTRL
#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT
#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT
#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT
#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT
#define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT
#define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT
#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK
#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK
#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK
#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK
#define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK
#define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK
//UVD_LMI_EJPEG_CTRL
#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT
#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT
#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT
#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT
#define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT
#define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT
#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK
#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK
#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK
#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK
#define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK
#define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK
//UVD_JMI_SCALER_CTRL
#define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN__SHIFT
#define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN__SHIFT
#define UVD_JMI_SCALER_CTRL__RD_MAX_BURST__SHIFT
#define UVD_JMI_SCALER_CTRL__WR_MAX_BURST__SHIFT
#define UVD_JMI_SCALER_CTRL__RD_SWAP__SHIFT
#define UVD_JMI_SCALER_CTRL__WR_SWAP__SHIFT
#define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN_MASK
#define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN_MASK
#define UVD_JMI_SCALER_CTRL__RD_MAX_BURST_MASK
#define UVD_JMI_SCALER_CTRL__WR_MAX_BURST_MASK
#define UVD_JMI_SCALER_CTRL__RD_SWAP_MASK
#define UVD_JMI_SCALER_CTRL__WR_SWAP_MASK
//JPEG_LMI_DROP
#define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT
#define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT
#define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT
#define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT
#define JPEG_LMI_DROP__JPEG_WR_DROP_MASK
#define JPEG_LMI_DROP__JRBC_WR_DROP_MASK
#define JPEG_LMI_DROP__JPEG_RD_DROP_MASK
#define JPEG_LMI_DROP__JRBC_RD_DROP_MASK
//UVD_JMI_EJPEG_DROP
#define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP__SHIFT
#define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP__SHIFT
#define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP__SHIFT
#define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP__SHIFT
#define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP__SHIFT
#define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT
#define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP_MASK
#define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP_MASK
#define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP_MASK
#define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP_MASK
#define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP_MASK
#define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP_MASK
//JPEG_MEMCHECK_CLAMPING
#define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT
#define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN__SHIFT
#define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT
#define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN__SHIFT
#define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT
#define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT
#define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT
#define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK
#define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN_MASK
#define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK
#define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN_MASK
#define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK
#define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK
#define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK
//UVD_JMI_EJPEG_MEMCHECK_CLAMPING
#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT
#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT
#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT
#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT
#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN__SHIFT
#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT
#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT
#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK
#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK