linux/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef _vcn_4_0_5_SH_MASK_HEADER
#define _vcn_4_0_5_SH_MASK_HEADER


// addressBlock: uvd_uvddec
//UVD_CGC_GATE
#define UVD_CGC_GATE__SYS__SHIFT
#define UVD_CGC_GATE__UDEC__SHIFT
#define UVD_CGC_GATE__MPEG2__SHIFT
#define UVD_CGC_GATE__REGS__SHIFT
#define UVD_CGC_GATE__RBC__SHIFT
#define UVD_CGC_GATE__LMI_MC__SHIFT
#define UVD_CGC_GATE__LMI_UMC__SHIFT
#define UVD_CGC_GATE__IDCT__SHIFT
#define UVD_CGC_GATE__MPRD__SHIFT
#define UVD_CGC_GATE__MPC__SHIFT
#define UVD_CGC_GATE__LBSI__SHIFT
#define UVD_CGC_GATE__LRBBM__SHIFT
#define UVD_CGC_GATE__UDEC_RE__SHIFT
#define UVD_CGC_GATE__UDEC_CM__SHIFT
#define UVD_CGC_GATE__UDEC_IT__SHIFT
#define UVD_CGC_GATE__UDEC_DB__SHIFT
#define UVD_CGC_GATE__UDEC_MP__SHIFT
#define UVD_CGC_GATE__WCB__SHIFT
#define UVD_CGC_GATE__VCPU__SHIFT
#define UVD_CGC_GATE__MMSCH__SHIFT
#define UVD_CGC_GATE__LCM0__SHIFT
#define UVD_CGC_GATE__LCM1__SHIFT
#define UVD_CGC_GATE__MIF__SHIFT
#define UVD_CGC_GATE__VREG__SHIFT
#define UVD_CGC_GATE__PE__SHIFT
#define UVD_CGC_GATE__PPU__SHIFT
#define UVD_CGC_GATE__SYS_MASK
#define UVD_CGC_GATE__UDEC_MASK
#define UVD_CGC_GATE__MPEG2_MASK
#define UVD_CGC_GATE__REGS_MASK
#define UVD_CGC_GATE__RBC_MASK
#define UVD_CGC_GATE__LMI_MC_MASK
#define UVD_CGC_GATE__LMI_UMC_MASK
#define UVD_CGC_GATE__IDCT_MASK
#define UVD_CGC_GATE__MPRD_MASK
#define UVD_CGC_GATE__MPC_MASK
#define UVD_CGC_GATE__LBSI_MASK
#define UVD_CGC_GATE__LRBBM_MASK
#define UVD_CGC_GATE__UDEC_RE_MASK
#define UVD_CGC_GATE__UDEC_CM_MASK
#define UVD_CGC_GATE__UDEC_IT_MASK
#define UVD_CGC_GATE__UDEC_DB_MASK
#define UVD_CGC_GATE__UDEC_MP_MASK
#define UVD_CGC_GATE__WCB_MASK
#define UVD_CGC_GATE__VCPU_MASK
#define UVD_CGC_GATE__MMSCH_MASK
#define UVD_CGC_GATE__LCM0_MASK
#define UVD_CGC_GATE__LCM1_MASK
#define UVD_CGC_GATE__MIF_MASK
#define UVD_CGC_GATE__VREG_MASK
#define UVD_CGC_GATE__PE_MASK
#define UVD_CGC_GATE__PPU_MASK
//UVD_CGC_CTRL
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT
#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT
#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT
#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT
#define UVD_CGC_CTRL__SYS_MODE__SHIFT
#define UVD_CGC_CTRL__UDEC_MODE__SHIFT
#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT
#define UVD_CGC_CTRL__REGS_MODE__SHIFT
#define UVD_CGC_CTRL__RBC_MODE__SHIFT
#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT
#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT
#define UVD_CGC_CTRL__IDCT_MODE__SHIFT
#define UVD_CGC_CTRL__MPRD_MODE__SHIFT
#define UVD_CGC_CTRL__MPC_MODE__SHIFT
#define UVD_CGC_CTRL__LBSI_MODE__SHIFT
#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT
#define UVD_CGC_CTRL__WCB_MODE__SHIFT
#define UVD_CGC_CTRL__VCPU_MODE__SHIFT
#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT
#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK
#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK
#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK
#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK
#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK
#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK
#define UVD_CGC_CTRL__SYS_MODE_MASK
#define UVD_CGC_CTRL__UDEC_MODE_MASK
#define UVD_CGC_CTRL__MPEG2_MODE_MASK
#define UVD_CGC_CTRL__REGS_MODE_MASK
#define UVD_CGC_CTRL__RBC_MODE_MASK
#define UVD_CGC_CTRL__LMI_MC_MODE_MASK
#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK
#define UVD_CGC_CTRL__IDCT_MODE_MASK
#define UVD_CGC_CTRL__MPRD_MODE_MASK
#define UVD_CGC_CTRL__MPC_MODE_MASK
#define UVD_CGC_CTRL__LBSI_MODE_MASK
#define UVD_CGC_CTRL__LRBBM_MODE_MASK
#define UVD_CGC_CTRL__WCB_MODE_MASK
#define UVD_CGC_CTRL__VCPU_MODE_MASK
#define UVD_CGC_CTRL__MMSCH_MODE_MASK
//AVM_SUVD_CGC_GATE
#define AVM_SUVD_CGC_GATE__SRE__SHIFT
#define AVM_SUVD_CGC_GATE__SIT__SHIFT
#define AVM_SUVD_CGC_GATE__SMP__SHIFT
#define AVM_SUVD_CGC_GATE__SCM__SHIFT
#define AVM_SUVD_CGC_GATE__SDB__SHIFT
#define AVM_SUVD_CGC_GATE__SRE_H264__SHIFT
#define AVM_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define AVM_SUVD_CGC_GATE__SIT_H264__SHIFT
#define AVM_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define AVM_SUVD_CGC_GATE__SCM_H264__SHIFT
#define AVM_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define AVM_SUVD_CGC_GATE__SDB_H264__SHIFT
#define AVM_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define AVM_SUVD_CGC_GATE__SCLR__SHIFT
#define AVM_SUVD_CGC_GATE__UVD_SC__SHIFT
#define AVM_SUVD_CGC_GATE__ENT__SHIFT
#define AVM_SUVD_CGC_GATE__IME__SHIFT
#define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define AVM_SUVD_CGC_GATE__SITE__SHIFT
#define AVM_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define AVM_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define AVM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define AVM_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define AVM_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define AVM_SUVD_CGC_GATE__EFC__SHIFT
#define AVM_SUVD_CGC_GATE__SAOE__SHIFT
#define AVM_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define AVM_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define AVM_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define AVM_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define AVM_SUVD_CGC_GATE__SMPA__SHIFT
#define AVM_SUVD_CGC_GATE__SRE_MASK
#define AVM_SUVD_CGC_GATE__SIT_MASK
#define AVM_SUVD_CGC_GATE__SMP_MASK
#define AVM_SUVD_CGC_GATE__SCM_MASK
#define AVM_SUVD_CGC_GATE__SDB_MASK
#define AVM_SUVD_CGC_GATE__SRE_H264_MASK
#define AVM_SUVD_CGC_GATE__SRE_HEVC_MASK
#define AVM_SUVD_CGC_GATE__SIT_H264_MASK
#define AVM_SUVD_CGC_GATE__SIT_HEVC_MASK
#define AVM_SUVD_CGC_GATE__SCM_H264_MASK
#define AVM_SUVD_CGC_GATE__SCM_HEVC_MASK
#define AVM_SUVD_CGC_GATE__SDB_H264_MASK
#define AVM_SUVD_CGC_GATE__SDB_HEVC_MASK
#define AVM_SUVD_CGC_GATE__SCLR_MASK
#define AVM_SUVD_CGC_GATE__UVD_SC_MASK
#define AVM_SUVD_CGC_GATE__ENT_MASK
#define AVM_SUVD_CGC_GATE__IME_MASK
#define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define AVM_SUVD_CGC_GATE__SITE_MASK
#define AVM_SUVD_CGC_GATE__SRE_VP9_MASK
#define AVM_SUVD_CGC_GATE__SCM_VP9_MASK
#define AVM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define AVM_SUVD_CGC_GATE__SDB_VP9_MASK
#define AVM_SUVD_CGC_GATE__IME_HEVC_MASK
#define AVM_SUVD_CGC_GATE__EFC_MASK
#define AVM_SUVD_CGC_GATE__SAOE_MASK
#define AVM_SUVD_CGC_GATE__SRE_AV1_MASK
#define AVM_SUVD_CGC_GATE__FBC_PCLK_MASK
#define AVM_SUVD_CGC_GATE__FBC_CCLK_MASK
#define AVM_SUVD_CGC_GATE__SCM_AV1_MASK
#define AVM_SUVD_CGC_GATE__SMPA_MASK
//CDEFE_SUVD_CGC_GATE
#define CDEFE_SUVD_CGC_GATE__SRE__SHIFT
#define CDEFE_SUVD_CGC_GATE__SIT__SHIFT
#define CDEFE_SUVD_CGC_GATE__SMP__SHIFT
#define CDEFE_SUVD_CGC_GATE__SCM__SHIFT
#define CDEFE_SUVD_CGC_GATE__SDB__SHIFT
#define CDEFE_SUVD_CGC_GATE__SRE_H264__SHIFT
#define CDEFE_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define CDEFE_SUVD_CGC_GATE__SIT_H264__SHIFT
#define CDEFE_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define CDEFE_SUVD_CGC_GATE__SCM_H264__SHIFT
#define CDEFE_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define CDEFE_SUVD_CGC_GATE__SDB_H264__SHIFT
#define CDEFE_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define CDEFE_SUVD_CGC_GATE__SCLR__SHIFT
#define CDEFE_SUVD_CGC_GATE__UVD_SC__SHIFT
#define CDEFE_SUVD_CGC_GATE__ENT__SHIFT
#define CDEFE_SUVD_CGC_GATE__IME__SHIFT
#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define CDEFE_SUVD_CGC_GATE__SITE__SHIFT
#define CDEFE_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define CDEFE_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define CDEFE_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define CDEFE_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define CDEFE_SUVD_CGC_GATE__EFC__SHIFT
#define CDEFE_SUVD_CGC_GATE__SAOE__SHIFT
#define CDEFE_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define CDEFE_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define CDEFE_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define CDEFE_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define CDEFE_SUVD_CGC_GATE__SMPA__SHIFT
#define CDEFE_SUVD_CGC_GATE__SRE_MASK
#define CDEFE_SUVD_CGC_GATE__SIT_MASK
#define CDEFE_SUVD_CGC_GATE__SMP_MASK
#define CDEFE_SUVD_CGC_GATE__SCM_MASK
#define CDEFE_SUVD_CGC_GATE__SDB_MASK
#define CDEFE_SUVD_CGC_GATE__SRE_H264_MASK
#define CDEFE_SUVD_CGC_GATE__SRE_HEVC_MASK
#define CDEFE_SUVD_CGC_GATE__SIT_H264_MASK
#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_MASK
#define CDEFE_SUVD_CGC_GATE__SCM_H264_MASK
#define CDEFE_SUVD_CGC_GATE__SCM_HEVC_MASK
#define CDEFE_SUVD_CGC_GATE__SDB_H264_MASK
#define CDEFE_SUVD_CGC_GATE__SDB_HEVC_MASK
#define CDEFE_SUVD_CGC_GATE__SCLR_MASK
#define CDEFE_SUVD_CGC_GATE__UVD_SC_MASK
#define CDEFE_SUVD_CGC_GATE__ENT_MASK
#define CDEFE_SUVD_CGC_GATE__IME_MASK
#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define CDEFE_SUVD_CGC_GATE__SITE_MASK
#define CDEFE_SUVD_CGC_GATE__SRE_VP9_MASK
#define CDEFE_SUVD_CGC_GATE__SCM_VP9_MASK
#define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define CDEFE_SUVD_CGC_GATE__SDB_VP9_MASK
#define CDEFE_SUVD_CGC_GATE__IME_HEVC_MASK
#define CDEFE_SUVD_CGC_GATE__EFC_MASK
#define CDEFE_SUVD_CGC_GATE__SAOE_MASK
#define CDEFE_SUVD_CGC_GATE__SRE_AV1_MASK
#define CDEFE_SUVD_CGC_GATE__FBC_PCLK_MASK
#define CDEFE_SUVD_CGC_GATE__FBC_CCLK_MASK
#define CDEFE_SUVD_CGC_GATE__SCM_AV1_MASK
#define CDEFE_SUVD_CGC_GATE__SMPA_MASK
//EFC_SUVD_CGC_GATE
#define EFC_SUVD_CGC_GATE__SRE__SHIFT
#define EFC_SUVD_CGC_GATE__SIT__SHIFT
#define EFC_SUVD_CGC_GATE__SMP__SHIFT
#define EFC_SUVD_CGC_GATE__SCM__SHIFT
#define EFC_SUVD_CGC_GATE__SDB__SHIFT
#define EFC_SUVD_CGC_GATE__SRE_H264__SHIFT
#define EFC_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define EFC_SUVD_CGC_GATE__SIT_H264__SHIFT
#define EFC_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define EFC_SUVD_CGC_GATE__SCM_H264__SHIFT
#define EFC_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define EFC_SUVD_CGC_GATE__SDB_H264__SHIFT
#define EFC_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define EFC_SUVD_CGC_GATE__SCLR__SHIFT
#define EFC_SUVD_CGC_GATE__UVD_SC__SHIFT
#define EFC_SUVD_CGC_GATE__ENT__SHIFT
#define EFC_SUVD_CGC_GATE__IME__SHIFT
#define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define EFC_SUVD_CGC_GATE__SITE__SHIFT
#define EFC_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define EFC_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define EFC_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define EFC_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define EFC_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define EFC_SUVD_CGC_GATE__EFC__SHIFT
#define EFC_SUVD_CGC_GATE__SAOE__SHIFT
#define EFC_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define EFC_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define EFC_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define EFC_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define EFC_SUVD_CGC_GATE__SMPA__SHIFT
#define EFC_SUVD_CGC_GATE__SRE_MASK
#define EFC_SUVD_CGC_GATE__SIT_MASK
#define EFC_SUVD_CGC_GATE__SMP_MASK
#define EFC_SUVD_CGC_GATE__SCM_MASK
#define EFC_SUVD_CGC_GATE__SDB_MASK
#define EFC_SUVD_CGC_GATE__SRE_H264_MASK
#define EFC_SUVD_CGC_GATE__SRE_HEVC_MASK
#define EFC_SUVD_CGC_GATE__SIT_H264_MASK
#define EFC_SUVD_CGC_GATE__SIT_HEVC_MASK
#define EFC_SUVD_CGC_GATE__SCM_H264_MASK
#define EFC_SUVD_CGC_GATE__SCM_HEVC_MASK
#define EFC_SUVD_CGC_GATE__SDB_H264_MASK
#define EFC_SUVD_CGC_GATE__SDB_HEVC_MASK
#define EFC_SUVD_CGC_GATE__SCLR_MASK
#define EFC_SUVD_CGC_GATE__UVD_SC_MASK
#define EFC_SUVD_CGC_GATE__ENT_MASK
#define EFC_SUVD_CGC_GATE__IME_MASK
#define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define EFC_SUVD_CGC_GATE__SITE_MASK
#define EFC_SUVD_CGC_GATE__SRE_VP9_MASK
#define EFC_SUVD_CGC_GATE__SCM_VP9_MASK
#define EFC_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define EFC_SUVD_CGC_GATE__SDB_VP9_MASK
#define EFC_SUVD_CGC_GATE__IME_HEVC_MASK
#define EFC_SUVD_CGC_GATE__EFC_MASK
#define EFC_SUVD_CGC_GATE__SAOE_MASK
#define EFC_SUVD_CGC_GATE__SRE_AV1_MASK
#define EFC_SUVD_CGC_GATE__FBC_PCLK_MASK
#define EFC_SUVD_CGC_GATE__FBC_CCLK_MASK
#define EFC_SUVD_CGC_GATE__SCM_AV1_MASK
#define EFC_SUVD_CGC_GATE__SMPA_MASK
//ENT_SUVD_CGC_GATE
#define ENT_SUVD_CGC_GATE__SRE__SHIFT
#define ENT_SUVD_CGC_GATE__SIT__SHIFT
#define ENT_SUVD_CGC_GATE__SMP__SHIFT
#define ENT_SUVD_CGC_GATE__SCM__SHIFT
#define ENT_SUVD_CGC_GATE__SDB__SHIFT
#define ENT_SUVD_CGC_GATE__SRE_H264__SHIFT
#define ENT_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define ENT_SUVD_CGC_GATE__SIT_H264__SHIFT
#define ENT_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define ENT_SUVD_CGC_GATE__SCM_H264__SHIFT
#define ENT_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define ENT_SUVD_CGC_GATE__SDB_H264__SHIFT
#define ENT_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define ENT_SUVD_CGC_GATE__SCLR__SHIFT
#define ENT_SUVD_CGC_GATE__UVD_SC__SHIFT
#define ENT_SUVD_CGC_GATE__ENT__SHIFT
#define ENT_SUVD_CGC_GATE__IME__SHIFT
#define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define ENT_SUVD_CGC_GATE__SITE__SHIFT
#define ENT_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define ENT_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define ENT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define ENT_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define ENT_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define ENT_SUVD_CGC_GATE__EFC__SHIFT
#define ENT_SUVD_CGC_GATE__SAOE__SHIFT
#define ENT_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define ENT_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define ENT_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define ENT_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define ENT_SUVD_CGC_GATE__SMPA__SHIFT
#define ENT_SUVD_CGC_GATE__SRE_MASK
#define ENT_SUVD_CGC_GATE__SIT_MASK
#define ENT_SUVD_CGC_GATE__SMP_MASK
#define ENT_SUVD_CGC_GATE__SCM_MASK
#define ENT_SUVD_CGC_GATE__SDB_MASK
#define ENT_SUVD_CGC_GATE__SRE_H264_MASK
#define ENT_SUVD_CGC_GATE__SRE_HEVC_MASK
#define ENT_SUVD_CGC_GATE__SIT_H264_MASK
#define ENT_SUVD_CGC_GATE__SIT_HEVC_MASK
#define ENT_SUVD_CGC_GATE__SCM_H264_MASK
#define ENT_SUVD_CGC_GATE__SCM_HEVC_MASK
#define ENT_SUVD_CGC_GATE__SDB_H264_MASK
#define ENT_SUVD_CGC_GATE__SDB_HEVC_MASK
#define ENT_SUVD_CGC_GATE__SCLR_MASK
#define ENT_SUVD_CGC_GATE__UVD_SC_MASK
#define ENT_SUVD_CGC_GATE__ENT_MASK
#define ENT_SUVD_CGC_GATE__IME_MASK
#define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define ENT_SUVD_CGC_GATE__SITE_MASK
#define ENT_SUVD_CGC_GATE__SRE_VP9_MASK
#define ENT_SUVD_CGC_GATE__SCM_VP9_MASK
#define ENT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define ENT_SUVD_CGC_GATE__SDB_VP9_MASK
#define ENT_SUVD_CGC_GATE__IME_HEVC_MASK
#define ENT_SUVD_CGC_GATE__EFC_MASK
#define ENT_SUVD_CGC_GATE__SAOE_MASK
#define ENT_SUVD_CGC_GATE__SRE_AV1_MASK
#define ENT_SUVD_CGC_GATE__FBC_PCLK_MASK
#define ENT_SUVD_CGC_GATE__FBC_CCLK_MASK
#define ENT_SUVD_CGC_GATE__SCM_AV1_MASK
#define ENT_SUVD_CGC_GATE__SMPA_MASK
//IME_SUVD_CGC_GATE
#define IME_SUVD_CGC_GATE__SRE__SHIFT
#define IME_SUVD_CGC_GATE__SIT__SHIFT
#define IME_SUVD_CGC_GATE__SMP__SHIFT
#define IME_SUVD_CGC_GATE__SCM__SHIFT
#define IME_SUVD_CGC_GATE__SDB__SHIFT
#define IME_SUVD_CGC_GATE__SRE_H264__SHIFT
#define IME_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define IME_SUVD_CGC_GATE__SIT_H264__SHIFT
#define IME_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define IME_SUVD_CGC_GATE__SCM_H264__SHIFT
#define IME_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define IME_SUVD_CGC_GATE__SDB_H264__SHIFT
#define IME_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define IME_SUVD_CGC_GATE__SCLR__SHIFT
#define IME_SUVD_CGC_GATE__UVD_SC__SHIFT
#define IME_SUVD_CGC_GATE__ENT__SHIFT
#define IME_SUVD_CGC_GATE__IME__SHIFT
#define IME_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define IME_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define IME_SUVD_CGC_GATE__SITE__SHIFT
#define IME_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define IME_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define IME_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define IME_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define IME_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define IME_SUVD_CGC_GATE__EFC__SHIFT
#define IME_SUVD_CGC_GATE__SAOE__SHIFT
#define IME_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define IME_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define IME_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define IME_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define IME_SUVD_CGC_GATE__SMPA__SHIFT
#define IME_SUVD_CGC_GATE__SRE_MASK
#define IME_SUVD_CGC_GATE__SIT_MASK
#define IME_SUVD_CGC_GATE__SMP_MASK
#define IME_SUVD_CGC_GATE__SCM_MASK
#define IME_SUVD_CGC_GATE__SDB_MASK
#define IME_SUVD_CGC_GATE__SRE_H264_MASK
#define IME_SUVD_CGC_GATE__SRE_HEVC_MASK
#define IME_SUVD_CGC_GATE__SIT_H264_MASK
#define IME_SUVD_CGC_GATE__SIT_HEVC_MASK
#define IME_SUVD_CGC_GATE__SCM_H264_MASK
#define IME_SUVD_CGC_GATE__SCM_HEVC_MASK
#define IME_SUVD_CGC_GATE__SDB_H264_MASK
#define IME_SUVD_CGC_GATE__SDB_HEVC_MASK
#define IME_SUVD_CGC_GATE__SCLR_MASK
#define IME_SUVD_CGC_GATE__UVD_SC_MASK
#define IME_SUVD_CGC_GATE__ENT_MASK
#define IME_SUVD_CGC_GATE__IME_MASK
#define IME_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define IME_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define IME_SUVD_CGC_GATE__SITE_MASK
#define IME_SUVD_CGC_GATE__SRE_VP9_MASK
#define IME_SUVD_CGC_GATE__SCM_VP9_MASK
#define IME_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define IME_SUVD_CGC_GATE__SDB_VP9_MASK
#define IME_SUVD_CGC_GATE__IME_HEVC_MASK
#define IME_SUVD_CGC_GATE__EFC_MASK
#define IME_SUVD_CGC_GATE__SAOE_MASK
#define IME_SUVD_CGC_GATE__SRE_AV1_MASK
#define IME_SUVD_CGC_GATE__FBC_PCLK_MASK
#define IME_SUVD_CGC_GATE__FBC_CCLK_MASK
#define IME_SUVD_CGC_GATE__SCM_AV1_MASK
#define IME_SUVD_CGC_GATE__SMPA_MASK
//PPU_SUVD_CGC_GATE
#define PPU_SUVD_CGC_GATE__SRE__SHIFT
#define PPU_SUVD_CGC_GATE__SIT__SHIFT
#define PPU_SUVD_CGC_GATE__SMP__SHIFT
#define PPU_SUVD_CGC_GATE__SCM__SHIFT
#define PPU_SUVD_CGC_GATE__SDB__SHIFT
#define PPU_SUVD_CGC_GATE__SRE_H264__SHIFT
#define PPU_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define PPU_SUVD_CGC_GATE__SIT_H264__SHIFT
#define PPU_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define PPU_SUVD_CGC_GATE__SCM_H264__SHIFT
#define PPU_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define PPU_SUVD_CGC_GATE__SDB_H264__SHIFT
#define PPU_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define PPU_SUVD_CGC_GATE__SCLR__SHIFT
#define PPU_SUVD_CGC_GATE__UVD_SC__SHIFT
#define PPU_SUVD_CGC_GATE__ENT__SHIFT
#define PPU_SUVD_CGC_GATE__IME__SHIFT
#define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define PPU_SUVD_CGC_GATE__SITE__SHIFT
#define PPU_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define PPU_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define PPU_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define PPU_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define PPU_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define PPU_SUVD_CGC_GATE__EFC__SHIFT
#define PPU_SUVD_CGC_GATE__SAOE__SHIFT
#define PPU_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define PPU_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define PPU_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define PPU_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define PPU_SUVD_CGC_GATE__SMPA__SHIFT
#define PPU_SUVD_CGC_GATE__SRE_MASK
#define PPU_SUVD_CGC_GATE__SIT_MASK
#define PPU_SUVD_CGC_GATE__SMP_MASK
#define PPU_SUVD_CGC_GATE__SCM_MASK
#define PPU_SUVD_CGC_GATE__SDB_MASK
#define PPU_SUVD_CGC_GATE__SRE_H264_MASK
#define PPU_SUVD_CGC_GATE__SRE_HEVC_MASK
#define PPU_SUVD_CGC_GATE__SIT_H264_MASK
#define PPU_SUVD_CGC_GATE__SIT_HEVC_MASK
#define PPU_SUVD_CGC_GATE__SCM_H264_MASK
#define PPU_SUVD_CGC_GATE__SCM_HEVC_MASK
#define PPU_SUVD_CGC_GATE__SDB_H264_MASK
#define PPU_SUVD_CGC_GATE__SDB_HEVC_MASK
#define PPU_SUVD_CGC_GATE__SCLR_MASK
#define PPU_SUVD_CGC_GATE__UVD_SC_MASK
#define PPU_SUVD_CGC_GATE__ENT_MASK
#define PPU_SUVD_CGC_GATE__IME_MASK
#define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define PPU_SUVD_CGC_GATE__SITE_MASK
#define PPU_SUVD_CGC_GATE__SRE_VP9_MASK
#define PPU_SUVD_CGC_GATE__SCM_VP9_MASK
#define PPU_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define PPU_SUVD_CGC_GATE__SDB_VP9_MASK
#define PPU_SUVD_CGC_GATE__IME_HEVC_MASK
#define PPU_SUVD_CGC_GATE__EFC_MASK
#define PPU_SUVD_CGC_GATE__SAOE_MASK
#define PPU_SUVD_CGC_GATE__SRE_AV1_MASK
#define PPU_SUVD_CGC_GATE__FBC_PCLK_MASK
#define PPU_SUVD_CGC_GATE__FBC_CCLK_MASK
#define PPU_SUVD_CGC_GATE__SCM_AV1_MASK
#define PPU_SUVD_CGC_GATE__SMPA_MASK
//SAOE_SUVD_CGC_GATE
#define SAOE_SUVD_CGC_GATE__SRE__SHIFT
#define SAOE_SUVD_CGC_GATE__SIT__SHIFT
#define SAOE_SUVD_CGC_GATE__SMP__SHIFT
#define SAOE_SUVD_CGC_GATE__SCM__SHIFT
#define SAOE_SUVD_CGC_GATE__SDB__SHIFT
#define SAOE_SUVD_CGC_GATE__SRE_H264__SHIFT
#define SAOE_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define SAOE_SUVD_CGC_GATE__SIT_H264__SHIFT
#define SAOE_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define SAOE_SUVD_CGC_GATE__SCM_H264__SHIFT
#define SAOE_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define SAOE_SUVD_CGC_GATE__SDB_H264__SHIFT
#define SAOE_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define SAOE_SUVD_CGC_GATE__SCLR__SHIFT
#define SAOE_SUVD_CGC_GATE__UVD_SC__SHIFT
#define SAOE_SUVD_CGC_GATE__ENT__SHIFT
#define SAOE_SUVD_CGC_GATE__IME__SHIFT
#define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define SAOE_SUVD_CGC_GATE__SITE__SHIFT
#define SAOE_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define SAOE_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define SAOE_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define SAOE_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define SAOE_SUVD_CGC_GATE__EFC__SHIFT
#define SAOE_SUVD_CGC_GATE__SAOE__SHIFT
#define SAOE_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define SAOE_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define SAOE_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define SAOE_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define SAOE_SUVD_CGC_GATE__SMPA__SHIFT
#define SAOE_SUVD_CGC_GATE__SRE_MASK
#define SAOE_SUVD_CGC_GATE__SIT_MASK
#define SAOE_SUVD_CGC_GATE__SMP_MASK
#define SAOE_SUVD_CGC_GATE__SCM_MASK
#define SAOE_SUVD_CGC_GATE__SDB_MASK
#define SAOE_SUVD_CGC_GATE__SRE_H264_MASK
#define SAOE_SUVD_CGC_GATE__SRE_HEVC_MASK
#define SAOE_SUVD_CGC_GATE__SIT_H264_MASK
#define SAOE_SUVD_CGC_GATE__SIT_HEVC_MASK
#define SAOE_SUVD_CGC_GATE__SCM_H264_MASK
#define SAOE_SUVD_CGC_GATE__SCM_HEVC_MASK
#define SAOE_SUVD_CGC_GATE__SDB_H264_MASK
#define SAOE_SUVD_CGC_GATE__SDB_HEVC_MASK
#define SAOE_SUVD_CGC_GATE__SCLR_MASK
#define SAOE_SUVD_CGC_GATE__UVD_SC_MASK
#define SAOE_SUVD_CGC_GATE__ENT_MASK
#define SAOE_SUVD_CGC_GATE__IME_MASK
#define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define SAOE_SUVD_CGC_GATE__SITE_MASK
#define SAOE_SUVD_CGC_GATE__SRE_VP9_MASK
#define SAOE_SUVD_CGC_GATE__SCM_VP9_MASK
#define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define SAOE_SUVD_CGC_GATE__SDB_VP9_MASK
#define SAOE_SUVD_CGC_GATE__IME_HEVC_MASK
#define SAOE_SUVD_CGC_GATE__EFC_MASK
#define SAOE_SUVD_CGC_GATE__SAOE_MASK
#define SAOE_SUVD_CGC_GATE__SRE_AV1_MASK
#define SAOE_SUVD_CGC_GATE__FBC_PCLK_MASK
#define SAOE_SUVD_CGC_GATE__FBC_CCLK_MASK
#define SAOE_SUVD_CGC_GATE__SCM_AV1_MASK
#define SAOE_SUVD_CGC_GATE__SMPA_MASK
//SCM_SUVD_CGC_GATE
#define SCM_SUVD_CGC_GATE__SRE__SHIFT
#define SCM_SUVD_CGC_GATE__SIT__SHIFT
#define SCM_SUVD_CGC_GATE__SMP__SHIFT
#define SCM_SUVD_CGC_GATE__SCM__SHIFT
#define SCM_SUVD_CGC_GATE__SDB__SHIFT
#define SCM_SUVD_CGC_GATE__SRE_H264__SHIFT
#define SCM_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define SCM_SUVD_CGC_GATE__SIT_H264__SHIFT
#define SCM_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define SCM_SUVD_CGC_GATE__SCM_H264__SHIFT
#define SCM_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define SCM_SUVD_CGC_GATE__SDB_H264__SHIFT
#define SCM_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define SCM_SUVD_CGC_GATE__SCLR__SHIFT
#define SCM_SUVD_CGC_GATE__UVD_SC__SHIFT
#define SCM_SUVD_CGC_GATE__ENT__SHIFT
#define SCM_SUVD_CGC_GATE__IME__SHIFT
#define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define SCM_SUVD_CGC_GATE__SITE__SHIFT
#define SCM_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define SCM_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define SCM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define SCM_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define SCM_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define SCM_SUVD_CGC_GATE__EFC__SHIFT
#define SCM_SUVD_CGC_GATE__SAOE__SHIFT
#define SCM_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define SCM_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define SCM_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define SCM_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define SCM_SUVD_CGC_GATE__SMPA__SHIFT
#define SCM_SUVD_CGC_GATE__SRE_MASK
#define SCM_SUVD_CGC_GATE__SIT_MASK
#define SCM_SUVD_CGC_GATE__SMP_MASK
#define SCM_SUVD_CGC_GATE__SCM_MASK
#define SCM_SUVD_CGC_GATE__SDB_MASK
#define SCM_SUVD_CGC_GATE__SRE_H264_MASK
#define SCM_SUVD_CGC_GATE__SRE_HEVC_MASK
#define SCM_SUVD_CGC_GATE__SIT_H264_MASK
#define SCM_SUVD_CGC_GATE__SIT_HEVC_MASK
#define SCM_SUVD_CGC_GATE__SCM_H264_MASK
#define SCM_SUVD_CGC_GATE__SCM_HEVC_MASK
#define SCM_SUVD_CGC_GATE__SDB_H264_MASK
#define SCM_SUVD_CGC_GATE__SDB_HEVC_MASK
#define SCM_SUVD_CGC_GATE__SCLR_MASK
#define SCM_SUVD_CGC_GATE__UVD_SC_MASK
#define SCM_SUVD_CGC_GATE__ENT_MASK
#define SCM_SUVD_CGC_GATE__IME_MASK
#define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define SCM_SUVD_CGC_GATE__SITE_MASK
#define SCM_SUVD_CGC_GATE__SRE_VP9_MASK
#define SCM_SUVD_CGC_GATE__SCM_VP9_MASK
#define SCM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define SCM_SUVD_CGC_GATE__SDB_VP9_MASK
#define SCM_SUVD_CGC_GATE__IME_HEVC_MASK
#define SCM_SUVD_CGC_GATE__EFC_MASK
#define SCM_SUVD_CGC_GATE__SAOE_MASK
#define SCM_SUVD_CGC_GATE__SRE_AV1_MASK
#define SCM_SUVD_CGC_GATE__FBC_PCLK_MASK
#define SCM_SUVD_CGC_GATE__FBC_CCLK_MASK
#define SCM_SUVD_CGC_GATE__SCM_AV1_MASK
#define SCM_SUVD_CGC_GATE__SMPA_MASK
//SDB_SUVD_CGC_GATE
#define SDB_SUVD_CGC_GATE__SRE__SHIFT
#define SDB_SUVD_CGC_GATE__SIT__SHIFT
#define SDB_SUVD_CGC_GATE__SMP__SHIFT
#define SDB_SUVD_CGC_GATE__SCM__SHIFT
#define SDB_SUVD_CGC_GATE__SDB__SHIFT
#define SDB_SUVD_CGC_GATE__SRE_H264__SHIFT
#define SDB_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define SDB_SUVD_CGC_GATE__SIT_H264__SHIFT
#define SDB_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define SDB_SUVD_CGC_GATE__SCM_H264__SHIFT
#define SDB_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define SDB_SUVD_CGC_GATE__SDB_H264__SHIFT
#define SDB_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define SDB_SUVD_CGC_GATE__SCLR__SHIFT
#define SDB_SUVD_CGC_GATE__UVD_SC__SHIFT
#define SDB_SUVD_CGC_GATE__ENT__SHIFT
#define SDB_SUVD_CGC_GATE__IME__SHIFT
#define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define SDB_SUVD_CGC_GATE__SITE__SHIFT
#define SDB_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define SDB_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define SDB_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define SDB_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define SDB_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define SDB_SUVD_CGC_GATE__EFC__SHIFT
#define SDB_SUVD_CGC_GATE__SAOE__SHIFT
#define SDB_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define SDB_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define SDB_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define SDB_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define SDB_SUVD_CGC_GATE__SMPA__SHIFT
#define SDB_SUVD_CGC_GATE__SRE_MASK
#define SDB_SUVD_CGC_GATE__SIT_MASK
#define SDB_SUVD_CGC_GATE__SMP_MASK
#define SDB_SUVD_CGC_GATE__SCM_MASK
#define SDB_SUVD_CGC_GATE__SDB_MASK
#define SDB_SUVD_CGC_GATE__SRE_H264_MASK
#define SDB_SUVD_CGC_GATE__SRE_HEVC_MASK
#define SDB_SUVD_CGC_GATE__SIT_H264_MASK
#define SDB_SUVD_CGC_GATE__SIT_HEVC_MASK
#define SDB_SUVD_CGC_GATE__SCM_H264_MASK
#define SDB_SUVD_CGC_GATE__SCM_HEVC_MASK
#define SDB_SUVD_CGC_GATE__SDB_H264_MASK
#define SDB_SUVD_CGC_GATE__SDB_HEVC_MASK
#define SDB_SUVD_CGC_GATE__SCLR_MASK
#define SDB_SUVD_CGC_GATE__UVD_SC_MASK
#define SDB_SUVD_CGC_GATE__ENT_MASK
#define SDB_SUVD_CGC_GATE__IME_MASK
#define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define SDB_SUVD_CGC_GATE__SITE_MASK
#define SDB_SUVD_CGC_GATE__SRE_VP9_MASK
#define SDB_SUVD_CGC_GATE__SCM_VP9_MASK
#define SDB_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define SDB_SUVD_CGC_GATE__SDB_VP9_MASK
#define SDB_SUVD_CGC_GATE__IME_HEVC_MASK
#define SDB_SUVD_CGC_GATE__EFC_MASK
#define SDB_SUVD_CGC_GATE__SAOE_MASK
#define SDB_SUVD_CGC_GATE__SRE_AV1_MASK
#define SDB_SUVD_CGC_GATE__FBC_PCLK_MASK
#define SDB_SUVD_CGC_GATE__FBC_CCLK_MASK
#define SDB_SUVD_CGC_GATE__SCM_AV1_MASK
#define SDB_SUVD_CGC_GATE__SMPA_MASK
//SIT0_NXT_SUVD_CGC_GATE
#define SIT0_NXT_SUVD_CGC_GATE__SRE__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SIT__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SMP__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SCM__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SDB__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SCLR__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__ENT__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__IME__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SITE__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__EFC__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SAOE__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SMPA__SHIFT
#define SIT0_NXT_SUVD_CGC_GATE__SRE_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SIT_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SMP_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SCM_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SDB_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SRE_H264_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SIT_H264_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SCM_H264_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SDB_H264_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SCLR_MASK
#define SIT0_NXT_SUVD_CGC_GATE__UVD_SC_MASK
#define SIT0_NXT_SUVD_CGC_GATE__ENT_MASK
#define SIT0_NXT_SUVD_CGC_GATE__IME_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SITE_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9_MASK
#define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC_MASK
#define SIT0_NXT_SUVD_CGC_GATE__EFC_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SAOE_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1_MASK
#define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK
#define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1_MASK
#define SIT0_NXT_SUVD_CGC_GATE__SMPA_MASK
//SIT1_NXT_SUVD_CGC_GATE
#define SIT1_NXT_SUVD_CGC_GATE__SRE__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SIT__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SMP__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SCM__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SDB__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SCLR__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__ENT__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__IME__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SITE__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__EFC__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SAOE__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SMPA__SHIFT
#define SIT1_NXT_SUVD_CGC_GATE__SRE_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SIT_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SMP_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SCM_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SDB_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SRE_H264_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SIT_H264_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SCM_H264_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SDB_H264_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SCLR_MASK
#define SIT1_NXT_SUVD_CGC_GATE__UVD_SC_MASK
#define SIT1_NXT_SUVD_CGC_GATE__ENT_MASK
#define SIT1_NXT_SUVD_CGC_GATE__IME_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SITE_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9_MASK
#define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC_MASK
#define SIT1_NXT_SUVD_CGC_GATE__EFC_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SAOE_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1_MASK
#define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK
#define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1_MASK
#define SIT1_NXT_SUVD_CGC_GATE__SMPA_MASK
//SIT2_NXT_SUVD_CGC_GATE
#define SIT2_NXT_SUVD_CGC_GATE__SRE__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SIT__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SMP__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SCM__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SDB__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SCLR__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__ENT__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__IME__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SITE__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__EFC__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SAOE__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SMPA__SHIFT
#define SIT2_NXT_SUVD_CGC_GATE__SRE_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SIT_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SMP_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SCM_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SDB_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SRE_H264_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SIT_H264_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SCM_H264_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SDB_H264_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SCLR_MASK
#define SIT2_NXT_SUVD_CGC_GATE__UVD_SC_MASK
#define SIT2_NXT_SUVD_CGC_GATE__ENT_MASK
#define SIT2_NXT_SUVD_CGC_GATE__IME_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SITE_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9_MASK
#define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC_MASK
#define SIT2_NXT_SUVD_CGC_GATE__EFC_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SAOE_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1_MASK
#define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK
#define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1_MASK
#define SIT2_NXT_SUVD_CGC_GATE__SMPA_MASK
//SIT_SUVD_CGC_GATE
#define SIT_SUVD_CGC_GATE__SRE__SHIFT
#define SIT_SUVD_CGC_GATE__SIT__SHIFT
#define SIT_SUVD_CGC_GATE__SMP__SHIFT
#define SIT_SUVD_CGC_GATE__SCM__SHIFT
#define SIT_SUVD_CGC_GATE__SDB__SHIFT
#define SIT_SUVD_CGC_GATE__SRE_H264__SHIFT
#define SIT_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define SIT_SUVD_CGC_GATE__SIT_H264__SHIFT
#define SIT_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define SIT_SUVD_CGC_GATE__SCM_H264__SHIFT
#define SIT_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define SIT_SUVD_CGC_GATE__SDB_H264__SHIFT
#define SIT_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define SIT_SUVD_CGC_GATE__SCLR__SHIFT
#define SIT_SUVD_CGC_GATE__UVD_SC__SHIFT
#define SIT_SUVD_CGC_GATE__ENT__SHIFT
#define SIT_SUVD_CGC_GATE__IME__SHIFT
#define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define SIT_SUVD_CGC_GATE__SITE__SHIFT
#define SIT_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define SIT_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define SIT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define SIT_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define SIT_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define SIT_SUVD_CGC_GATE__EFC__SHIFT
#define SIT_SUVD_CGC_GATE__SAOE__SHIFT
#define SIT_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define SIT_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define SIT_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define SIT_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define SIT_SUVD_CGC_GATE__SMPA__SHIFT
#define SIT_SUVD_CGC_GATE__SRE_MASK
#define SIT_SUVD_CGC_GATE__SIT_MASK
#define SIT_SUVD_CGC_GATE__SMP_MASK
#define SIT_SUVD_CGC_GATE__SCM_MASK
#define SIT_SUVD_CGC_GATE__SDB_MASK
#define SIT_SUVD_CGC_GATE__SRE_H264_MASK
#define SIT_SUVD_CGC_GATE__SRE_HEVC_MASK
#define SIT_SUVD_CGC_GATE__SIT_H264_MASK
#define SIT_SUVD_CGC_GATE__SIT_HEVC_MASK
#define SIT_SUVD_CGC_GATE__SCM_H264_MASK
#define SIT_SUVD_CGC_GATE__SCM_HEVC_MASK
#define SIT_SUVD_CGC_GATE__SDB_H264_MASK
#define SIT_SUVD_CGC_GATE__SDB_HEVC_MASK
#define SIT_SUVD_CGC_GATE__SCLR_MASK
#define SIT_SUVD_CGC_GATE__UVD_SC_MASK
#define SIT_SUVD_CGC_GATE__ENT_MASK
#define SIT_SUVD_CGC_GATE__IME_MASK
#define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define SIT_SUVD_CGC_GATE__SITE_MASK
#define SIT_SUVD_CGC_GATE__SRE_VP9_MASK
#define SIT_SUVD_CGC_GATE__SCM_VP9_MASK
#define SIT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define SIT_SUVD_CGC_GATE__SDB_VP9_MASK
#define SIT_SUVD_CGC_GATE__IME_HEVC_MASK
#define SIT_SUVD_CGC_GATE__EFC_MASK
#define SIT_SUVD_CGC_GATE__SAOE_MASK
#define SIT_SUVD_CGC_GATE__SRE_AV1_MASK
#define SIT_SUVD_CGC_GATE__FBC_PCLK_MASK
#define SIT_SUVD_CGC_GATE__FBC_CCLK_MASK
#define SIT_SUVD_CGC_GATE__SCM_AV1_MASK
#define SIT_SUVD_CGC_GATE__SMPA_MASK
//SMPA_SUVD_CGC_GATE
#define SMPA_SUVD_CGC_GATE__SRE__SHIFT
#define SMPA_SUVD_CGC_GATE__SIT__SHIFT
#define SMPA_SUVD_CGC_GATE__SMP__SHIFT
#define SMPA_SUVD_CGC_GATE__SCM__SHIFT
#define SMPA_SUVD_CGC_GATE__SDB__SHIFT
#define SMPA_SUVD_CGC_GATE__SRE_H264__SHIFT
#define SMPA_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define SMPA_SUVD_CGC_GATE__SIT_H264__SHIFT
#define SMPA_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define SMPA_SUVD_CGC_GATE__SCM_H264__SHIFT
#define SMPA_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define SMPA_SUVD_CGC_GATE__SDB_H264__SHIFT
#define SMPA_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define SMPA_SUVD_CGC_GATE__SCLR__SHIFT
#define SMPA_SUVD_CGC_GATE__UVD_SC__SHIFT
#define SMPA_SUVD_CGC_GATE__ENT__SHIFT
#define SMPA_SUVD_CGC_GATE__IME__SHIFT
#define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define SMPA_SUVD_CGC_GATE__SITE__SHIFT
#define SMPA_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define SMPA_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define SMPA_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define SMPA_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define SMPA_SUVD_CGC_GATE__EFC__SHIFT
#define SMPA_SUVD_CGC_GATE__SAOE__SHIFT
#define SMPA_SUVD_CGC_GATE__SRE_AV1__SHIFT
#define SMPA_SUVD_CGC_GATE__FBC_PCLK__SHIFT
#define SMPA_SUVD_CGC_GATE__FBC_CCLK__SHIFT
#define SMPA_SUVD_CGC_GATE__SCM_AV1__SHIFT
#define SMPA_SUVD_CGC_GATE__SMPA__SHIFT
#define SMPA_SUVD_CGC_GATE__SRE_MASK
#define SMPA_SUVD_CGC_GATE__SIT_MASK
#define SMPA_SUVD_CGC_GATE__SMP_MASK
#define SMPA_SUVD_CGC_GATE__SCM_MASK
#define SMPA_SUVD_CGC_GATE__SDB_MASK
#define SMPA_SUVD_CGC_GATE__SRE_H264_MASK
#define SMPA_SUVD_CGC_GATE__SRE_HEVC_MASK
#define SMPA_SUVD_CGC_GATE__SIT_H264_MASK
#define SMPA_SUVD_CGC_GATE__SIT_HEVC_MASK
#define SMPA_SUVD_CGC_GATE__SCM_H264_MASK
#define SMPA_SUVD_CGC_GATE__SCM_HEVC_MASK
#define SMPA_SUVD_CGC_GATE__SDB_H264_MASK
#define SMPA_SUVD_CGC_GATE__SDB_HEVC_MASK
#define SMPA_SUVD_CGC_GATE__SCLR_MASK
#define SMPA_SUVD_CGC_GATE__UVD_SC_MASK
#define SMPA_SUVD_CGC_GATE__ENT_MASK
#define SMPA_SUVD_CGC_GATE__IME_MASK
#define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
#define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
#define SMPA_SUVD_CGC_GATE__SITE_MASK
#define SMPA_SUVD_CGC_GATE__SRE_VP9_MASK
#define SMPA_SUVD_CGC_GATE__SCM_VP9_MASK
#define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
#define SMPA_SUVD_CGC_GATE__SDB_VP9_MASK
#define SMPA_SUVD_CGC_GATE__IME_HEVC_MASK
#define SMPA_SUVD_CGC_GATE__EFC_MASK
#define SMPA_SUVD_CGC_GATE__SAOE_MASK
#define SMPA_SUVD_CGC_GATE__SRE_AV1_MASK
#define SMPA_SUVD_CGC_GATE__FBC_PCLK_MASK
#define SMPA_SUVD_CGC_GATE__FBC_CCLK_MASK
#define SMPA_SUVD_CGC_GATE__SCM_AV1_MASK
#define SMPA_SUVD_CGC_GATE__SMPA_MASK
//SMP_SUVD_CGC_GATE
#define SMP_SUVD_CGC_GATE__SRE__SHIFT
#define SMP_SUVD_CGC_GATE__SIT__SHIFT
#define SMP_SUVD_CGC_GATE__SMP__SHIFT
#define SMP_SUVD_CGC_GATE__SCM__SHIFT
#define SMP_SUVD_CGC_GATE__SDB__SHIFT
#define SMP_SUVD_CGC_GATE__SRE_H264__SHIFT
#define SMP_SUVD_CGC_GATE__SRE_HEVC__SHIFT
#define SMP_SUVD_CGC_GATE__SIT_H264__SHIFT
#define SMP_SUVD_CGC_GATE__SIT_HEVC__SHIFT
#define SMP_SUVD_CGC_GATE__SCM_H264__SHIFT
#define SMP_SUVD_CGC_GATE__SCM_HEVC__SHIFT
#define SMP_SUVD_CGC_GATE__SDB_H264__SHIFT
#define SMP_SUVD_CGC_GATE__SDB_HEVC__SHIFT
#define SMP_SUVD_CGC_GATE__SCLR__SHIFT
#define SMP_SUVD_CGC_GATE__UVD_SC__SHIFT
#define SMP_SUVD_CGC_GATE__ENT__SHIFT
#define SMP_SUVD_CGC_GATE__IME__SHIFT
#define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
#define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
#define SMP_SUVD_CGC_GATE__SITE__SHIFT
#define SMP_SUVD_CGC_GATE__SRE_VP9__SHIFT
#define SMP_SUVD_CGC_GATE__SCM_VP9__SHIFT
#define SMP_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
#define SMP_SUVD_CGC_GATE__SDB_VP9__SHIFT
#define SMP_SUVD_CGC_GATE__IME_HEVC__SHIFT
#define SMP_SUVD_CGC_GATE__EFC__SHIFT
#define SMP_SUVD_CGC_GATE__SAOE__SHIFT
#define SMP_SUVD_CGC_GATE__SRE_AV1__SHIFT<