/* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _vpe_6_1_0_SH_MASK_HEADER #define _vpe_6_1_0_SH_MASK_HEADER // addressBlock: vpe_vpedec //VPEC_DEC_START #define VPEC_DEC_START__START__SHIFT … #define VPEC_DEC_START__START_MASK … //VPEC_UCODE_ADDR #define VPEC_UCODE_ADDR__VALUE__SHIFT … #define VPEC_UCODE_ADDR__THID__SHIFT … #define VPEC_UCODE_ADDR__VALUE_MASK … #define VPEC_UCODE_ADDR__THID_MASK … //VPEC_UCODE_DATA #define VPEC_UCODE_DATA__VALUE__SHIFT … #define VPEC_UCODE_DATA__VALUE_MASK … //VPEC_F32_CNTL #define VPEC_F32_CNTL__HALT__SHIFT … #define VPEC_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT … #define VPEC_F32_CNTL__TH0_RESET__SHIFT … #define VPEC_F32_CNTL__TH0_ENABLE__SHIFT … #define VPEC_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT … #define VPEC_F32_CNTL__TH1_RESET__SHIFT … #define VPEC_F32_CNTL__TH1_ENABLE__SHIFT … #define VPEC_F32_CNTL__TH0_PRIORITY__SHIFT … #define VPEC_F32_CNTL__TH1_PRIORITY__SHIFT … #define VPEC_F32_CNTL__HALT_MASK … #define VPEC_F32_CNTL__TH0_CHECKSUM_CLR_MASK … #define VPEC_F32_CNTL__TH0_RESET_MASK … #define VPEC_F32_CNTL__TH0_ENABLE_MASK … #define VPEC_F32_CNTL__TH1_CHECKSUM_CLR_MASK … #define VPEC_F32_CNTL__TH1_RESET_MASK … #define VPEC_F32_CNTL__TH1_ENABLE_MASK … #define VPEC_F32_CNTL__TH0_PRIORITY_MASK … #define VPEC_F32_CNTL__TH1_PRIORITY_MASK … //VPEC_VPEP_CTRL #define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN__SHIFT … #define VPEC_VPEP_CTRL__VPEP_SW_RESETB__SHIFT … #define VPEC_VPEP_CTRL__RESERVED__SHIFT … #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK__SHIFT … #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK__SHIFT … #define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN_MASK … #define VPEC_VPEP_CTRL__VPEP_SW_RESETB_MASK … #define VPEC_VPEP_CTRL__RESERVED_MASK … #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK_MASK … #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK_MASK … //VPEC_CLK_CTRL #define VPEC_CLK_CTRL__VPECLK_EN__SHIFT … #define VPEC_CLK_CTRL__RESERVED__SHIFT … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK__SHIFT … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK__SHIFT … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK__SHIFT … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK__SHIFT … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK__SHIFT … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK__SHIFT … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK__SHIFT … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK__SHIFT … #define VPEC_CLK_CTRL__VPECLK_EN_MASK … #define VPEC_CLK_CTRL__RESERVED_MASK … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK_MASK … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK_MASK … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK_MASK … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK_MASK … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK_MASK … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK_MASK … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK_MASK … #define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK_MASK … //VPEC_PG_CNTL #define VPEC_PG_CNTL__PG_EN__SHIFT … #define VPEC_PG_CNTL__PG_HYSTERESIS__SHIFT … #define VPEC_PG_CNTL__PG_EN_MASK … #define VPEC_PG_CNTL__PG_HYSTERESIS_MASK … //VPEC_POWER_CNTL #define VPEC_POWER_CNTL__LS_ENABLE__SHIFT … #define VPEC_POWER_CNTL__LS_ENABLE_MASK … //VPEC_CNTL #define VPEC_CNTL__TRAP_ENABLE__SHIFT … #define VPEC_CNTL__RESERVED_2_2__SHIFT … #define VPEC_CNTL__DATA_SWAP__SHIFT … #define VPEC_CNTL__FENCE_SWAP_ENABLE__SHIFT … #define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT … #define VPEC_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT … #define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT … #define VPEC_CNTL__UMSCH_INT_ENABLE__SHIFT … #define VPEC_CNTL__RESERVED_13_11__SHIFT … #define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT … #define VPEC_CNTL__NACK_PRT_INT_ENABLE__SHIFT … #define VPEC_CNTL__RESERVED_16_16__SHIFT … #define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT … #define VPEC_CNTL__RESERVED_19_19__SHIFT … #define VPEC_CNTL__ZSTATES_ENABLE__SHIFT … #define VPEC_CNTL__ZSTATES_HYSTERESIS__SHIFT … #define VPEC_CNTL__CTXEMPTY_INT_ENABLE__SHIFT … #define VPEC_CNTL__FROZEN_INT_ENABLE__SHIFT … #define VPEC_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT … #define VPEC_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT … #define VPEC_CNTL__TRAP_ENABLE_MASK … #define VPEC_CNTL__RESERVED_2_2_MASK … #define VPEC_CNTL__DATA_SWAP_MASK … #define VPEC_CNTL__FENCE_SWAP_ENABLE_MASK … #define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE_MASK … #define VPEC_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK … #define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE_MASK … #define VPEC_CNTL__UMSCH_INT_ENABLE_MASK … #define VPEC_CNTL__RESERVED_13_11_MASK … #define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK … #define VPEC_CNTL__NACK_PRT_INT_ENABLE_MASK … #define VPEC_CNTL__RESERVED_16_16_MASK … #define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK … #define VPEC_CNTL__RESERVED_19_19_MASK … #define VPEC_CNTL__ZSTATES_ENABLE_MASK … #define VPEC_CNTL__ZSTATES_HYSTERESIS_MASK … #define VPEC_CNTL__CTXEMPTY_INT_ENABLE_MASK … #define VPEC_CNTL__FROZEN_INT_ENABLE_MASK … #define VPEC_CNTL__IB_PREEMPT_INT_ENABLE_MASK … #define VPEC_CNTL__RB_PREEMPT_INT_ENABLE_MASK … //VPEC_CNTL1 #define VPEC_CNTL1__RESERVED_3_1__SHIFT … #define VPEC_CNTL1__SRBM_POLL_RETRYING__SHIFT … #define VPEC_CNTL1__RESERVED_23_10__SHIFT … #define VPEC_CNTL1__CG_STATUS_OUTPUT__SHIFT … #define VPEC_CNTL1__SW_FREEZE_ENABLE__SHIFT … #define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE__SHIFT … #define VPEC_CNTL1__RESERVED__SHIFT … #define VPEC_CNTL1__RESERVED_3_1_MASK … #define VPEC_CNTL1__SRBM_POLL_RETRYING_MASK … #define VPEC_CNTL1__RESERVED_23_10_MASK … #define VPEC_CNTL1__CG_STATUS_OUTPUT_MASK … #define VPEC_CNTL1__SW_FREEZE_ENABLE_MASK … #define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE_MASK … #define VPEC_CNTL1__RESERVED_MASK … //VPEC_CNTL2 #define VPEC_CNTL2__F32_CMD_PROC_DELAY__SHIFT … #define VPEC_CNTL2__F32_SEND_POSTCODE_EN__SHIFT … #define VPEC_CNTL2__UCODE_BUF_DS_EN__SHIFT … #define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT … #define VPEC_CNTL2__RESERVED_11_8__SHIFT … #define VPEC_CNTL2__RESERVED_14_12__SHIFT … #define VPEC_CNTL2__RESERVED_15__SHIFT … #define VPEC_CNTL2__RB_FIFO_WATERMARK__SHIFT … #define VPEC_CNTL2__IB_FIFO_WATERMARK__SHIFT … #define VPEC_CNTL2__RESERVED_22_20__SHIFT … #define VPEC_CNTL2__CH_RD_WATERMARK__SHIFT … #define VPEC_CNTL2__CH_WR_WATERMARK__SHIFT … #define VPEC_CNTL2__CH_WR_WATERMARK_LSB__SHIFT … #define VPEC_CNTL2__F32_CMD_PROC_DELAY_MASK … #define VPEC_CNTL2__F32_SEND_POSTCODE_EN_MASK … #define VPEC_CNTL2__UCODE_BUF_DS_EN_MASK … #define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK … #define VPEC_CNTL2__RESERVED_11_8_MASK … #define VPEC_CNTL2__RESERVED_14_12_MASK … #define VPEC_CNTL2__RESERVED_15_MASK … #define VPEC_CNTL2__RB_FIFO_WATERMARK_MASK … #define VPEC_CNTL2__IB_FIFO_WATERMARK_MASK … #define VPEC_CNTL2__RESERVED_22_20_MASK … #define VPEC_CNTL2__CH_RD_WATERMARK_MASK … #define VPEC_CNTL2__CH_WR_WATERMARK_MASK … #define VPEC_CNTL2__CH_WR_WATERMARK_LSB_MASK … //VPEC_GB_ADDR_CONFIG #define VPEC_GB_ADDR_CONFIG__NUM_PIPES__SHIFT … #define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT … #define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT … #define VPEC_GB_ADDR_CONFIG__NUM_PKRS__SHIFT … #define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT … #define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT … #define VPEC_GB_ADDR_CONFIG__NUM_PIPES_MASK … #define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK … #define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK … #define VPEC_GB_ADDR_CONFIG__NUM_PKRS_MASK … #define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK … #define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK … //VPEC_GB_ADDR_CONFIG_READ #define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT … #define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT … #define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT … #define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT … #define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT … #define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT … #define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK … #define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK … #define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK … #define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK … #define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK … #define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK … //VPEC_PROCESS_QUANTUM0 #define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT … #define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT … #define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT … #define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT … #define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK … #define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK … #define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK … #define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK … //VPEC_PROCESS_QUANTUM1 #define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT … #define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT … #define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT … #define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT … #define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK … #define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK … #define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK … #define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK … //VPEC_CONTEXT_SWITCH_THRESHOLD #define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD__SHIFT … #define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD__SHIFT … #define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD__SHIFT … #define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD__SHIFT … #define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD_MASK … #define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD_MASK … #define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD_MASK … #define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD_MASK … //VPEC_GLOBAL_QUANTUM #define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT … #define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT … #define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK … #define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK … //VPEC_WATCHDOG_CNTL #define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT … #define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT … #define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK … #define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK … //VPEC_ATOMIC_CNTL #define VPEC_ATOMIC_CNTL__LOOP_TIMER__SHIFT … #define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT … #define VPEC_ATOMIC_CNTL__LOOP_TIMER_MASK … #define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK … //VPEC_UCODE_VERSION #define VPEC_UCODE_VERSION__T0_UCODE_VERSION__SHIFT … #define VPEC_UCODE_VERSION__T1_UCODE_VERSION__SHIFT … #define VPEC_UCODE_VERSION__T0_UCODE_VERSION_MASK … #define VPEC_UCODE_VERSION__T1_UCODE_VERSION_MASK … //VPEC_MEMREQ_BURST_CNTL #define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST__SHIFT … #define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST__SHIFT … #define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST__SHIFT … #define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST__SHIFT … #define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE__SHIFT … #define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST_MASK … #define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST_MASK … #define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST_MASK … #define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST_MASK … #define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE_MASK … //VPEC_TIMESTAMP_CNTL #define VPEC_TIMESTAMP_CNTL__CAPTURE__SHIFT … #define VPEC_TIMESTAMP_CNTL__CAPTURE_MASK … //VPEC_GLOBAL_TIMESTAMP_LO #define VPEC_GLOBAL_TIMESTAMP_LO__DATA__SHIFT … #define VPEC_GLOBAL_TIMESTAMP_LO__DATA_MASK … //VPEC_GLOBAL_TIMESTAMP_HI #define VPEC_GLOBAL_TIMESTAMP_HI__DATA__SHIFT … #define VPEC_GLOBAL_TIMESTAMP_HI__DATA_MASK … //VPEC_FREEZE #define VPEC_FREEZE__PREEMPT__SHIFT … #define VPEC_FREEZE__FREEZE__SHIFT … #define VPEC_FREEZE__FROZEN__SHIFT … #define VPEC_FREEZE__F32_FREEZE__SHIFT … #define VPEC_FREEZE__PREEMPT_MASK … #define VPEC_FREEZE__FREEZE_MASK … #define VPEC_FREEZE__FROZEN_MASK … #define VPEC_FREEZE__F32_FREEZE_MASK … //VPEC_CE_CTRL #define VPEC_CE_CTRL__RD_LUT_WATERMARK__SHIFT … #define VPEC_CE_CTRL__RD_LUT_DEPTH__SHIFT … #define VPEC_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT … #define VPEC_CE_CTRL__RESERVED__SHIFT … #define VPEC_CE_CTRL__RD_LUT_WATERMARK_MASK … #define VPEC_CE_CTRL__RD_LUT_DEPTH_MASK … #define VPEC_CE_CTRL__WR_AFIFO_WATERMARK_MASK … #define VPEC_CE_CTRL__RESERVED_MASK … //VPEC_RELAX_ORDERING_LUT #define VPEC_RELAX_ORDERING_LUT__RESERVED0__SHIFT … #define VPEC_RELAX_ORDERING_LUT__VPE__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RESERVED3__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RESERVED4__SHIFT … #define VPEC_RELAX_ORDERING_LUT__FENCE__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RESERVED76__SHIFT … #define VPEC_RELAX_ORDERING_LUT__POLL_MEM__SHIFT … #define VPEC_RELAX_ORDERING_LUT__COND_EXE__SHIFT … #define VPEC_RELAX_ORDERING_LUT__ATOMIC__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12__SHIFT … #define VPEC_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RESERVED__SHIFT … #define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29__SHIFT … #define VPEC_RELAX_ORDERING_LUT__IB_FETCH__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RB_FETCH__SHIFT … #define VPEC_RELAX_ORDERING_LUT__RESERVED0_MASK … #define VPEC_RELAX_ORDERING_LUT__VPE_MASK … #define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2_MASK … #define VPEC_RELAX_ORDERING_LUT__RESERVED3_MASK … #define VPEC_RELAX_ORDERING_LUT__RESERVED4_MASK … #define VPEC_RELAX_ORDERING_LUT__FENCE_MASK … #define VPEC_RELAX_ORDERING_LUT__RESERVED76_MASK … #define VPEC_RELAX_ORDERING_LUT__POLL_MEM_MASK … #define VPEC_RELAX_ORDERING_LUT__COND_EXE_MASK … #define VPEC_RELAX_ORDERING_LUT__ATOMIC_MASK … #define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11_MASK … #define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12_MASK … #define VPEC_RELAX_ORDERING_LUT__TIMESTAMP_MASK … #define VPEC_RELAX_ORDERING_LUT__RESERVED_MASK … #define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK … #define VPEC_RELAX_ORDERING_LUT__RPTR_WRB_MASK … #define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29_MASK … #define VPEC_RELAX_ORDERING_LUT__IB_FETCH_MASK … #define VPEC_RELAX_ORDERING_LUT__RB_FETCH_MASK … //VPEC_CREDIT_CNTL #define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT__SHIFT … #define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT__SHIFT … #define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT_MASK … #define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT_MASK … //VPEC_SCRATCH_RAM_DATA #define VPEC_SCRATCH_RAM_DATA__DATA__SHIFT … #define VPEC_SCRATCH_RAM_DATA__DATA_MASK … //VPEC_SCRATCH_RAM_ADDR #define VPEC_SCRATCH_RAM_ADDR__ADDR__SHIFT … #define VPEC_SCRATCH_RAM_ADDR__ADDR_MASK … //VPEC_QUEUE_RESET_REQ #define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT … #define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT … #define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT … #define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT … #define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT … #define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT … #define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT … #define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT … #define VPEC_QUEUE_RESET_REQ__RESERVED__SHIFT … #define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK … #define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET_MASK … #define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET_MASK … #define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET_MASK … #define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET_MASK … #define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET_MASK … #define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET_MASK … #define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET_MASK … #define VPEC_QUEUE_RESET_REQ__RESERVED_MASK … //VPEC_PERFCNT_PERFCOUNTER0_CFG #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK … #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK … #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK … #define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK … #define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK … //VPEC_PERFCNT_PERFCOUNTER1_CFG #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK … #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK … #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK … #define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK … #define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK … //VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK … #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK … //VPEC_PERFCNT_MISC_CNTL #define VPEC_PERFCNT_MISC_CNTL__CMD_OP__SHIFT … #define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT__SHIFT … #define VPEC_PERFCNT_MISC_CNTL__CMD_OP_MASK … #define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK … //VPEC_PERFCNT_PERFCOUNTER_LO #define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK … //VPEC_PERFCNT_PERFCOUNTER_HI #define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT … #define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK … #define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK … //VPEC_CRC_CTRL #define VPEC_CRC_CTRL__INDEX__SHIFT … #define VPEC_CRC_CTRL__START__SHIFT … #define VPEC_CRC_CTRL__INDEX_MASK … #define VPEC_CRC_CTRL__START_MASK … //VPEC_CRC_DATA #define VPEC_CRC_DATA__DATA__SHIFT … #define VPEC_CRC_DATA__DATA_MASK … //VPEC_PUB_DUMMY0 #define VPEC_PUB_DUMMY0__VALUE__SHIFT … #define VPEC_PUB_DUMMY0__VALUE_MASK … //VPEC_PUB_DUMMY1 #define VPEC_PUB_DUMMY1__VALUE__SHIFT … #define VPEC_PUB_DUMMY1__VALUE_MASK … //VPEC_PUB_DUMMY2 #define VPEC_PUB_DUMMY2__VALUE__SHIFT … #define VPEC_PUB_DUMMY2__VALUE_MASK … //VPEC_PUB_DUMMY3 #define VPEC_PUB_DUMMY3__VALUE__SHIFT … #define VPEC_PUB_DUMMY3__VALUE_MASK … //VPEC_PUB_DUMMY4 #define VPEC_PUB_DUMMY4__VALUE__SHIFT … #define VPEC_PUB_DUMMY4__VALUE_MASK … //VPEC_PUB_DUMMY5 #define VPEC_PUB_DUMMY5__VALUE__SHIFT … #define VPEC_PUB_DUMMY5__VALUE_MASK … //VPEC_PUB_DUMMY6 #define VPEC_PUB_DUMMY6__VALUE__SHIFT … #define VPEC_PUB_DUMMY6__VALUE_MASK … //VPEC_PUB_DUMMY7 #define VPEC_PUB_DUMMY7__VALUE__SHIFT … #define VPEC_PUB_DUMMY7__VALUE_MASK … //VPEC_UCODE1_CHECKSUM #define VPEC_UCODE1_CHECKSUM__DATA__SHIFT … #define VPEC_UCODE1_CHECKSUM__DATA_MASK … //VPEC_VERSION #define VPEC_VERSION__MINVER__SHIFT … #define VPEC_VERSION__MAJVER__SHIFT … #define VPEC_VERSION__REV__SHIFT … #define VPEC_VERSION__MINVER_MASK … #define VPEC_VERSION__MAJVER_MASK … #define VPEC_VERSION__REV_MASK … //VPEC_UCODE_CHECKSUM #define VPEC_UCODE_CHECKSUM__DATA__SHIFT … #define VPEC_UCODE_CHECKSUM__DATA_MASK … //VPEC_CLOCK_GATING_STATUS #define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT … #define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS__SHIFT … #define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS__SHIFT … #define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS__SHIFT … #define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT … #define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT … #define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK … #define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS_MASK … #define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS_MASK … #define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS_MASK … #define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK … #define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK … //VPEC_RB_RPTR_FETCH #define VPEC_RB_RPTR_FETCH__OFFSET__SHIFT … #define VPEC_RB_RPTR_FETCH__OFFSET_MASK … //VPEC_RB_RPTR_FETCH_HI #define VPEC_RB_RPTR_FETCH_HI__OFFSET__SHIFT … #define VPEC_RB_RPTR_FETCH_HI__OFFSET_MASK … //VPEC_IB_OFFSET_FETCH #define VPEC_IB_OFFSET_FETCH__OFFSET__SHIFT … #define VPEC_IB_OFFSET_FETCH__OFFSET_MASK … //VPEC_CMDIB_OFFSET_FETCH #define VPEC_CMDIB_OFFSET_FETCH__OFFSET__SHIFT … #define VPEC_CMDIB_OFFSET_FETCH__OFFSET_MASK … //VPEC_ATOMIC_PREOP_LO #define VPEC_ATOMIC_PREOP_LO__DATA__SHIFT … #define VPEC_ATOMIC_PREOP_LO__DATA_MASK … //VPEC_ATOMIC_PREOP_HI #define VPEC_ATOMIC_PREOP_HI__DATA__SHIFT … #define VPEC_ATOMIC_PREOP_HI__DATA_MASK … //VPEC_CE_BUSY #define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY__SHIFT … #define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY__SHIFT … #define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY__SHIFT … #define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY_MASK … #define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY_MASK … #define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY_MASK … //VPEC_F32_COUNTER #define VPEC_F32_COUNTER__VALUE__SHIFT … #define VPEC_F32_COUNTER__VALUE_MASK … //VPEC_HOLE_ADDR_LO #define VPEC_HOLE_ADDR_LO__VALUE__SHIFT … #define VPEC_HOLE_ADDR_LO__VALUE_MASK … //VPEC_HOLE_ADDR_HI #define VPEC_HOLE_ADDR_HI__VALUE__SHIFT … #define VPEC_HOLE_ADDR_HI__VALUE_MASK … //VPEC_ERROR_LOG //VPEC_INT_STATUS #define VPEC_INT_STATUS__DATA__SHIFT … #define VPEC_INT_STATUS__DATA_MASK … //VPEC_STATUS #define VPEC_STATUS__IDLE__SHIFT … #define VPEC_STATUS__REG_IDLE__SHIFT … #define VPEC_STATUS__RB_EMPTY__SHIFT … #define VPEC_STATUS__RB_FULL__SHIFT … #define VPEC_STATUS__RB_CMD_IDLE__SHIFT … #define VPEC_STATUS__RB_CMD_FULL__SHIFT … #define VPEC_STATUS__IB_CMD_IDLE__SHIFT … #define VPEC_STATUS__IB_CMD_FULL__SHIFT … #define VPEC_STATUS__BLOCK_IDLE__SHIFT … #define VPEC_STATUS__INSIDE_VPEP_CONFIG__SHIFT … #define VPEC_STATUS__EX_IDLE__SHIFT … #define VPEC_STATUS__RESERVED_11_11__SHIFT … #define VPEC_STATUS__PACKET_READY__SHIFT … #define VPEC_STATUS__MC_WR_IDLE__SHIFT … #define VPEC_STATUS__SRBM_IDLE__SHIFT … #define VPEC_STATUS__CONTEXT_EMPTY__SHIFT … #define VPEC_STATUS__INSIDE_IB__SHIFT … #define VPEC_STATUS__RB_MC_RREQ_IDLE__SHIFT … #define VPEC_STATUS__IB_MC_RREQ_IDLE__SHIFT … #define VPEC_STATUS__MC_RD_IDLE__SHIFT … #define VPEC_STATUS__DELTA_RPTR_EMPTY__SHIFT … #define VPEC_STATUS__MC_RD_RET_STALL__SHIFT … #define VPEC_STATUS__RESERVED_22_22__SHIFT … #define VPEC_STATUS__RESERVED_23_23__SHIFT … #define VPEC_STATUS__RESERVED_24_24__SHIFT … #define VPEC_STATUS__PREV_CMD_IDLE__SHIFT … #define VPEC_STATUS__RESERVED_26_26__SHIFT … #define VPEC_STATUS__RESERVED_27_27__SHIFT … #define VPEC_STATUS__RESERVED_29_28__SHIFT … #define VPEC_STATUS__INT_IDLE__SHIFT … #define VPEC_STATUS__INT_REQ_STALL__SHIFT … #define VPEC_STATUS__IDLE_MASK … #define VPEC_STATUS__REG_IDLE_MASK … #define VPEC_STATUS__RB_EMPTY_MASK … #define VPEC_STATUS__RB_FULL_MASK … #define VPEC_STATUS__RB_CMD_IDLE_MASK … #define VPEC_STATUS__RB_CMD_FULL_MASK … #define VPEC_STATUS__IB_CMD_IDLE_MASK … #define VPEC_STATUS__IB_CMD_FULL_MASK … #define VPEC_STATUS__BLOCK_IDLE_MASK … #define VPEC_STATUS__INSIDE_VPEP_CONFIG_MASK … #define VPEC_STATUS__EX_IDLE_MASK … #define VPEC_STATUS__RESERVED_11_11_MASK … #define VPEC_STATUS__PACKET_READY_MASK … #define VPEC_STATUS__MC_WR_IDLE_MASK … #define VPEC_STATUS__SRBM_IDLE_MASK … #define VPEC_STATUS__CONTEXT_EMPTY_MASK … #define VPEC_STATUS__INSIDE_IB_MASK … #define VPEC_STATUS__RB_MC_RREQ_IDLE_MASK … #define VPEC_STATUS__IB_MC_RREQ_IDLE_MASK … #define VPEC_STATUS__MC_RD_IDLE_MASK … #define VPEC_STATUS__DELTA_RPTR_EMPTY_MASK … #define VPEC_STATUS__MC_RD_RET_STALL_MASK … #define VPEC_STATUS__RESERVED_22_22_MASK … #define VPEC_STATUS__RESERVED_23_23_MASK … #define VPEC_STATUS__RESERVED_24_24_MASK … #define VPEC_STATUS__PREV_CMD_IDLE_MASK … #define VPEC_STATUS__RESERVED_26_26_MASK … #define VPEC_STATUS__RESERVED_27_27_MASK … #define VPEC_STATUS__RESERVED_29_28_MASK … #define VPEC_STATUS__INT_IDLE_MASK … #define VPEC_STATUS__INT_REQ_STALL_MASK … //VPEC_STATUS1 #define VPEC_STATUS1__CE_IP0_WREQ_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP0_WR_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP0_SPLIT_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP0_RREQ_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP0_OUT_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP0_IN_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP0_DST_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP0_CMD_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP1_WREQ_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP1_WR_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP1_SPLIT_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP1_RREQ_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP1_OUT_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP1_IN_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP1_DST_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP1_CMD_IDLE__SHIFT … #define VPEC_STATUS1__CE_OP0_WR_IDLE__SHIFT … #define VPEC_STATUS1__CE_OP0_CMD_IDLE__SHIFT … #define VPEC_STATUS1__CE_IP0_AFIFO_FULL__SHIFT … #define VPEC_STATUS1__CE_IP0_CMD_INFO_FULL__SHIFT … #define VPEC_STATUS1__CE_IP0_CMD_INFO1_FULL__SHIFT … #define VPEC_STATUS1__CE_IP1_AFIFO_FULL__SHIFT … #define VPEC_STATUS1__CE_IP1_CMD_INFO_FULL__SHIFT … #define VPEC_STATUS1__CE_IP1_CMD_INFO1_FULL__SHIFT … #define VPEC_STATUS1__EX_START__SHIFT … #define VPEC_STATUS1__CE_RD_STALL__SHIFT … #define VPEC_STATUS1__CE_IP0_WR_STALL__SHIFT … #define VPEC_STATUS1__CE_IP1_WR_STALL__SHIFT … #define VPEC_STATUS1__RESERVED_28_28__SHIFT … #define VPEC_STATUS1__VPEC_IDLE__SHIFT … #define VPEC_STATUS1__PG_STATUS__SHIFT … #define VPEC_STATUS1__CE_IP0_WREQ_IDLE_MASK … #define VPEC_STATUS1__CE_IP0_WR_IDLE_MASK … #define VPEC_STATUS1__CE_IP0_SPLIT_IDLE_MASK … #define VPEC_STATUS1__CE_IP0_RREQ_IDLE_MASK … #define VPEC_STATUS1__CE_IP0_OUT_IDLE_MASK … #define VPEC_STATUS1__CE_IP0_IN_IDLE_MASK … #define VPEC_STATUS1__CE_IP0_DST_IDLE_MASK … #define VPEC_STATUS1__CE_IP0_CMD_IDLE_MASK … #define VPEC_STATUS1__CE_IP1_WREQ_IDLE_MASK … #define VPEC_STATUS1__CE_IP1_WR_IDLE_MASK … #define VPEC_STATUS1__CE_IP1_SPLIT_IDLE_MASK … #define VPEC_STATUS1__CE_IP1_RREQ_IDLE_MASK … #define VPEC_STATUS1__CE_IP1_OUT_IDLE_MASK … #define VPEC_STATUS1__CE_IP1_IN_IDLE_MASK … #define VPEC_STATUS1__CE_IP1_DST_IDLE_MASK … #define VPEC_STATUS1__CE_IP1_CMD_IDLE_MASK … #define VPEC_STATUS1__CE_OP0_WR_IDLE_MASK … #define VPEC_STATUS1__CE_OP0_CMD_IDLE_MASK … #define VPEC_STATUS1__CE_IP0_AFIFO_FULL_MASK … #define VPEC_STATUS1__CE_IP0_CMD_INFO_FULL_MASK … #define VPEC_STATUS1__CE_IP0_CMD_INFO1_FULL_MASK … #define VPEC_STATUS1__CE_IP1_AFIFO_FULL_MASK … #define VPEC_STATUS1__CE_IP1_CMD_INFO_FULL_MASK … #define VPEC_STATUS1__CE_IP1_CMD_INFO1_FULL_MASK … #define VPEC_STATUS1__EX_START_MASK … #define VPEC_STATUS1__CE_RD_STALL_MASK … #define VPEC_STATUS1__CE_IP0_WR_STALL_MASK … #define VPEC_STATUS1__CE_IP1_WR_STALL_MASK … #define VPEC_STATUS1__RESERVED_28_28_MASK … #define VPEC_STATUS1__VPEC_IDLE_MASK … #define VPEC_STATUS1__PG_STATUS_MASK … //VPEC_STATUS2 #define VPEC_STATUS2__ID__SHIFT … #define VPEC_STATUS2__TH0F32_INSTR_PTR__SHIFT … #define VPEC_STATUS2__CMD_OP__SHIFT … #define VPEC_STATUS2__ID_MASK … #define VPEC_STATUS2__TH0F32_INSTR_PTR_MASK … #define VPEC_STATUS2__CMD_OP_MASK … //VPEC_STATUS3 #define VPEC_STATUS3__CMD_OP_STATUS__SHIFT … #define VPEC_STATUS3__RESERVED_19_16__SHIFT … #define VPEC_STATUS3__EXCEPTION_IDLE__SHIFT … #define VPEC_STATUS3__RESERVED_21_21__SHIFT … #define VPEC_STATUS3__RESERVED_22_22__SHIFT … #define VPEC_STATUS3__RESERVED_23_23__SHIFT … #define VPEC_STATUS3__RESERVED_24_24__SHIFT … #define VPEC_STATUS3__RESERVED_25_25__SHIFT … #define VPEC_STATUS3__INT_QUEUE_ID__SHIFT … #define VPEC_STATUS3__RESERVED_31_30__SHIFT … #define VPEC_STATUS3__CMD_OP_STATUS_MASK … #define VPEC_STATUS3__RESERVED_19_16_MASK … #define VPEC_STATUS3__EXCEPTION_IDLE_MASK … #define VPEC_STATUS3__RESERVED_21_21_MASK … #define VPEC_STATUS3__RESERVED_22_22_MASK … #define VPEC_STATUS3__RESERVED_23_23_MASK … #define VPEC_STATUS3__RESERVED_24_24_MASK … #define VPEC_STATUS3__RESERVED_25_25_MASK … #define VPEC_STATUS3__INT_QUEUE_ID_MASK … #define VPEC_STATUS3__RESERVED_31_30_MASK … //VPEC_STATUS4 #define VPEC_STATUS4__IDLE__SHIFT … #define VPEC_STATUS4__IH_OUTSTANDING__SHIFT … #define VPEC_STATUS4__RESERVED_3_3__SHIFT … #define VPEC_STATUS4__CH_RD_OUTSTANDING__SHIFT … #define VPEC_STATUS4__CH_WR_OUTSTANDING__SHIFT … #define VPEC_STATUS4__RESERVED_6_6__SHIFT … #define VPEC_STATUS4__RESERVED_7_7__SHIFT … #define VPEC_STATUS4__RESERVED_8_8__SHIFT … #define VPEC_STATUS4__RESERVED_9_9__SHIFT … #define VPEC_STATUS4__REG_POLLING__SHIFT … #define VPEC_STATUS4__MEM_POLLING__SHIFT … #define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING__SHIFT … #define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING__SHIFT … #define VPEC_STATUS4__RESERVED_15_14__SHIFT … #define VPEC_STATUS4__ACTIVE_QUEUE_ID__SHIFT … #define VPEC_STATUS4__RESERVED_27_20__SHIFT … #define VPEC_STATUS4__IDLE_MASK … #define VPEC_STATUS4__IH_OUTSTANDING_MASK … #define VPEC_STATUS4__RESERVED_3_3_MASK … #define VPEC_STATUS4__CH_RD_OUTSTANDING_MASK … #define VPEC_STATUS4__CH_WR_OUTSTANDING_MASK … #define VPEC_STATUS4__RESERVED_6_6_MASK … #define VPEC_STATUS4__RESERVED_7_7_MASK … #define VPEC_STATUS4__RESERVED_8_8_MASK … #define VPEC_STATUS4__RESERVED_9_9_MASK … #define VPEC_STATUS4__REG_POLLING_MASK … #define VPEC_STATUS4__MEM_POLLING_MASK … #define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING_MASK … #define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING_MASK … #define VPEC_STATUS4__RESERVED_15_14_MASK … #define VPEC_STATUS4__ACTIVE_QUEUE_ID_MASK … #define VPEC_STATUS4__RESERVED_27_20_MASK … //VPEC_STATUS5 #define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS__SHIFT … #define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS__SHIFT … #define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS__SHIFT … #define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS__SHIFT … #define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS__SHIFT … #define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS__SHIFT … #define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS__SHIFT … #define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS__SHIFT … #define VPEC_STATUS5__RESERVED_27_16__SHIFT … #define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS_MASK … #define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS_MASK … #define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS_MASK … #define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS_MASK … #define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS_MASK … #define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS_MASK … #define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS_MASK … #define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS_MASK … #define VPEC_STATUS5__RESERVED_27_16_MASK … //VPEC_STATUS6 #define VPEC_STATUS6__ID__SHIFT … #define VPEC_STATUS6__TH1F32_INSTR_PTR__SHIFT … #define VPEC_STATUS6__TH1_EXCEPTION__SHIFT … #define VPEC_STATUS6__ID_MASK … #define VPEC_STATUS6__TH1F32_INSTR_PTR_MASK … #define VPEC_STATUS6__TH1_EXCEPTION_MASK … //VPEC_STATUS7 //VPEC_INST #define VPEC_INST__ID__SHIFT … #define VPEC_INST__RESERVED__SHIFT … #define VPEC_INST__ID_MASK … #define VPEC_INST__RESERVED_MASK … //VPEC_QUEUE_STATUS0 #define VPEC_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT … #define VPEC_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT … #define VPEC_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT … #define VPEC_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT … #define VPEC_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT … #define VPEC_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT … #define VPEC_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT … #define VPEC_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT … #define VPEC_QUEUE_STATUS0__QUEUE0_STATUS_MASK … #define VPEC_QUEUE_STATUS0__QUEUE1_STATUS_MASK … #define VPEC_QUEUE_STATUS0__QUEUE2_STATUS_MASK … #define VPEC_QUEUE_STATUS0__QUEUE3_STATUS_MASK … #define VPEC_QUEUE_STATUS0__QUEUE4_STATUS_MASK … #define VPEC_QUEUE_STATUS0__QUEUE5_STATUS_MASK … #define VPEC_QUEUE_STATUS0__QUEUE6_STATUS_MASK … #define VPEC_QUEUE_STATUS0__QUEUE7_STATUS_MASK … //VPEC_QUEUE_HANG_STATUS #define VPEC_QUEUE_HANG_STATUS__F30T0_HANG__SHIFT … #define VPEC_QUEUE_HANG_STATUS__CE_HANG__SHIFT … #define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH__SHIFT … #define VPEC_QUEUE_HANG_STATUS__INVALID_OPCODE__SHIFT … #define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR__SHIFT … #define VPEC_QUEUE_HANG_STATUS__F30T0_HANG_MASK … #define VPEC_QUEUE_HANG_STATUS__CE_HANG_MASK … #define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH_MASK … #define VPEC_QUEUE_HANG_STATUS__INVALID_OPCODE_MASK … #define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR_MASK … //VPEC_QUEUE0_RB_CNTL #define VPEC_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT … #define VPEC_QUEUE0_RB_CNTL__RB_SIZE__SHIFT … #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT … #define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT … #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT … #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT … #define VPEC_QUEUE0_RB_CNTL__RB_PRIV__SHIFT … #define VPEC_QUEUE0_RB_CNTL__RB_VMID__SHIFT … #define VPEC_QUEUE0_RB_CNTL__RB_ENABLE_MASK … #define VPEC_QUEUE0_RB_CNTL__RB_SIZE_MASK … #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK … #define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK … #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK … #define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK … #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK … #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK … #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK … #define VPEC_QUEUE0_RB_CNTL__RB_PRIV_MASK … #define VPEC_QUEUE0_RB_CNTL__RB_VMID_MASK … //VPEC_QUEUE0_SCHEDULE_CNTL #define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT … #define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT … #define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT … #define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT … #define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK … #define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK … #define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK … #define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK … //VPEC_QUEUE0_RB_BASE #define VPEC_QUEUE0_RB_BASE__ADDR__SHIFT … #define VPEC_QUEUE0_RB_BASE__ADDR_MASK … //VPEC_QUEUE0_RB_BASE_HI #define VPEC_QUEUE0_RB_BASE_HI__ADDR__SHIFT … #define VPEC_QUEUE0_RB_BASE_HI__ADDR_MASK … //VPEC_QUEUE0_RB_RPTR #define VPEC_QUEUE0_RB_RPTR__OFFSET__SHIFT … #define VPEC_QUEUE0_RB_RPTR__OFFSET_MASK … //VPEC_QUEUE0_RB_RPTR_HI #define VPEC_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT … #define VPEC_QUEUE0_RB_RPTR_HI__OFFSET_MASK … //VPEC_QUEUE0_RB_WPTR #define VPEC_QUEUE0_RB_WPTR__OFFSET__SHIFT … #define VPEC_QUEUE0_RB_WPTR__OFFSET_MASK … //VPEC_QUEUE0_RB_WPTR_HI #define VPEC_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT … #define VPEC_QUEUE0_RB_WPTR_HI__OFFSET_MASK … //VPEC_QUEUE0_RB_RPTR_ADDR_HI #define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT … #define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK … //VPEC_QUEUE0_RB_RPTR_ADDR_LO #define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT … #define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK … //VPEC_QUEUE0_RB_AQL_CNTL #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT … #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT … #define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT … #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT … #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT … #define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT … #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK … #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK … #define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK … #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK … #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK … #define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK … //VPEC_QUEUE0_MINOR_PTR_UPDATE #define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT … #define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK … //VPEC_QUEUE0_CD_INFO #define VPEC_QUEUE0_CD_INFO__CD_INFO__SHIFT … #define VPEC_QUEUE0_CD_INFO__CD_INFO_MASK … //VPEC_QUEUE0_RB_PREEMPT #define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT … #define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK … //VPEC_QUEUE0_SKIP_CNTL #define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT … #define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK … //VPEC_QUEUE0_DOORBELL #define VPEC_QUEUE0_DOORBELL__ENABLE__SHIFT … #define VPEC_QUEUE0_DOORBELL__CAPTURED__SHIFT … #define VPEC_QUEUE0_DOORBELL__ENABLE_MASK … #define VPEC_QUEUE0_DOORBELL__CAPTURED_MASK … //VPEC_QUEUE0_DOORBELL_OFFSET #define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT … #define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK … //VPEC_QUEUE0_DUMMY0 #define VPEC_QUEUE0_DUMMY0__DUMMY__SHIFT … #define VPEC_QUEUE0_DUMMY0__DUMMY_MASK … //VPEC_QUEUE0_DUMMY1 #define VPEC_QUEUE0_DUMMY1__VALUE__SHIFT … #define VPEC_QUEUE0_DUMMY1__VALUE_MASK … //VPEC_QUEUE0_DUMMY2 #define VPEC_QUEUE0_DUMMY2__VALUE__SHIFT … #define VPEC_QUEUE0_DUMMY2__VALUE_MASK … //VPEC_QUEUE0_DUMMY3 #define VPEC_QUEUE0_DUMMY3__VALUE__SHIFT … #define VPEC_QUEUE0_DUMMY3__VALUE_MASK … //VPEC_QUEUE0_DUMMY4 #define VPEC_QUEUE0_DUMMY4__VALUE__SHIFT … #define VPEC_QUEUE0_DUMMY4__VALUE_MASK … //VPEC_QUEUE0_IB_CNTL #define VPEC_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT … #define VPEC_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT … #define VPEC_QUEUE0_IB_CNTL__CMD_VMID__SHIFT … #define VPEC_QUEUE0_IB_CNTL__IB_ENABLE_MASK … #define VPEC_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK … #define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK … #define VPEC_QUEUE0_IB_CNTL__CMD_VMID_MASK … //VPEC_QUEUE0_IB_RPTR #define VPEC_QUEUE0_IB_RPTR__OFFSET__SHIFT … #define VPEC_QUEUE0_IB_RPTR__OFFSET_MASK … //VPEC_QUEUE0_IB_OFFSET #define VPEC_QUEUE0_IB_OFFSET__OFFSET__SHIFT … #define VPEC_QUEUE0_IB_OFFSET__OFFSET_MASK … //VPEC_QUEUE0_IB_BASE_LO #define VPEC_QUEUE0_IB_BASE_LO__ADDR__SHIFT … #define VPEC_QUEUE0_IB_BASE_LO__ADDR_MASK … //VPEC_QUEUE0_IB_BASE_HI #define VPEC_QUEUE0_IB_BASE_HI__ADDR__SHIFT … #define VPEC_QUEUE0_IB_BASE_HI__ADDR_MASK … //VPEC_QUEUE0_IB_SIZE #define VPEC_QUEUE0_IB_SIZE__SIZE__SHIFT … #define VPEC_QUEUE0_IB_SIZE__SIZE_MASK … //VPEC_QUEUE0_CMDIB_CNTL #define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE__SHIFT … #define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT … #define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID__SHIFT … #define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE_MASK … #define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE_MASK … #define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK … #define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID_MASK … //VPEC_QUEUE0_CMDIB_RPTR #define VPEC_QUEUE0_CMDIB_RPTR__OFFSET__SHIFT … #define VPEC_QUEUE0_CMDIB_RPTR__OFFSET_MASK … //VPEC_QUEUE0_CMDIB_OFFSET #define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET__SHIFT … #define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET_MASK … //VPEC_QUEUE0_CMDIB_BASE_LO #define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR__SHIFT … #define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR_MASK … //VPEC_QUEUE0_CMDIB_BASE_HI #define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR__SHIFT … #define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR_MASK … //VPEC_QUEUE0_CMDIB_SIZE #define VPEC_QUEUE0_CMDIB_SIZE__SIZE__SHIFT … #define VPEC_QUEUE0_CMDIB_SIZE__SIZE_MASK … //VPEC_QUEUE0_CSA_ADDR_LO #define VPEC_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT … #define VPEC_QUEUE0_CSA_ADDR_LO__ADDR_MASK … //VPEC_QUEUE0_CSA_ADDR_HI #define VPEC_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT … #define VPEC_QUEUE0_CSA_ADDR_HI__ADDR_MASK … //VPEC_QUEUE0_CONTEXT_STATUS #define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT … #define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT … #define VPEC_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT … #define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT … #define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT … #define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT … #define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT … #define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT … #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT … #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … #define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED_MASK … #define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB_MASK … #define VPEC_QUEUE0_CONTEXT_STATUS__IDLE_MASK … #define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK … #define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK … #define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK … #define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK … #define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK … #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK … #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK … //VPEC_QUEUE0_DOORBELL_LOG //VPEC_QUEUE0_IB_SUB_REMAIN #define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT … #define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE_MASK … //VPEC_QUEUE0_PREEMPT #define VPEC_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT … #define VPEC_QUEUE0_PREEMPT__IB_PREEMPT_MASK … //VPEC_QUEUE1_RB_CNTL #define VPEC_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT … #define VPEC_QUEUE1_RB_CNTL__RB_SIZE__SHIFT … #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT … #define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT … #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT … #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT … #define VPEC_QUEUE1_RB_CNTL__RB_PRIV__SHIFT … #define VPEC_QUEUE1_RB_CNTL__RB_VMID__SHIFT … #define VPEC_QUEUE1_RB_CNTL__RB_ENABLE_MASK … #define VPEC_QUEUE1_RB_CNTL__RB_SIZE_MASK … #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK … #define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK … #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK … #define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK … #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK … #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK … #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK … #define VPEC_QUEUE1_RB_CNTL__RB_PRIV_MASK … #define VPEC_QUEUE1_RB_CNTL__RB_VMID_MASK … //VPEC_QUEUE1_SCHEDULE_CNTL #define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT … #define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT … #define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT … #define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT … #define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK … #define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK … #define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK … #define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK … //VPEC_QUEUE1_RB_BASE #define VPEC_QUEUE1_RB_BASE__ADDR__SHIFT … #define VPEC_QUEUE1_RB_BASE__ADDR_MASK … //VPEC_QUEUE1_RB_BASE_HI #define VPEC_QUEUE1_RB_BASE_HI__ADDR__SHIFT … #define VPEC_QUEUE1_RB_BASE_HI__ADDR_MASK … //VPEC_QUEUE1_RB_RPTR #define VPEC_QUEUE1_RB_RPTR__OFFSET__SHIFT … #define VPEC_QUEUE1_RB_RPTR__OFFSET_MASK … //VPEC_QUEUE1_RB_RPTR_HI #define VPEC_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT … #define VPEC_QUEUE1_RB_RPTR_HI__OFFSET_MASK … //VPEC_QUEUE1_RB_WPTR #define VPEC_QUEUE1_RB_WPTR__OFFSET__SHIFT … #define VPEC_QUEUE1_RB_WPTR__OFFSET_MASK … //VPEC_QUEUE1_RB_WPTR_HI #define VPEC_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT … #define VPEC_QUEUE1_RB_WPTR_HI__OFFSET_MASK … //VPEC_QUEUE1_RB_RPTR_ADDR_HI #define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT … #define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK … //VPEC_QUEUE1_RB_RPTR_ADDR_LO #define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT … #define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK … //VPEC_QUEUE1_RB_AQL_CNTL #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT … #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT … #define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT … #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT … #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT … #define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT … #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK … #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK … #define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK … #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK … #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK … #define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK … //VPEC_QUEUE1_MINOR_PTR_UPDATE #define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT … #define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK … //VPEC_QUEUE1_CD_INFO #define VPEC_QUEUE1_CD_INFO__CD_INFO__SHIFT … #define VPEC_QUEUE1_CD_INFO__CD_INFO_MASK … //VPEC_QUEUE1_RB_PREEMPT #define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT … #define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK … //VPEC_QUEUE1_SKIP_CNTL #define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT … #define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK … //VPEC_QUEUE1_DOORBELL #define VPEC_QUEUE1_DOORBELL__ENABLE__SHIFT … #define VPEC_QUEUE1_DOORBELL__CAPTURED__SHIFT … #define VPEC_QUEUE1_DOORBELL__ENABLE_MASK … #define VPEC_QUEUE1_DOORBELL__CAPTURED_MASK … //VPEC_QUEUE1_DOORBELL_OFFSET #define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT … #define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK … //VPEC_QUEUE1_DUMMY0 #define VPEC_QUEUE1_DUMMY0__DUMMY__SHIFT … #define VPEC_QUEUE1_DUMMY0__DUMMY_MASK … //VPEC_QUEUE1_DUMMY1 #define VPEC_QUEUE1_DUMMY1__VALUE__SHIFT … #define VPEC_QUEUE1_DUMMY1__VALUE_MASK … //VPEC_QUEUE1_DUMMY2 #define VPEC_QUEUE1_DUMMY2__VALUE__SHIFT … #define VPEC_QUEUE1_DUMMY2__VALUE_MASK … //VPEC_QUEUE1_DUMMY3 #define VPEC_QUEUE1_DUMMY3__VALUE__SHIFT … #define VPEC_QUEUE1_DUMMY3__VALUE_MASK … //VPEC_QUEUE1_DUMMY4 #define VPEC_QUEUE1_DUMMY4__VALUE__SHIFT … #define VPEC_QUEUE1_DUMMY4__VALUE_MASK … //VPEC_QUEUE1_IB_CNTL #define VPEC_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT … #define VPEC_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT … #define VPEC_QUEUE1_IB_CNTL__CMD_VMID__SHIFT … #define VPEC_QUEUE1_IB_CNTL__IB_ENABLE_MASK … #define VPEC_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK … #define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK … #define VPEC_QUEUE1_IB_CNTL__CMD_VMID_MASK … //VPEC_QUEUE1_IB_RPTR #define VPEC_QUEUE1_IB_RPTR__OFFSET__SHIFT … #define VPEC_QUEUE1_IB_RPTR__OFFSET_MASK … //VPEC_QUEUE1_IB_OFFSET #define VPEC_QUEUE1_IB_OFFSET__OFFSET__SHIFT … #define VPEC_QUEUE1_IB_OFFSET__OFFSET_MASK … //VPEC_QUEUE1_IB_BASE_LO #define VPEC_QUEUE1_IB_BASE_LO__ADDR__SHIFT … #define VPEC_QUEUE1_IB_BASE_LO__ADDR_MASK … //VPEC_QUEUE1_IB_BASE_HI #define VPEC_QUEUE1_IB_BASE_HI__ADDR__SHIFT … #define VPEC_QUEUE1_IB_BASE_HI__ADDR_MASK … //VPEC_QUEUE1_IB_SIZE #define VPEC_QUEUE1_IB_SIZE__SIZE__SHIFT … #define VPEC_QUEUE1_IB_SIZE__SIZE_MASK … //VPEC_QUEUE1_CMDIB_CNTL #define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE__SHIFT … #define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT … #define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID__SHIFT … #define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE_MASK … #define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE_MASK … #define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK … #define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID_MASK … //VPEC_QUEUE1_CMDIB_RPTR #define VPEC_QUEUE1_CMDIB_RPTR__OFFSET__SHIFT … #define VPEC_QUEUE1_CMDIB_RPTR__OFFSET_MASK … //VPEC_QUEUE1_CMDIB_OFFSET #define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET__SHIFT … #define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET_MASK … //VPEC_QUEUE1_CMDIB_BASE_LO #define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR__SHIFT … #define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR_MASK … //VPEC_QUEUE1_CMDIB_BASE_HI #define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR__SHIFT … #define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR_MASK … //VPEC_QUEUE1_CMDIB_SIZE #define VPEC_QUEUE1_CMDIB_SIZE__SIZE__SHIFT … #define VPEC_QUEUE1_CMDIB_SIZE__SIZE_MASK … //VPEC_QUEUE1_CSA_ADDR_LO #define VPEC_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT … #define VPEC_QUEUE1_CSA_ADDR_LO__ADDR_MASK … //VPEC_QUEUE1_CSA_ADDR_HI #define VPEC_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT … #define VPEC_QUEUE1_CSA_ADDR_HI__ADDR_MASK … //VPEC_QUEUE1_CONTEXT_STATUS #define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT … #define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT … #define VPEC_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT … #define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT … #define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT … #define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT … #define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT … #define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT … #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT … #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … #define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED_MASK … #define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB_MASK … #define VPEC_QUEUE1_CONTEXT_STATUS__IDLE_MASK … #define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK … #define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK … #define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK … #define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK … #define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK … #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK … #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK … //VPEC_QUEUE1_DOORBELL_LOG //VPEC_QUEUE1_IB_SUB_REMAIN #define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT … #define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE_MASK … //VPEC_QUEUE1_PREEMPT #define VPEC_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT … #define VPEC_QUEUE1_PREEMPT__IB_PREEMPT_MASK … //VPEC_QUEUE2_RB_CNTL #define VPEC_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT … #define VPEC_QUEUE2_RB_CNTL__RB_SIZE__SHIFT … #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT … #define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT … #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT … #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT … #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT … #define VPEC_QUEUE2_RB_CNTL__RB_PRIV__SHIFT … #define VPEC_QUEUE2_RB_CNTL__RB_VMID__SHIFT … #define VPEC_QUEUE2_RB_CNTL__RB_ENABLE_MASK … #define VPEC_QUEUE2_RB_CNTL__RB_SIZE_MASK … #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK … #define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK … #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK … #define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK … #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK … #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK … #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK … #define VPEC_QUEUE2_RB_CNTL__RB_PRIV_MASK … #define VPEC_QUEUE2_RB_CNTL__RB_VMID_MASK … //VPEC_QUEUE2_SCHEDULE_CNTL #define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT … #define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT … #define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT … #define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT … #define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK … #define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK … #define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK … #define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK … //VPEC_QUEUE2_RB_BASE #define VPEC_QUEUE2_RB_BASE__ADDR__SHIFT … #define VPEC_QUEUE2_RB_BASE__ADDR_MASK … //VPEC_QUEUE2_RB_BASE_HI #define VPEC_QUEUE2_RB_BASE_HI__ADDR__SHIFT … #define VPEC_QUEUE2_RB_BASE_HI__ADDR_MASK … //VPEC_QUEUE2_RB_RPTR #define VPEC_QUEUE2_RB_RPTR__OFFSET__SHIFT … #define VPEC_QUEUE2_RB_RPTR__OFFSET_MASK … //VPEC_QUEUE2_RB_RPTR_HI #define VPEC_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT … #define VPEC_QUEUE2_RB_RPTR_HI__OFFSET_MASK … //VPEC_QUEUE2_RB_WPTR #define VPEC_QUEUE2_RB_WPTR__OFFSET__SHIFT … #define VPEC_QUEUE2_RB_WPTR__OFFSET_MASK … //VPEC_QUEUE2_RB_WPTR_HI #define VPEC_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT … #define VPEC_QUEUE2_RB_WPTR_HI__OFFSET_MASK … //VPEC_QUEUE2_RB_RPTR_ADDR_HI #define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT … #define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK … //VPEC_QUEUE2_RB_RPTR_ADDR_LO #define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT … #define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK … //VPEC_QUEUE2_RB_AQL_CNTL #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT … #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT … #define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT … #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT … #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT … #define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT … #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK … #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK … #define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK … #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK … #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK … #define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK … //VPEC_QUEUE2_MINOR_PTR_UPDATE #define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT … #define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK … //VPEC_QUEUE2_CD_INFO #define VPEC_QUEUE2_CD_INFO__CD_INFO__SHIFT … #define VPEC_QUEUE2_CD_INFO__CD_INFO_MASK
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