linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h

/*
 * Copyright (C) 2018  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef _sdma0_4_2_2_OFFSET_HEADER
#define _sdma0_4_2_2_OFFSET_HEADER



// addressBlock: sdma0_sdma0dec
// base address: 0x4980
#define mmSDMA0_UCODE_ADDR
#define mmSDMA0_UCODE_ADDR_BASE_IDX
#define mmSDMA0_UCODE_DATA
#define mmSDMA0_UCODE_DATA_BASE_IDX
#define mmSDMA0_VM_CNTL
#define mmSDMA0_VM_CNTL_BASE_IDX
#define mmSDMA0_VM_CTX_LO
#define mmSDMA0_VM_CTX_LO_BASE_IDX
#define mmSDMA0_VM_CTX_HI
#define mmSDMA0_VM_CTX_HI_BASE_IDX
#define mmSDMA0_ACTIVE_FCN_ID
#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX
#define mmSDMA0_VM_CTX_CNTL
#define mmSDMA0_VM_CTX_CNTL_BASE_IDX
#define mmSDMA0_VIRT_RESET_REQ
#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX
#define mmSDMA0_VF_ENABLE
#define mmSDMA0_VF_ENABLE_BASE_IDX
#define mmSDMA0_CONTEXT_REG_TYPE0
#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX
#define mmSDMA0_CONTEXT_REG_TYPE1
#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX
#define mmSDMA0_CONTEXT_REG_TYPE2
#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX
#define mmSDMA0_CONTEXT_REG_TYPE3
#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX
#define mmSDMA0_PUB_REG_TYPE0
#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX
#define mmSDMA0_PUB_REG_TYPE1
#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX
#define mmSDMA0_PUB_REG_TYPE2
#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX
#define mmSDMA0_PUB_REG_TYPE3
#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX
#define mmSDMA0_MMHUB_CNTL
#define mmSDMA0_MMHUB_CNTL_BASE_IDX
#define mmSDMA0_CONTEXT_GROUP_BOUNDARY
#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX
#define mmSDMA0_POWER_CNTL
#define mmSDMA0_POWER_CNTL_BASE_IDX
#define mmSDMA0_CLK_CTRL
#define mmSDMA0_CLK_CTRL_BASE_IDX
#define mmSDMA0_CNTL
#define mmSDMA0_CNTL_BASE_IDX
#define mmSDMA0_CHICKEN_BITS
#define mmSDMA0_CHICKEN_BITS_BASE_IDX
#define mmSDMA0_GB_ADDR_CONFIG
#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX
#define mmSDMA0_GB_ADDR_CONFIG_READ
#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX
#define mmSDMA0_RB_RPTR_FETCH_HI
#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX
#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX
#define mmSDMA0_RB_RPTR_FETCH
#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX
#define mmSDMA0_IB_OFFSET_FETCH
#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX
#define mmSDMA0_PROGRAM
#define mmSDMA0_PROGRAM_BASE_IDX
#define mmSDMA0_STATUS_REG
#define mmSDMA0_STATUS_REG_BASE_IDX
#define mmSDMA0_STATUS1_REG
#define mmSDMA0_STATUS1_REG_BASE_IDX
#define mmSDMA0_RD_BURST_CNTL
#define mmSDMA0_RD_BURST_CNTL_BASE_IDX
#define mmSDMA0_HBM_PAGE_CONFIG
#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX
#define mmSDMA0_UCODE_CHECKSUM
#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX
#define mmSDMA0_F32_CNTL
#define mmSDMA0_F32_CNTL_BASE_IDX
#define mmSDMA0_FREEZE
#define mmSDMA0_FREEZE_BASE_IDX
#define mmSDMA0_PHASE0_QUANTUM
#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX
#define mmSDMA0_PHASE1_QUANTUM
#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX
#define mmSDMA_POWER_GATING
#define mmSDMA_POWER_GATING_BASE_IDX
#define mmSDMA_PGFSM_CONFIG
#define mmSDMA_PGFSM_CONFIG_BASE_IDX
#define mmSDMA_PGFSM_WRITE
#define mmSDMA_PGFSM_WRITE_BASE_IDX
#define mmSDMA_PGFSM_READ
#define mmSDMA_PGFSM_READ_BASE_IDX
#define mmSDMA0_EDC_CONFIG
#define mmSDMA0_EDC_CONFIG_BASE_IDX
#define mmSDMA0_BA_THRESHOLD
#define mmSDMA0_BA_THRESHOLD_BASE_IDX
#define mmSDMA0_ID
#define mmSDMA0_ID_BASE_IDX
#define mmSDMA0_VERSION
#define mmSDMA0_VERSION_BASE_IDX
#define mmSDMA0_EDC_COUNTER
#define mmSDMA0_EDC_COUNTER_BASE_IDX
#define mmSDMA0_EDC_COUNTER_CLEAR
#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX
#define mmSDMA0_STATUS2_REG
#define mmSDMA0_STATUS2_REG_BASE_IDX
#define mmSDMA0_ATOMIC_CNTL
#define mmSDMA0_ATOMIC_CNTL_BASE_IDX
#define mmSDMA0_ATOMIC_PREOP_LO
#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX
#define mmSDMA0_ATOMIC_PREOP_HI
#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX
#define mmSDMA0_UTCL1_CNTL
#define mmSDMA0_UTCL1_CNTL_BASE_IDX
#define mmSDMA0_UTCL1_WATERMK
#define mmSDMA0_UTCL1_WATERMK_BASE_IDX
#define mmSDMA0_UTCL1_RD_STATUS
#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX
#define mmSDMA0_UTCL1_WR_STATUS
#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX
#define mmSDMA0_UTCL1_INV0
#define mmSDMA0_UTCL1_INV0_BASE_IDX
#define mmSDMA0_UTCL1_INV1
#define mmSDMA0_UTCL1_INV1_BASE_IDX
#define mmSDMA0_UTCL1_INV2
#define mmSDMA0_UTCL1_INV2_BASE_IDX
#define mmSDMA0_UTCL1_RD_XNACK0
#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX
#define mmSDMA0_UTCL1_RD_XNACK1
#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX
#define mmSDMA0_UTCL1_WR_XNACK0
#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX
#define mmSDMA0_UTCL1_WR_XNACK1
#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX
#define mmSDMA0_UTCL1_TIMEOUT
#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX
#define mmSDMA0_UTCL1_PAGE
#define mmSDMA0_UTCL1_PAGE_BASE_IDX
#define mmSDMA0_POWER_CNTL_IDLE
#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX
#define mmSDMA0_RELAX_ORDERING_LUT
#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX
#define mmSDMA0_CHICKEN_BITS_2
#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX
#define mmSDMA0_STATUS3_REG
#define mmSDMA0_STATUS3_REG_BASE_IDX
#define mmSDMA0_PHYSICAL_ADDR_LO
#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX
#define mmSDMA0_PHYSICAL_ADDR_HI
#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX
#define mmSDMA0_PHASE2_QUANTUM
#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX
#define mmSDMA0_ERROR_LOG
#define mmSDMA0_ERROR_LOG_BASE_IDX
#define mmSDMA0_PUB_DUMMY_REG0
#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX
#define mmSDMA0_PUB_DUMMY_REG1
#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX
#define mmSDMA0_PUB_DUMMY_REG2
#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX
#define mmSDMA0_PUB_DUMMY_REG3
#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX
#define mmSDMA0_F32_COUNTER
#define mmSDMA0_F32_COUNTER_BASE_IDX
#define mmSDMA0_UNBREAKABLE
#define mmSDMA0_UNBREAKABLE_BASE_IDX
#define mmSDMA0_PERFMON_CNTL
#define mmSDMA0_PERFMON_CNTL_BASE_IDX
#define mmSDMA0_PERFCOUNTER0_RESULT
#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX
#define mmSDMA0_PERFCOUNTER1_RESULT
#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX
#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE
#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX
#define mmSDMA0_CRD_CNTL
#define mmSDMA0_CRD_CNTL_BASE_IDX
#define mmSDMA0_GPU_IOV_VIOLATION_LOG
#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX
#define mmSDMA0_ULV_CNTL
#define mmSDMA0_ULV_CNTL_BASE_IDX
#define mmSDMA0_EA_DBIT_ADDR_DATA
#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX
#define mmSDMA0_EA_DBIT_ADDR_INDEX
#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX
#define mmSDMA0_GPU_IOV_VIOLATION_LOG2
#define mmSDMA0_GPU_IOV_VIOLATION_LOG2_BASE_IDX
#define mmSDMA0_GFX_RB_CNTL
#define mmSDMA0_GFX_RB_CNTL_BASE_IDX
#define mmSDMA0_GFX_RB_BASE
#define mmSDMA0_GFX_RB_BASE_BASE_IDX
#define mmSDMA0_GFX_RB_BASE_HI
#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX
#define mmSDMA0_GFX_RB_RPTR
#define mmSDMA0_GFX_RB_RPTR_BASE_IDX
#define mmSDMA0_GFX_RB_RPTR_HI
#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX
#define mmSDMA0_GFX_RB_WPTR
#define mmSDMA0_GFX_RB_WPTR_BASE_IDX
#define mmSDMA0_GFX_RB_WPTR_HI
#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX
#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL
#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX
#define mmSDMA0_GFX_RB_RPTR_ADDR_HI
#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX
#define mmSDMA0_GFX_RB_RPTR_ADDR_LO
#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX
#define mmSDMA0_GFX_IB_CNTL
#define mmSDMA0_GFX_IB_CNTL_BASE_IDX
#define mmSDMA0_GFX_IB_RPTR
#define mmSDMA0_GFX_IB_RPTR_BASE_IDX
#define mmSDMA0_GFX_IB_OFFSET
#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX
#define mmSDMA0_GFX_IB_BASE_LO
#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX
#define mmSDMA0_GFX_IB_BASE_HI
#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX
#define mmSDMA0_GFX_IB_SIZE
#define mmSDMA0_GFX_IB_SIZE_BASE_IDX
#define mmSDMA0_GFX_SKIP_CNTL
#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX
#define mmSDMA0_GFX_CONTEXT_STATUS
#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX
#define mmSDMA0_GFX_DOORBELL
#define mmSDMA0_GFX_DOORBELL_BASE_IDX
#define mmSDMA0_GFX_CONTEXT_CNTL
#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX
#define mmSDMA0_GFX_STATUS
#define mmSDMA0_GFX_STATUS_BASE_IDX
#define mmSDMA0_GFX_DOORBELL_LOG
#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX
#define mmSDMA0_GFX_WATERMARK
#define mmSDMA0_GFX_WATERMARK_BASE_IDX
#define mmSDMA0_GFX_DOORBELL_OFFSET
#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX
#define mmSDMA0_GFX_CSA_ADDR_LO
#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX
#define mmSDMA0_GFX_CSA_ADDR_HI
#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX
#define mmSDMA0_GFX_IB_SUB_REMAIN
#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX
#define mmSDMA0_GFX_PREEMPT
#define mmSDMA0_GFX_PREEMPT_BASE_IDX
#define mmSDMA0_GFX_DUMMY_REG
#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX
#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define mmSDMA0_GFX_RB_AQL_CNTL
#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX
#define mmSDMA0_GFX_MINOR_PTR_UPDATE
#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX
#define mmSDMA0_GFX_MIDCMD_DATA0
#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX
#define mmSDMA0_GFX_MIDCMD_DATA1
#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX
#define mmSDMA0_GFX_MIDCMD_DATA2
#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX
#define mmSDMA0_GFX_MIDCMD_DATA3
#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX
#define mmSDMA0_GFX_MIDCMD_DATA4
#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX
#define mmSDMA0_GFX_MIDCMD_DATA5
#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX
#define mmSDMA0_GFX_MIDCMD_DATA6
#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX
#define mmSDMA0_GFX_MIDCMD_DATA7
#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX
#define mmSDMA0_GFX_MIDCMD_DATA8
#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX
#define mmSDMA0_GFX_MIDCMD_CNTL
#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX
#define mmSDMA0_PAGE_RB_CNTL
#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX
#define mmSDMA0_PAGE_RB_BASE
#define mmSDMA0_PAGE_RB_BASE_BASE_IDX
#define mmSDMA0_PAGE_RB_BASE_HI
#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX
#define mmSDMA0_PAGE_RB_RPTR
#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX
#define mmSDMA0_PAGE_RB_RPTR_HI
#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX
#define mmSDMA0_PAGE_RB_WPTR
#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX
#define mmSDMA0_PAGE_RB_WPTR_HI
#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX
#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL
#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX
#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI
#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX
#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO
#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX
#define mmSDMA0_PAGE_IB_CNTL
#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX
#define mmSDMA0_PAGE_IB_RPTR
#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX
#define mmSDMA0_PAGE_IB_OFFSET
#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX
#define mmSDMA0_PAGE_IB_BASE_LO
#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX
#define mmSDMA0_PAGE_IB_BASE_HI
#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX
#define mmSDMA0_PAGE_IB_SIZE
#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX
#define mmSDMA0_PAGE_SKIP_CNTL
#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX
#define mmSDMA0_PAGE_CONTEXT_STATUS
#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX
#define mmSDMA0_PAGE_DOORBELL
#define mmSDMA0_PAGE_DOORBELL_BASE_IDX
#define mmSDMA0_PAGE_STATUS
#define mmSDMA0_PAGE_STATUS_BASE_IDX
#define mmSDMA0_PAGE_DOORBELL_LOG
#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX
#define mmSDMA0_PAGE_WATERMARK
#define mmSDMA0_PAGE_WATERMARK_BASE_IDX
#define mmSDMA0_PAGE_DOORBELL_OFFSET
#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX
#define mmSDMA0_PAGE_CSA_ADDR_LO
#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX
#define mmSDMA0_PAGE_CSA_ADDR_HI
#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX
#define mmSDMA0_PAGE_IB_SUB_REMAIN
#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX
#define mmSDMA0_PAGE_PREEMPT
#define mmSDMA0_PAGE_PREEMPT_BASE_IDX
#define mmSDMA0_PAGE_DUMMY_REG
#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX
#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define mmSDMA0_PAGE_RB_AQL_CNTL
#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX
#define mmSDMA0_PAGE_MINOR_PTR_UPDATE
#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX
#define mmSDMA0_PAGE_MIDCMD_DATA0
#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX
#define mmSDMA0_PAGE_MIDCMD_DATA1
#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX
#define mmSDMA0_PAGE_MIDCMD_DATA2
#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX
#define mmSDMA0_PAGE_MIDCMD_DATA3
#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX
#define mmSDMA0_PAGE_MIDCMD_DATA4
#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX
#define mmSDMA0_PAGE_MIDCMD_DATA5
#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX
#define mmSDMA0_PAGE_MIDCMD_DATA6
#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX
#define mmSDMA0_PAGE_MIDCMD_DATA7
#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX
#define mmSDMA0_PAGE_MIDCMD_DATA8
#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX
#define mmSDMA0_PAGE_MIDCMD_CNTL
#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX
#define mmSDMA0_RLC0_RB_CNTL
#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX
#define mmSDMA0_RLC0_RB_BASE
#define mmSDMA0_RLC0_RB_BASE_BASE_IDX
#define mmSDMA0_RLC0_RB_BASE_HI
#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC0_RB_RPTR
#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX
#define mmSDMA0_RLC0_RB_RPTR_HI
#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX
#define mmSDMA0_RLC0_RB_WPTR
#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX
#define mmSDMA0_RLC0_RB_WPTR_HI
#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX
#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL
#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX
#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI
#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO
#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC0_IB_CNTL
#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX
#define mmSDMA0_RLC0_IB_RPTR
#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX
#define mmSDMA0_RLC0_IB_OFFSET
#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX
#define mmSDMA0_RLC0_IB_BASE_LO
#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX
#define mmSDMA0_RLC0_IB_BASE_HI
#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC0_IB_SIZE
#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX
#define mmSDMA0_RLC0_SKIP_CNTL
#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX
#define mmSDMA0_RLC0_CONTEXT_STATUS
#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX
#define mmSDMA0_RLC0_DOORBELL
#define mmSDMA0_RLC0_DOORBELL_BASE_IDX
#define mmSDMA0_RLC0_STATUS
#define mmSDMA0_RLC0_STATUS_BASE_IDX
#define mmSDMA0_RLC0_DOORBELL_LOG
#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX
#define mmSDMA0_RLC0_WATERMARK
#define mmSDMA0_RLC0_WATERMARK_BASE_IDX
#define mmSDMA0_RLC0_DOORBELL_OFFSET
#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX
#define mmSDMA0_RLC0_CSA_ADDR_LO
#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC0_CSA_ADDR_HI
#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC0_IB_SUB_REMAIN
#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX
#define mmSDMA0_RLC0_PREEMPT
#define mmSDMA0_RLC0_PREEMPT_BASE_IDX
#define mmSDMA0_RLC0_DUMMY_REG
#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX
#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC0_RB_AQL_CNTL
#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX
#define mmSDMA0_RLC0_MINOR_PTR_UPDATE
#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX
#define mmSDMA0_RLC0_MIDCMD_DATA0
#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX
#define mmSDMA0_RLC0_MIDCMD_DATA1
#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX
#define mmSDMA0_RLC0_MIDCMD_DATA2
#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX
#define mmSDMA0_RLC0_MIDCMD_DATA3
#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX
#define mmSDMA0_RLC0_MIDCMD_DATA4
#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX
#define mmSDMA0_RLC0_MIDCMD_DATA5
#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX
#define mmSDMA0_RLC0_MIDCMD_DATA6
#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX
#define mmSDMA0_RLC0_MIDCMD_DATA7
#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX
#define mmSDMA0_RLC0_MIDCMD_DATA8
#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX
#define mmSDMA0_RLC0_MIDCMD_CNTL
#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX
#define mmSDMA0_RLC1_RB_CNTL
#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX
#define mmSDMA0_RLC1_RB_BASE
#define mmSDMA0_RLC1_RB_BASE_BASE_IDX
#define mmSDMA0_RLC1_RB_BASE_HI
#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC1_RB_RPTR
#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX
#define mmSDMA0_RLC1_RB_RPTR_HI
#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX
#define mmSDMA0_RLC1_RB_WPTR
#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX
#define mmSDMA0_RLC1_RB_WPTR_HI
#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX
#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL
#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX
#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI
#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO
#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC1_IB_CNTL
#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX
#define mmSDMA0_RLC1_IB_RPTR
#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX
#define mmSDMA0_RLC1_IB_OFFSET
#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX
#define mmSDMA0_RLC1_IB_BASE_LO
#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX
#define mmSDMA0_RLC1_IB_BASE_HI
#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC1_IB_SIZE
#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX
#define mmSDMA0_RLC1_SKIP_CNTL
#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX
#define mmSDMA0_RLC1_CONTEXT_STATUS
#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX
#define mmSDMA0_RLC1_DOORBELL
#define mmSDMA0_RLC1_DOORBELL_BASE_IDX
#define mmSDMA0_RLC1_STATUS
#define mmSDMA0_RLC1_STATUS_BASE_IDX
#define mmSDMA0_RLC1_DOORBELL_LOG
#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX
#define mmSDMA0_RLC1_WATERMARK
#define mmSDMA0_RLC1_WATERMARK_BASE_IDX
#define mmSDMA0_RLC1_DOORBELL_OFFSET
#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX
#define mmSDMA0_RLC1_CSA_ADDR_LO
#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC1_CSA_ADDR_HI
#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC1_IB_SUB_REMAIN
#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX
#define mmSDMA0_RLC1_PREEMPT
#define mmSDMA0_RLC1_PREEMPT_BASE_IDX
#define mmSDMA0_RLC1_DUMMY_REG
#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX
#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC1_RB_AQL_CNTL
#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX
#define mmSDMA0_RLC1_MINOR_PTR_UPDATE
#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX
#define mmSDMA0_RLC1_MIDCMD_DATA0
#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX
#define mmSDMA0_RLC1_MIDCMD_DATA1
#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX
#define mmSDMA0_RLC1_MIDCMD_DATA2
#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX
#define mmSDMA0_RLC1_MIDCMD_DATA3
#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX
#define mmSDMA0_RLC1_MIDCMD_DATA4
#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX
#define mmSDMA0_RLC1_MIDCMD_DATA5
#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX
#define mmSDMA0_RLC1_MIDCMD_DATA6
#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX
#define mmSDMA0_RLC1_MIDCMD_DATA7
#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX
#define mmSDMA0_RLC1_MIDCMD_DATA8
#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX
#define mmSDMA0_RLC1_MIDCMD_CNTL
#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX
#define mmSDMA0_RLC2_RB_CNTL
#define mmSDMA0_RLC2_RB_CNTL_BASE_IDX
#define mmSDMA0_RLC2_RB_BASE
#define mmSDMA0_RLC2_RB_BASE_BASE_IDX
#define mmSDMA0_RLC2_RB_BASE_HI
#define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC2_RB_RPTR
#define mmSDMA0_RLC2_RB_RPTR_BASE_IDX
#define mmSDMA0_RLC2_RB_RPTR_HI
#define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX
#define mmSDMA0_RLC2_RB_WPTR
#define mmSDMA0_RLC2_RB_WPTR_BASE_IDX
#define mmSDMA0_RLC2_RB_WPTR_HI
#define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX
#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL
#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX
#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI
#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO
#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC2_IB_CNTL
#define mmSDMA0_RLC2_IB_CNTL_BASE_IDX
#define mmSDMA0_RLC2_IB_RPTR
#define mmSDMA0_RLC2_IB_RPTR_BASE_IDX
#define mmSDMA0_RLC2_IB_OFFSET
#define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX
#define mmSDMA0_RLC2_IB_BASE_LO
#define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX
#define mmSDMA0_RLC2_IB_BASE_HI
#define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC2_IB_SIZE
#define mmSDMA0_RLC2_IB_SIZE_BASE_IDX
#define mmSDMA0_RLC2_SKIP_CNTL
#define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX
#define mmSDMA0_RLC2_CONTEXT_STATUS
#define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX
#define mmSDMA0_RLC2_DOORBELL
#define mmSDMA0_RLC2_DOORBELL_BASE_IDX
#define mmSDMA0_RLC2_STATUS
#define mmSDMA0_RLC2_STATUS_BASE_IDX
#define mmSDMA0_RLC2_DOORBELL_LOG
#define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX
#define mmSDMA0_RLC2_WATERMARK
#define mmSDMA0_RLC2_WATERMARK_BASE_IDX
#define mmSDMA0_RLC2_DOORBELL_OFFSET
#define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX
#define mmSDMA0_RLC2_CSA_ADDR_LO
#define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC2_CSA_ADDR_HI
#define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC2_IB_SUB_REMAIN
#define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX
#define mmSDMA0_RLC2_PREEMPT
#define mmSDMA0_RLC2_PREEMPT_BASE_IDX
#define mmSDMA0_RLC2_DUMMY_REG
#define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX
#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC2_RB_AQL_CNTL
#define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX
#define mmSDMA0_RLC2_MINOR_PTR_UPDATE
#define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX
#define mmSDMA0_RLC2_MIDCMD_DATA0
#define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX
#define mmSDMA0_RLC2_MIDCMD_DATA1
#define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX
#define mmSDMA0_RLC2_MIDCMD_DATA2
#define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX
#define mmSDMA0_RLC2_MIDCMD_DATA3
#define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX
#define mmSDMA0_RLC2_MIDCMD_DATA4
#define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX
#define mmSDMA0_RLC2_MIDCMD_DATA5
#define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX
#define mmSDMA0_RLC2_MIDCMD_DATA6
#define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX
#define mmSDMA0_RLC2_MIDCMD_DATA7
#define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX
#define mmSDMA0_RLC2_MIDCMD_DATA8
#define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX
#define mmSDMA0_RLC2_MIDCMD_CNTL
#define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX
#define mmSDMA0_RLC3_RB_CNTL
#define mmSDMA0_RLC3_RB_CNTL_BASE_IDX
#define mmSDMA0_RLC3_RB_BASE
#define mmSDMA0_RLC3_RB_BASE_BASE_IDX
#define mmSDMA0_RLC3_RB_BASE_HI
#define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC3_RB_RPTR
#define mmSDMA0_RLC3_RB_RPTR_BASE_IDX
#define mmSDMA0_RLC3_RB_RPTR_HI
#define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX
#define mmSDMA0_RLC3_RB_WPTR
#define mmSDMA0_RLC3_RB_WPTR_BASE_IDX
#define mmSDMA0_RLC3_RB_WPTR_HI
#define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX
#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL
#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX
#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI
#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO
#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC3_IB_CNTL
#define mmSDMA0_RLC3_IB_CNTL_BASE_IDX
#define mmSDMA0_RLC3_IB_RPTR
#define mmSDMA0_RLC3_IB_RPTR_BASE_IDX
#define mmSDMA0_RLC3_IB_OFFSET
#define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX
#define mmSDMA0_RLC3_IB_BASE_LO
#define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX
#define mmSDMA0_RLC3_IB_BASE_HI
#define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC3_IB_SIZE
#define mmSDMA0_RLC3_IB_SIZE_BASE_IDX
#define mmSDMA0_RLC3_SKIP_CNTL
#define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX
#define mmSDMA0_RLC3_CONTEXT_STATUS
#define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX
#define mmSDMA0_RLC3_DOORBELL
#define mmSDMA0_RLC3_DOORBELL_BASE_IDX
#define mmSDMA0_RLC3_STATUS
#define mmSDMA0_RLC3_STATUS_BASE_IDX
#define mmSDMA0_RLC3_DOORBELL_LOG
#define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX
#define mmSDMA0_RLC3_WATERMARK
#define mmSDMA0_RLC3_WATERMARK_BASE_IDX
#define mmSDMA0_RLC3_DOORBELL_OFFSET
#define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX
#define mmSDMA0_RLC3_CSA_ADDR_LO
#define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC3_CSA_ADDR_HI
#define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC3_IB_SUB_REMAIN
#define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX
#define mmSDMA0_RLC3_PREEMPT
#define mmSDMA0_RLC3_PREEMPT_BASE_IDX
#define mmSDMA0_RLC3_DUMMY_REG
#define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX
#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC3_RB_AQL_CNTL
#define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX
#define mmSDMA0_RLC3_MINOR_PTR_UPDATE
#define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX
#define mmSDMA0_RLC3_MIDCMD_DATA0
#define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX
#define mmSDMA0_RLC3_MIDCMD_DATA1
#define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX
#define mmSDMA0_RLC3_MIDCMD_DATA2
#define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX
#define mmSDMA0_RLC3_MIDCMD_DATA3
#define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX
#define mmSDMA0_RLC3_MIDCMD_DATA4
#define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX
#define mmSDMA0_RLC3_MIDCMD_DATA5
#define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX
#define mmSDMA0_RLC3_MIDCMD_DATA6
#define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX
#define mmSDMA0_RLC3_MIDCMD_DATA7
#define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX
#define mmSDMA0_RLC3_MIDCMD_DATA8
#define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX
#define mmSDMA0_RLC3_MIDCMD_CNTL
#define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX
#define mmSDMA0_RLC4_RB_CNTL
#define mmSDMA0_RLC4_RB_CNTL_BASE_IDX
#define mmSDMA0_RLC4_RB_BASE
#define mmSDMA0_RLC4_RB_BASE_BASE_IDX
#define mmSDMA0_RLC4_RB_BASE_HI
#define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC4_RB_RPTR
#define mmSDMA0_RLC4_RB_RPTR_BASE_IDX
#define mmSDMA0_RLC4_RB_RPTR_HI
#define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX
#define mmSDMA0_RLC4_RB_WPTR
#define mmSDMA0_RLC4_RB_WPTR_BASE_IDX
#define mmSDMA0_RLC4_RB_WPTR_HI
#define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX
#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL
#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX
#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI
#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO
#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC4_IB_CNTL
#define mmSDMA0_RLC4_IB_CNTL_BASE_IDX
#define mmSDMA0_RLC4_IB_RPTR
#define mmSDMA0_RLC4_IB_RPTR_BASE_IDX
#define mmSDMA0_RLC4_IB_OFFSET
#define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX
#define mmSDMA0_RLC4_IB_BASE_LO
#define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX
#define mmSDMA0_RLC4_IB_BASE_HI
#define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC4_IB_SIZE
#define mmSDMA0_RLC4_IB_SIZE_BASE_IDX
#define mmSDMA0_RLC4_SKIP_CNTL
#define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX
#define mmSDMA0_RLC4_CONTEXT_STATUS
#define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX
#define mmSDMA0_RLC4_DOORBELL
#define mmSDMA0_RLC4_DOORBELL_BASE_IDX
#define mmSDMA0_RLC4_STATUS
#define mmSDMA0_RLC4_STATUS_BASE_IDX
#define mmSDMA0_RLC4_DOORBELL_LOG
#define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX
#define mmSDMA0_RLC4_WATERMARK
#define mmSDMA0_RLC4_WATERMARK_BASE_IDX
#define mmSDMA0_RLC4_DOORBELL_OFFSET
#define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX
#define mmSDMA0_RLC4_CSA_ADDR_LO
#define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC4_CSA_ADDR_HI
#define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC4_IB_SUB_REMAIN
#define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX
#define mmSDMA0_RLC4_PREEMPT
#define mmSDMA0_RLC4_PREEMPT_BASE_IDX
#define mmSDMA0_RLC4_DUMMY_REG
#define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX
#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC4_RB_AQL_CNTL
#define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX
#define mmSDMA0_RLC4_MINOR_PTR_UPDATE
#define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX
#define mmSDMA0_RLC4_MIDCMD_DATA0
#define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX
#define mmSDMA0_RLC4_MIDCMD_DATA1
#define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX
#define mmSDMA0_RLC4_MIDCMD_DATA2
#define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX
#define mmSDMA0_RLC4_MIDCMD_DATA3
#define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX
#define mmSDMA0_RLC4_MIDCMD_DATA4
#define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX
#define mmSDMA0_RLC4_MIDCMD_DATA5
#define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX
#define mmSDMA0_RLC4_MIDCMD_DATA6
#define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX
#define mmSDMA0_RLC4_MIDCMD_DATA7
#define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX
#define mmSDMA0_RLC4_MIDCMD_DATA8
#define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX
#define mmSDMA0_RLC4_MIDCMD_CNTL
#define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX
#define mmSDMA0_RLC5_RB_CNTL
#define mmSDMA0_RLC5_RB_CNTL_BASE_IDX
#define mmSDMA0_RLC5_RB_BASE
#define mmSDMA0_RLC5_RB_BASE_BASE_IDX
#define mmSDMA0_RLC5_RB_BASE_HI
#define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC5_RB_RPTR
#define mmSDMA0_RLC5_RB_RPTR_BASE_IDX
#define mmSDMA0_RLC5_RB_RPTR_HI
#define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX
#define mmSDMA0_RLC5_RB_WPTR
#define mmSDMA0_RLC5_RB_WPTR_BASE_IDX
#define mmSDMA0_RLC5_RB_WPTR_HI
#define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX
#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL
#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX
#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI
#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO
#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC5_IB_CNTL
#define mmSDMA0_RLC5_IB_CNTL_BASE_IDX
#define mmSDMA0_RLC5_IB_RPTR
#define mmSDMA0_RLC5_IB_RPTR_BASE_IDX
#define mmSDMA0_RLC5_IB_OFFSET
#define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX
#define mmSDMA0_RLC5_IB_BASE_LO
#define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX
#define mmSDMA0_RLC5_IB_BASE_HI
#define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC5_IB_SIZE
#define mmSDMA0_RLC5_IB_SIZE_BASE_IDX
#define mmSDMA0_RLC5_SKIP_CNTL
#define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX
#define mmSDMA0_RLC5_CONTEXT_STATUS
#define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX
#define mmSDMA0_RLC5_DOORBELL
#define mmSDMA0_RLC5_DOORBELL_BASE_IDX
#define mmSDMA0_RLC5_STATUS
#define mmSDMA0_RLC5_STATUS_BASE_IDX
#define mmSDMA0_RLC5_DOORBELL_LOG
#define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX
#define mmSDMA0_RLC5_WATERMARK
#define mmSDMA0_RLC5_WATERMARK_BASE_IDX
#define mmSDMA0_RLC5_DOORBELL_OFFSET
#define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX
#define mmSDMA0_RLC5_CSA_ADDR_LO
#define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC5_CSA_ADDR_HI
#define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC5_IB_SUB_REMAIN
#define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX
#define mmSDMA0_RLC5_PREEMPT
#define mmSDMA0_RLC5_PREEMPT_BASE_IDX
#define mmSDMA0_RLC5_DUMMY_REG
#define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX
#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC5_RB_AQL_CNTL
#define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX
#define mmSDMA0_RLC5_MINOR_PTR_UPDATE
#define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX
#define mmSDMA0_RLC5_MIDCMD_DATA0
#define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX
#define mmSDMA0_RLC5_MIDCMD_DATA1
#define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX
#define mmSDMA0_RLC5_MIDCMD_DATA2
#define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX
#define mmSDMA0_RLC5_MIDCMD_DATA3
#define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX
#define mmSDMA0_RLC5_MIDCMD_DATA4
#define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX
#define mmSDMA0_RLC5_MIDCMD_DATA5
#define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX
#define mmSDMA0_RLC5_MIDCMD_DATA6
#define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX
#define mmSDMA0_RLC5_MIDCMD_DATA7
#define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX
#define mmSDMA0_RLC5_MIDCMD_DATA8
#define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX
#define mmSDMA0_RLC5_MIDCMD_CNTL
#define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX
#define mmSDMA0_RLC6_RB_CNTL
#define mmSDMA0_RLC6_RB_CNTL_BASE_IDX
#define mmSDMA0_RLC6_RB_BASE
#define mmSDMA0_RLC6_RB_BASE_BASE_IDX
#define mmSDMA0_RLC6_RB_BASE_HI
#define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC6_RB_RPTR
#define mmSDMA0_RLC6_RB_RPTR_BASE_IDX
#define mmSDMA0_RLC6_RB_RPTR_HI
#define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX
#define mmSDMA0_RLC6_RB_WPTR
#define mmSDMA0_RLC6_RB_WPTR_BASE_IDX
#define mmSDMA0_RLC6_RB_WPTR_HI
#define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX
#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL
#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX
#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI
#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO
#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC6_IB_CNTL
#define mmSDMA0_RLC6_IB_CNTL_BASE_IDX
#define mmSDMA0_RLC6_IB_RPTR
#define mmSDMA0_RLC6_IB_RPTR_BASE_IDX
#define mmSDMA0_RLC6_IB_OFFSET
#define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX
#define mmSDMA0_RLC6_IB_BASE_LO
#define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX
#define mmSDMA0_RLC6_IB_BASE_HI
#define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC6_IB_SIZE
#define mmSDMA0_RLC6_IB_SIZE_BASE_IDX
#define mmSDMA0_RLC6_SKIP_CNTL
#define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX
#define mmSDMA0_RLC6_CONTEXT_STATUS
#define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX
#define mmSDMA0_RLC6_DOORBELL
#define mmSDMA0_RLC6_DOORBELL_BASE_IDX
#define mmSDMA0_RLC6_STATUS
#define mmSDMA0_RLC6_STATUS_BASE_IDX
#define mmSDMA0_RLC6_DOORBELL_LOG
#define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX
#define mmSDMA0_RLC6_WATERMARK
#define mmSDMA0_RLC6_WATERMARK_BASE_IDX
#define mmSDMA0_RLC6_DOORBELL_OFFSET
#define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX
#define mmSDMA0_RLC6_CSA_ADDR_LO
#define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC6_CSA_ADDR_HI
#define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC6_IB_SUB_REMAIN
#define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX
#define mmSDMA0_RLC6_PREEMPT
#define mmSDMA0_RLC6_PREEMPT_BASE_IDX
#define mmSDMA0_RLC6_DUMMY_REG
#define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX
#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC6_RB_AQL_CNTL
#define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX
#define mmSDMA0_RLC6_MINOR_PTR_UPDATE
#define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX
#define mmSDMA0_RLC6_MIDCMD_DATA0
#define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX
#define mmSDMA0_RLC6_MIDCMD_DATA1
#define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX
#define mmSDMA0_RLC6_MIDCMD_DATA2
#define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX
#define mmSDMA0_RLC6_MIDCMD_DATA3
#define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX
#define mmSDMA0_RLC6_MIDCMD_DATA4
#define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX
#define mmSDMA0_RLC6_MIDCMD_DATA5
#define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX
#define mmSDMA0_RLC6_MIDCMD_DATA6
#define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX
#define mmSDMA0_RLC6_MIDCMD_DATA7
#define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX
#define mmSDMA0_RLC6_MIDCMD_DATA8
#define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX
#define mmSDMA0_RLC6_MIDCMD_CNTL
#define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX
#define mmSDMA0_RLC7_RB_CNTL
#define mmSDMA0_RLC7_RB_CNTL_BASE_IDX
#define mmSDMA0_RLC7_RB_BASE
#define mmSDMA0_RLC7_RB_BASE_BASE_IDX
#define mmSDMA0_RLC7_RB_BASE_HI
#define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC7_RB_RPTR
#define mmSDMA0_RLC7_RB_RPTR_BASE_IDX
#define mmSDMA0_RLC7_RB_RPTR_HI
#define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX
#define mmSDMA0_RLC7_RB_WPTR
#define mmSDMA0_RLC7_RB_WPTR_BASE_IDX
#define mmSDMA0_RLC7_RB_WPTR_HI
#define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX
#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL
#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX
#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI
#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO
#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC7_IB_CNTL
#define mmSDMA0_RLC7_IB_CNTL_BASE_IDX
#define mmSDMA0_RLC7_IB_RPTR
#define mmSDMA0_RLC7_IB_RPTR_BASE_IDX
#define mmSDMA0_RLC7_IB_OFFSET
#define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX
#define mmSDMA0_RLC7_IB_BASE_LO
#define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX
#define mmSDMA0_RLC7_IB_BASE_HI
#define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX
#define mmSDMA0_RLC7_IB_SIZE
#define mmSDMA0_RLC7_IB_SIZE_BASE_IDX
#define mmSDMA0_RLC7_SKIP_CNTL
#define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX
#define mmSDMA0_RLC7_CONTEXT_STATUS
#define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX
#define mmSDMA0_RLC7_DOORBELL
#define mmSDMA0_RLC7_DOORBELL_BASE_IDX
#define mmSDMA0_RLC7_STATUS
#define mmSDMA0_RLC7_STATUS_BASE_IDX
#define mmSDMA0_RLC7_DOORBELL_LOG
#define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX
#define mmSDMA0_RLC7_WATERMARK
#define mmSDMA0_RLC7_WATERMARK_BASE_IDX
#define mmSDMA0_RLC7_DOORBELL_OFFSET
#define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX
#define mmSDMA0_RLC7_CSA_ADDR_LO
#define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC7_CSA_ADDR_HI
#define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC7_IB_SUB_REMAIN
#define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX
#define mmSDMA0_RLC7_PREEMPT
#define mmSDMA0_RLC7_PREEMPT_BASE_IDX
#define mmSDMA0_RLC7_DUMMY_REG
#define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX
#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define mmSDMA0_RLC7_RB_AQL_CNTL
#define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX
#define mmSDMA0_RLC7_MINOR_PTR_UPDATE
#define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX
#define mmSDMA0_RLC7_MIDCMD_DATA0
#define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX
#define mmSDMA0_RLC7_MIDCMD_DATA1
#define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX
#define mmSDMA0_RLC7_MIDCMD_DATA2
#define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX
#define mmSDMA0_RLC7_MIDCMD_DATA3
#define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX
#define mmSDMA0_RLC7_MIDCMD_DATA4
#define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX
#define mmSDMA0_RLC7_MIDCMD_DATA5
#define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX
#define mmSDMA0_RLC7_MIDCMD_DATA6
#define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX
#define mmSDMA0_RLC7_MIDCMD_DATA7
#define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX
#define mmSDMA0_RLC7_MIDCMD_DATA8
#define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX
#define mmSDMA0_RLC7_MIDCMD_CNTL
#define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX

#endif