/* * SMU_8_0 Register documentation * * Copyright (C) 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef SMU_8_0_SH_MASK_H #define SMU_8_0_SH_MASK_H #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK … #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT … #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK … #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT … #define THM_TCON_CSR_DATA__TCC_DATA_MASK … #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT … #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK … #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT … #define THM_TCON_HTC__HTC_EN_MASK … #define THM_TCON_HTC__HTC_EN__SHIFT … #define THM_TCON_HTC__RSVD0_MASK … #define THM_TCON_HTC__RSVD0__SHIFT … #define THM_TCON_HTC__HTC_P_STATE_EN_MASK … #define THM_TCON_HTC__HTC_P_STATE_EN__SHIFT … #define THM_TCON_HTC__RSVD1_MASK … #define THM_TCON_HTC__RSVD1__SHIFT … #define THM_TCON_HTC__HTC_ACTIVE_MASK … #define THM_TCON_HTC__HTC_ACTIVE__SHIFT … #define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK … #define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT … #define THM_TCON_HTC__HTC_APIC_HI_EN_MASK … #define THM_TCON_HTC__HTC_APIC_HI_EN__SHIFT … #define THM_TCON_HTC__HTC_APIC_LO_EN_MASK … #define THM_TCON_HTC__HTC_APIC_LO_EN__SHIFT … #define THM_TCON_HTC__HTC_DIAG_MASK … #define THM_TCON_HTC__HTC_DIAG__SHIFT … #define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK … #define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT … #define THM_TCON_HTC__HTC_TO_GNB_EN_MASK … #define THM_TCON_HTC__HTC_TO_GNB_EN__SHIFT … #define THM_TCON_HTC__PROCHOT_TO_GNB_EN_MASK … #define THM_TCON_HTC__PROCHOT_TO_GNB_EN__SHIFT … #define THM_TCON_HTC__RSVD2_MASK … #define THM_TCON_HTC__RSVD2__SHIFT … #define THM_TCON_HTC__HTC_TMP_LMT_MASK … #define THM_TCON_HTC__HTC_TMP_LMT__SHIFT … #define THM_TCON_HTC__HTC_SLEW_SEL_MASK … #define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT … #define THM_TCON_HTC__HTC_HYST_LMT_MASK … #define THM_TCON_HTC__HTC_HYST_LMT__SHIFT … #define THM_TCON_HTC__HTC_PSTATE_LIMIT_MASK … #define THM_TCON_HTC__HTC_PSTATE_LIMIT__SHIFT … #define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK … #define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT … #define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK … #define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT … #define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK … #define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT … #define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK … #define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT … #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK … #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT … #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK … #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT … #define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK … #define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT … #define THM_TCON_CUR_TMP__CUR_TEMP_MASK … #define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT … #define THM_TCON_THERM_TRIP__RSVD0_MASK … #define THM_TCON_THERM_TRIP__RSVD0__SHIFT … #define THM_TCON_THERM_TRIP__THERM_TP_MASK … #define THM_TCON_THERM_TRIP__THERM_TP__SHIFT … #define THM_TCON_THERM_TRIP__RSVD1_MASK … #define THM_TCON_THERM_TRIP__RSVD1__SHIFT … #define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK … #define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT … #define THM_TCON_THERM_TRIP__RSVD2_MASK … #define THM_TCON_THERM_TRIP__RSVD2__SHIFT … #define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK … #define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT … #define THM_TCON_THERM_TRIP__RSVD3_MASK … #define THM_TCON_THERM_TRIP__RSVD3__SHIFT … #define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK … #define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT … #define THM_GPIO_PROCHOT_CTRL__TX12_EN_MASK … #define THM_GPIO_PROCHOT_CTRL__TX12_EN__SHIFT … #define THM_GPIO_PROCHOT_CTRL__PD_MASK … #define THM_GPIO_PROCHOT_CTRL__PD__SHIFT … #define THM_GPIO_PROCHOT_CTRL__PU_MASK … #define THM_GPIO_PROCHOT_CTRL__PU__SHIFT … #define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK … #define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT … #define THM_GPIO_PROCHOT_CTRL__SN_MASK … #define THM_GPIO_PROCHOT_CTRL__SN__SHIFT … #define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK … #define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT … #define THM_GPIO_PROCHOT_CTRL__OE_MASK … #define THM_GPIO_PROCHOT_CTRL__OE__SHIFT … #define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK … #define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT … #define THM_GPIO_PROCHOT_CTRL__A_MASK … #define THM_GPIO_PROCHOT_CTRL__A__SHIFT … #define THM_GPIO_PROCHOT_CTRL__Y_MASK … #define THM_GPIO_PROCHOT_CTRL__Y__SHIFT … #define THM_GPIO_THERMTRIP_CTRL__TX12_EN_MASK … #define THM_GPIO_THERMTRIP_CTRL__TX12_EN__SHIFT … #define THM_GPIO_THERMTRIP_CTRL__PD_MASK … #define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT … #define THM_GPIO_THERMTRIP_CTRL__PU_MASK … #define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT … #define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK … #define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT … #define THM_GPIO_THERMTRIP_CTRL__SN_MASK … #define THM_GPIO_THERMTRIP_CTRL__SN__SHIFT … #define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK … #define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT … #define THM_GPIO_THERMTRIP_CTRL__OE_MASK … #define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT … #define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK … #define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT … #define THM_GPIO_THERMTRIP_CTRL__A_MASK … #define THM_GPIO_THERMTRIP_CTRL__A__SHIFT … #define THM_GPIO_THERMTRIP_CTRL__Y_MASK … #define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT … #define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK … #define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT … #define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK … #define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT … #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK … #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT … #define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK … #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT … #define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK … #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT … #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK … #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT … #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK … #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT … #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK … #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT … #define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK … #define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT … #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK … #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT … #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK … #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT … #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK … #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT … #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK … #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT … #define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK … #define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT … #define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK … #define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT … #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK … #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT … #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK … #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT … #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK … #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT … #define TMON0_RDIL0_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL0_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL1_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL1_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL2_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL2_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL3_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL3_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL4_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL4_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL5_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL5_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL6_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL6_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL7_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL7_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL8_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL8_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL9_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL9_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL10_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL10_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL11_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL11_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL12_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL12_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL13_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL13_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL14_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL14_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL15_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIL15_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR0_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR0_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR1_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR1_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR2_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR2_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR3_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR3_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR4_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR4_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR5_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR5_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR6_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR6_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR7_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR7_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR8_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR8_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR9_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR9_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR10_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR10_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR11_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR11_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR12_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR12_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR13_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR13_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR14_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR14_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIR15_DATA__TEMP_Z_DATA_MASK … #define TMON0_RDIR15_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_INT_DATA__TEMP_Z_DATA_MASK … #define TMON0_INT_DATA__TEMP_Z_DATA__SHIFT … #define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK … #define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT … #define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK … #define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT … #define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK … #define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT … #define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK … #define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT … #define TMON0_CONFIG__NUM_ACQ_MASK … #define TMON0_CONFIG__NUM_ACQ__SHIFT … #define TMON0_CONFIG__FORCE_MAX_ACQ_MASK … #define TMON0_CONFIG__FORCE_MAX_ACQ__SHIFT … #define TMON0_CONFIG__RDI_INTERLEAVE_MASK … #define TMON0_CONFIG__RDI_INTERLEAVE__SHIFT … #define TMON0_CONFIG__RE_CALIB_EN_MASK … #define TMON0_CONFIG__RE_CALIB_EN__SHIFT … #define TMON0_TEMP_CALC_COEFF0__Z_MASK … #define TMON0_TEMP_CALC_COEFF0__Z__SHIFT … #define TMON0_TEMP_CALC_COEFF1__A_MASK … #define TMON0_TEMP_CALC_COEFF1__A__SHIFT … #define TMON0_TEMP_CALC_COEFF2__B_MASK … #define TMON0_TEMP_CALC_COEFF2__B__SHIFT … #define TMON0_TEMP_CALC_COEFF3__C_MASK … #define TMON0_TEMP_CALC_COEFF3__C__SHIFT … #define TMON0_TEMP_CALC_COEFF4__K_MASK … #define TMON0_TEMP_CALC_COEFF4__K__SHIFT … #define TMON0_DEBUG0__DEBUG_Z_MASK … #define TMON0_DEBUG0__DEBUG_Z__SHIFT … #define TMON0_DEBUG0__DEBUG_Z_EN_MASK … #define TMON0_DEBUG0__DEBUG_Z_EN__SHIFT … #define TMON0_DEBUG1__DEBUG_RDI_MASK … #define TMON0_DEBUG1__DEBUG_RDI__SHIFT … #define TMON1_RDIL0_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL0_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL1_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL1_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL2_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL2_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL3_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL3_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL4_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL4_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL5_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL5_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL6_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL6_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL7_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL7_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL8_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL8_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL9_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL9_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL10_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL10_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL11_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL11_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL12_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL12_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL13_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL13_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL14_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL14_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL15_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIL15_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR0_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR0_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR1_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR1_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR2_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR2_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR3_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR3_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR4_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR4_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR5_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR5_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR6_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR6_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR7_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR7_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR8_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR8_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR9_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR9_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR10_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR10_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR11_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR11_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR12_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR12_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR13_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR13_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR14_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR14_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIR15_DATA__TEMP_Z_DATA_MASK … #define TMON1_RDIR15_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_INT_DATA__TEMP_Z_DATA_MASK … #define TMON1_INT_DATA__TEMP_Z_DATA__SHIFT … #define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK … #define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT … #define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK … #define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT … #define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK … #define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT … #define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK … #define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT … #define TMON1_CONFIG__NUM_ACQ_MASK … #define TMON1_CONFIG__NUM_ACQ__SHIFT … #define TMON1_CONFIG__FORCE_MAX_ACQ_MASK … #define TMON1_CONFIG__FORCE_MAX_ACQ__SHIFT … #define TMON1_CONFIG__RDI_INTERLEAVE_MASK … #define TMON1_CONFIG__RDI_INTERLEAVE__SHIFT … #define TMON1_CONFIG__RE_CALIB_EN_MASK … #define TMON1_CONFIG__RE_CALIB_EN__SHIFT … #define TMON1_TEMP_CALC_COEFF0__Z_MASK … #define TMON1_TEMP_CALC_COEFF0__Z__SHIFT … #define TMON1_TEMP_CALC_COEFF1__A_MASK … #define TMON1_TEMP_CALC_COEFF1__A__SHIFT … #define TMON1_TEMP_CALC_COEFF2__B_MASK … #define TMON1_TEMP_CALC_COEFF2__B__SHIFT … #define TMON1_TEMP_CALC_COEFF3__C_MASK … #define TMON1_TEMP_CALC_COEFF3__C__SHIFT … #define TMON1_TEMP_CALC_COEFF4__K_MASK … #define TMON1_TEMP_CALC_COEFF4__K__SHIFT … #define TMON1_DEBUG0__DEBUG_Z_MASK … #define TMON1_DEBUG0__DEBUG_Z__SHIFT … #define TMON1_DEBUG0__DEBUG_Z_EN_MASK … #define TMON1_DEBUG0__DEBUG_Z_EN__SHIFT … #define TMON1_DEBUG1__DEBUG_RDI_MASK … #define TMON1_DEBUG1__DEBUG_RDI__SHIFT … #define THM_TMON0_REMOTE_START__DATA_MASK … #define THM_TMON0_REMOTE_START__DATA__SHIFT … #define THM_TMON0_REMOTE_END__DATA_MASK … #define THM_TMON0_REMOTE_END__DATA__SHIFT … #define THM_TMON1_REMOTE_START__DATA_MASK … #define THM_TMON1_REMOTE_START__DATA__SHIFT … #define THM_TMON1_REMOTE_END__DATA_MASK … #define THM_TMON1_REMOTE_END__DATA__SHIFT … #define THM_TCON_LOCAL0__HaltPolling_MASK … #define THM_TCON_LOCAL0__HaltPolling__SHIFT … #define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK … #define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT … #define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK … #define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT … #define THM_TCON_LOCAL1__PwrDn_Limit_Temp_MASK … #define THM_TCON_LOCAL1__PwrDn_Limit_Temp__SHIFT … #define THM_TCON_LOCAL1__PwrDn_DelaySlope_MASK … #define THM_TCON_LOCAL1__PwrDn_DelaySlope__SHIFT … #define THM_TCON_LOCAL1__PwrDn_MinDelay_MASK … #define THM_TCON_LOCAL1__PwrDn_MinDelay__SHIFT … #define THM_TCON_LOCAL2__PwrDn_MaxDlyMult_MASK … #define THM_TCON_LOCAL2__PwrDn_MaxDlyMult__SHIFT … #define THM_TCON_LOCAL2__PwrDn_NumSensors_MASK … #define THM_TCON_LOCAL2__PwrDn_NumSensors__SHIFT … #define THM_TCON_LOCAL2__start_mission_polling_MASK … #define THM_TCON_LOCAL2__start_mission_polling__SHIFT … #define THM_TCON_LOCAL2__short_stagger_count_MASK … #define THM_TCON_LOCAL2__short_stagger_count__SHIFT … #define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK … #define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT … #define THM_TCON_LOCAL2__csrslave_use_corrected_MASK … #define THM_TCON_LOCAL2__csrslave_use_corrected__SHIFT … #define THM_TCON_LOCAL2__smu_use_corrected_MASK … #define THM_TCON_LOCAL2__smu_use_corrected__SHIFT … #define THM_TCON_LOCAL2__skip_scale_correction_MASK … #define THM_TCON_LOCAL2__skip_scale_correction__SHIFT … #define THM_TCON_LOCAL3__Global_TMAX_MASK … #define THM_TCON_LOCAL3__Global_TMAX__SHIFT … #define THM_TCON_LOCAL4__Global_TMAX_ID_MASK … #define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT … #define THM_TCON_LOCAL5__Global_TMIN_MASK … #define THM_TCON_LOCAL5__Global_TMIN__SHIFT … #define THM_TCON_LOCAL6__Global_TMIN_ID_MASK … #define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT … #define THM_TCON_LOCAL7__THERMID_MASK … #define THM_TCON_LOCAL7__THERMID__SHIFT … #define THM_TCON_LOCAL8__THERMMAX_MASK … #define THM_TCON_LOCAL8__THERMMAX__SHIFT … #define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK … #define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT … #define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK … #define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT … #define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK … #define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT … #define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK … #define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT … #define THM_TCON_LOCAL13__PowerDownTmon0_MASK … #define THM_TCON_LOCAL13__PowerDownTmon0__SHIFT … #define THM_TCON_LOCAL13__PowerDownTmon1_MASK … #define THM_TCON_LOCAL13__PowerDownTmon1__SHIFT … #define THM_TCON_LOCAL14__boot_done_MASK … #define THM_TCON_LOCAL14__boot_done__SHIFT … #define THM_FUSE0__FUSE_TmonRsInterleave_MASK … #define THM_FUSE0__FUSE_TmonRsInterleave__SHIFT … #define THM_FUSE0__FUSE_TmonNumAcq_MASK … #define THM_FUSE0__FUSE_TmonNumAcq__SHIFT … #define THM_FUSE0__FUSE_TmonForceMaxAcq_MASK … #define THM_FUSE0__FUSE_TmonForceMaxAcq__SHIFT … #define THM_FUSE0__FUSE_TmonClkDiv_MASK … #define THM_FUSE0__FUSE_TmonClkDiv__SHIFT … #define THM_FUSE0__FUSE_TmonBGAdj1_MASK … #define THM_FUSE0__FUSE_TmonBGAdj1__SHIFT … #define THM_FUSE0__FUSE_TmonBGAdj0_MASK … #define THM_FUSE0__FUSE_TmonBGAdj0__SHIFT … #define THM_FUSE0__FUSE_TconZtValue_MASK … #define THM_FUSE0__FUSE_TconZtValue__SHIFT … #define THM_FUSE1__FUSE_TconZtValue_MASK … #define THM_FUSE1__FUSE_TconZtValue__SHIFT … #define THM_FUSE1__FUSE_TconUseSecondary_MASK … #define THM_FUSE1__FUSE_TconUseSecondary__SHIFT … #define THM_FUSE1__FUSE_TconTmpAdjLoRes_MASK … #define THM_FUSE1__FUSE_TconTmpAdjLoRes__SHIFT … #define THM_FUSE1__FUSE_TconPwrUpStaggerTime_MASK … #define THM_FUSE1__FUSE_TconPwrUpStaggerTime__SHIFT … #define THM_FUSE1__FUSE_TconPwrDnTmpLmt_MASK … #define THM_FUSE1__FUSE_TconPwrDnTmpLmt__SHIFT … #define THM_FUSE1__FUSE_TconPwrDnNumSensors_MASK … #define THM_FUSE1__FUSE_TconPwrDnNumSensors__SHIFT … #define THM_FUSE1__FUSE_TconPwrDnMinDelay_MASK … #define THM_FUSE1__FUSE_TconPwrDnMinDelay__SHIFT … #define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult_MASK … #define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult__SHIFT … #define THM_FUSE1__FUSE_TconPwrDnDelaySlope_MASK … #define THM_FUSE1__FUSE_TconPwrDnDelaySlope__SHIFT … #define THM_FUSE1__FUSE_TconKValue_MASK … #define THM_FUSE1__FUSE_TconKValue__SHIFT … #define THM_FUSE1__FUSE_TconDtValue31_MASK … #define THM_FUSE1__FUSE_TconDtValue31__SHIFT … #define THM_FUSE1__FUSE_TconDtValue30_MASK … #define THM_FUSE1__FUSE_TconDtValue30__SHIFT … #define THM_FUSE2__FUSE_TconDtValue30_MASK … #define THM_FUSE2__FUSE_TconDtValue30__SHIFT … #define THM_FUSE2__FUSE_TconDtValue29_MASK … #define THM_FUSE2__FUSE_TconDtValue29__SHIFT … #define THM_FUSE2__FUSE_TconDtValue28_MASK … #define THM_FUSE2__FUSE_TconDtValue28__SHIFT … #define THM_FUSE2__FUSE_TconDtValue27_MASK … #define THM_FUSE2__FUSE_TconDtValue27__SHIFT … #define THM_FUSE2__FUSE_TconDtValue26_MASK … #define THM_FUSE2__FUSE_TconDtValue26__SHIFT … #define THM_FUSE2__FUSE_TconDtValue25_MASK … #define THM_FUSE2__FUSE_TconDtValue25__SHIFT … #define THM_FUSE2__FUSE_TconDtValue24_MASK … #define THM_FUSE2__FUSE_TconDtValue24__SHIFT … #define THM_FUSE3__FUSE_TconDtValue24_MASK … #define THM_FUSE3__FUSE_TconDtValue24__SHIFT … #define THM_FUSE3__FUSE_TconDtValue23_MASK … #define THM_FUSE3__FUSE_TconDtValue23__SHIFT … #define THM_FUSE3__FUSE_TconDtValue22_MASK … #define THM_FUSE3__FUSE_TconDtValue22__SHIFT … #define THM_FUSE3__FUSE_TconDtValue21_MASK … #define THM_FUSE3__FUSE_TconDtValue21__SHIFT … #define THM_FUSE3__FUSE_TconDtValue20_MASK … #define THM_FUSE3__FUSE_TconDtValue20__SHIFT … #define THM_FUSE3__FUSE_TconDtValue19_MASK … #define THM_FUSE3__FUSE_TconDtValue19__SHIFT … #define THM_FUSE4__FUSE_TconDtValue19_MASK … #define THM_FUSE4__FUSE_TconDtValue19__SHIFT … #define THM_FUSE4__FUSE_TconDtValue18_MASK … #define THM_FUSE4__FUSE_TconDtValue18__SHIFT … #define THM_FUSE4__FUSE_TconDtValue17_MASK … #define THM_FUSE4__FUSE_TconDtValue17__SHIFT … #define THM_FUSE4__FUSE_TconDtValue16_MASK … #define THM_FUSE4__FUSE_TconDtValue16__SHIFT … #define THM_FUSE4__FUSE_TconDtValue15_MASK … #define THM_FUSE4__FUSE_TconDtValue15__SHIFT … #define THM_FUSE4__FUSE_TconDtValue14_MASK … #define THM_FUSE4__FUSE_TconDtValue14__SHIFT … #define THM_FUSE5__FUSE_TconDtValue14_MASK … #define THM_FUSE5__FUSE_TconDtValue14__SHIFT … #define THM_FUSE5__FUSE_TconDtValue13_MASK … #define THM_FUSE5__FUSE_TconDtValue13__SHIFT … #define THM_FUSE5__FUSE_TconDtValue12_MASK … #define THM_FUSE5__FUSE_TconDtValue12__SHIFT … #define THM_FUSE5__FUSE_TconDtValue11_MASK … #define THM_FUSE5__FUSE_TconDtValue11__SHIFT … #define THM_FUSE5__FUSE_TconDtValue10_MASK … #define THM_FUSE5__FUSE_TconDtValue10__SHIFT … #define THM_FUSE5__FUSE_TconDtValue9_MASK … #define THM_FUSE5__FUSE_TconDtValue9__SHIFT … #define THM_FUSE5__FUSE_TconDtValue8_MASK … #define THM_FUSE5__FUSE_TconDtValue8__SHIFT … #define THM_FUSE6__FUSE_TconDtValue8_MASK … #define THM_FUSE6__FUSE_TconDtValue8__SHIFT … #define THM_FUSE6__FUSE_TconDtValue7_MASK … #define THM_FUSE6__FUSE_TconDtValue7__SHIFT … #define THM_FUSE6__FUSE_TconDtValue6_MASK … #define THM_FUSE6__FUSE_TconDtValue6__SHIFT … #define THM_FUSE6__FUSE_TconDtValue5_MASK … #define THM_FUSE6__FUSE_TconDtValue5__SHIFT … #define THM_FUSE6__FUSE_TconDtValue4_MASK … #define THM_FUSE6__FUSE_TconDtValue4__SHIFT … #define THM_FUSE6__FUSE_TconDtValue3_MASK … #define THM_FUSE6__FUSE_TconDtValue3__SHIFT … #define THM_FUSE7__FUSE_TconDtValue3_MASK … #define THM_FUSE7__FUSE_TconDtValue3__SHIFT … #define THM_FUSE7__FUSE_TconDtValue2_MASK … #define THM_FUSE7__FUSE_TconDtValue2__SHIFT … #define THM_FUSE7__FUSE_TconDtValue1_MASK … #define THM_FUSE7__FUSE_TconDtValue1__SHIFT … #define THM_FUSE7__FUSE_TconDtValue0_MASK … #define THM_FUSE7__FUSE_TconDtValue0__SHIFT … #define THM_FUSE7__FUSE_TconCtValue1_MASK … #define THM_FUSE7__FUSE_TconCtValue1__SHIFT … #define THM_FUSE8__FUSE_TconCtValue0_MASK … #define THM_FUSE8__FUSE_TconCtValue0__SHIFT … #define THM_FUSE8__FUSE_TconBtValue_MASK … #define THM_FUSE8__FUSE_TconBtValue__SHIFT … #define THM_FUSE8__FUSE_TconBootDelay_MASK … #define THM_FUSE8__FUSE_TconBootDelay__SHIFT … #define THM_FUSE8__FUSE_TconAtValue1_MASK … #define THM_FUSE8__FUSE_TconAtValue1__SHIFT … #define THM_FUSE8__FUSE_TconAtValue0_MASK … #define THM_FUSE8__FUSE_TconAtValue0__SHIFT … #define THM_FUSE9__FUSE_TconAtValue0_MASK … #define THM_FUSE9__FUSE_TconAtValue0__SHIFT … #define THM_FUSE9__FUSE_ThermTripLimit_MASK … #define THM_FUSE9__FUSE_ThermTripLimit__SHIFT … #define THM_FUSE9__FUSE_ThermTripEn_MASK … #define THM_FUSE9__FUSE_ThermTripEn__SHIFT … #define THM_FUSE9__FUSE_HtcTmpLmt_MASK … #define THM_FUSE9__FUSE_HtcTmpLmt__SHIFT … #define THM_FUSE9__FUSE_HtcMsrLock_MASK … #define THM_FUSE9__FUSE_HtcMsrLock__SHIFT … #define THM_FUSE9__FUSE_HtcHystLmt_MASK … #define THM_FUSE9__FUSE_HtcHystLmt__SHIFT … #define THM_FUSE10__FUSE_HtcDis_MASK … #define THM_FUSE10__FUSE_HtcDis__SHIFT … #define THM_FUSE10__FUSE_HtcClkInact_MASK … #define THM_FUSE10__FUSE_HtcClkInact__SHIFT … #define THM_FUSE10__FUSE_HtcClkAct_MASK … #define THM_FUSE10__FUSE_HtcClkAct__SHIFT … #define THM_FUSE10__FUSE_UnusedBits_MASK … #define THM_FUSE10__FUSE_UnusedBits__SHIFT … #define THM_FUSE11__PA_SPARE_MASK … #define THM_FUSE11__PA_SPARE__SHIFT … #define THM_FUSE12__FusesValid_MASK … #define THM_FUSE12__FusesValid__SHIFT … #define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA__SHIFT … #define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR_MASK … #define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR__SHIFT … #define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA_MASK … #define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK … #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT … #define MP0_MSP_MESSAGE_0__MP0_MSP_MSG_MASK … #define MP0_MSP_MESSAGE_0__MP0_MSP_MSG__SHIFT … #define MP0_MSP_MESSAGE_1__MP0_MSP_MSG_MASK … #define MP0_MSP_MESSAGE_1__MP0_MSP_MSG__SHIFT … #define MP0_MSP_MESSAGE_2__MP0_MSP_MSG_MASK … #define MP0_MSP_MESSAGE_2__MP0_MSP_MSG__SHIFT … #define MP0_MSP_MESSAGE_3__MP0_MSP_MSG_MASK … #define MP0_MSP_MESSAGE_3__MP0_MSP_MSG__SHIFT … #define MP0_MSP_MESSAGE_4__MP0_MSP_MSG_MASK … #define MP0_MSP_MESSAGE_4__MP0_MSP_MSG__SHIFT … #define MP0_MSP_MESSAGE_5__MP0_MSP_MSG_MASK … #define MP0_MSP_MESSAGE_5__MP0_MSP_MSG__SHIFT … #define MP0_MSP_MESSAGE_6__MP0_MSP_MSG_MASK … #define MP0_MSP_MESSAGE_6__MP0_MSP_MSG__SHIFT … #define MP0_MSP_MESSAGE_7__MP0_MSP_MSG_MASK … #define MP0_MSP_MESSAGE_7__MP0_MSP_MSG__SHIFT … #define SAM_IH_EXT_ERR_INTR__UVD_MASK … #define SAM_IH_EXT_ERR_INTR__UVD__SHIFT … #define SAM_IH_EXT_ERR_INTR__VCE_MASK … #define SAM_IH_EXT_ERR_INTR__VCE__SHIFT … #define SAM_IH_EXT_ERR_INTR__ISP_MASK … #define SAM_IH_EXT_ERR_INTR__ISP__SHIFT … #define SAM_IH_EXT_ERR_INTR__RESERVED_MASK … #define SAM_IH_EXT_ERR_INTR__RESERVED__SHIFT … #define SAM_IH_EXT_ERR_INTR_STATUS__UVD_MASK … #define SAM_IH_EXT_ERR_INTR_STATUS__UVD__SHIFT … #define SAM_IH_EXT_ERR_INTR_STATUS__VCE_MASK … #define SAM_IH_EXT_ERR_INTR_STATUS__VCE__SHIFT … #define SAM_IH_EXT_ERR_INTR_STATUS__ISP_MASK … #define SAM_IH_EXT_ERR_INTR_STATUS__ISP__SHIFT … #define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED_MASK … #define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED__SHIFT … #define MP0_DISP_TIMER0_CTRL0__START_MASK … #define MP0_DISP_TIMER0_CTRL0__START__SHIFT … #define MP0_DISP_TIMER0_CTRL0__CLEAR_MASK … #define MP0_DISP_TIMER0_CTRL0__CLEAR__SHIFT … #define MP0_DISP_TIMER0_CTRL0__DEC_MASK … #define MP0_DISP_TIMER0_CTRL0__DEC__SHIFT … #define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE_MASK … #define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE__SHIFT … #define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN_MASK … #define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN__SHIFT … #define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN_MASK … #define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN__SHIFT … #define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN_MASK … #define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN__SHIFT … #define MP0_DISP_TIMER0_CTRL1__RESERVED_MASK … #define MP0_DISP_TIMER0_CTRL1__RESERVED__SHIFT … #define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC_MASK … #define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC__SHIFT … #define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED_MASK … #define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED__SHIFT … #define MP0_DISP_TIMER0_INTEN__INTEN_MASK … #define MP0_DISP_TIMER0_INTEN__INTEN__SHIFT … #define MP0_DISP_TIMER0_INTEN__RESERVED_MASK … #define MP0_DISP_TIMER0_INTEN__RESERVED__SHIFT … #define MP0_DISP_TIMER0_OCMP_0_0__OCMP_MASK … #define MP0_DISP_TIMER0_OCMP_0_0__OCMP__SHIFT … #define MP0_DISP_TIMER0_OCMP_0_1__OCMP_MASK … #define MP0_DISP_TIMER0_OCMP_0_1__OCMP__SHIFT … #define MP0_DISP_TIMER0_CNT__COUNT_MASK … #define MP0_DISP_TIMER0_CNT__COUNT__SHIFT … #define MP0_DISP_TIMER1_CTRL0__START_MASK … #define MP0_DISP_TIMER1_CTRL0__START__SHIFT … #define MP0_DISP_TIMER1_CTRL0__CLEAR_MASK … #define MP0_DISP_TIMER1_CTRL0__CLEAR__SHIFT … #define MP0_DISP_TIMER1_CTRL0__DEC_MASK … #define MP0_DISP_TIMER1_CTRL0__DEC__SHIFT … #define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE_MASK … #define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE__SHIFT … #define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN_MASK … #define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN__SHIFT … #define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN_MASK … #define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN__SHIFT … #define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN_MASK … #define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN__SHIFT … #define MP0_DISP_TIMER1_CTRL1__RESERVED_MASK … #define MP0_DISP_TIMER1_CTRL1__RESERVED__SHIFT … #define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC_MASK … #define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC__SHIFT … #define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED_MASK … #define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED__SHIFT … #define MP0_DISP_TIMER1_INTEN__INTEN_MASK … #define MP0_DISP_TIMER1_INTEN__INTEN__SHIFT … #define MP0_DISP_TIMER1_INTEN__RESERVED_MASK … #define MP0_DISP_TIMER1_INTEN__RESERVED__SHIFT … #define MP0_DISP_TIMER1_OCMP_0_0__OCMP_MASK … #define MP0_DISP_TIMER1_OCMP_0_0__OCMP__SHIFT … #define MP0_DISP_TIMER1_OCMP_0_1__OCMP_MASK … #define MP0_DISP_TIMER1_OCMP_0_1__OCMP__SHIFT … #define MP0_DISP_TIMER1_CNT__COUNT_MASK … #define MP0_DISP_TIMER1_CNT__COUNT__SHIFT … #define SMU_MP1_SRBM2P_MSG_0__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_0__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_1__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_1__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_2__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_2__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_3__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_3__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_4__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_4__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_5__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_5__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_6__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_6__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_7__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_7__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_8__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_8__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_9__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_9__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_10__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_10__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_11__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_11__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_12__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_12__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_13__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_13__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_14__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_14__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_MSG_15__CONTENT_MASK … #define SMU_MP1_SRBM2P_MSG_15__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_0__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_0__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_1__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_1__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_2__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_2__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_3__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_3__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_4__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_4__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_5__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_5__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_6__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_6__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_7__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_7__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_8__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_8__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_9__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_9__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_10__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_10__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_11__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_11__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_12__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_12__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_13__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_13__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_14__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_14__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_RESP_15__CONTENT_MASK … #define SMU_MP1_SRBM2P_RESP_15__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_0__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_0__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_1__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_1__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_2__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_2__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_3__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_3__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_4__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_4__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_5__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_5__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_6__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_6__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_7__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_7__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_8__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_8__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_9__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_9__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_10__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_10__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_11__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_11__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_12__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_12__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_13__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_13__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_14__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_14__CONTENT__SHIFT … #define SMU_MP1_SRBM2P_ARG_15__CONTENT_MASK … #define SMU_MP1_SRBM2P_ARG_15__CONTENT__SHIFT … #define SMU_MP1_ACP2MP_RESP__CONTENT_MASK … #define SMU_MP1_ACP2MP_RESP__CONTENT__SHIFT … #define SMU_MP1_DC2MP_RESP__CONTENT_MASK … #define SMU_MP1_DC2MP_RESP__CONTENT__SHIFT … #define SMU_MP1_UVD2MP_RESP__CONTENT_MASK … #define SMU_MP1_UVD2MP_RESP__CONTENT__SHIFT … #define SMU_MP1_VCE2MP_RESP__CONTENT_MASK … #define SMU_MP1_VCE2MP_RESP__CONTENT__SHIFT … #define SMU_MP1_RLC2MP_RESP__CONTENT_MASK … #define SMU_MP1_RLC2MP_RESP__CONTENT__SHIFT … #define MP_FPS_CNT__FPS_CNT_MASK … #define MP_FPS_CNT__FPS_CNT__SHIFT … #define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT_MASK … #define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT__SHIFT … #define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK_MASK … #define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK__SHIFT … #define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE_MASK … #define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE__SHIFT … #define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK_MASK … #define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK__SHIFT … #define SMU_DISP0_TIMER_INT_CONTROL__MASK_MASK … #define SMU_DISP0_TIMER_INT_CONTROL__MASK__SHIFT … #define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT_MASK … #define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT__SHIFT … #define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK_MASK … #define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK__SHIFT … #define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE_MASK … #define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE__SHIFT … #define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK_MASK … #define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK__SHIFT … #define SMU_DISP1_TIMER_INT_CONTROL__MASK_MASK … #define SMU_DISP1_TIMER_INT_CONTROL__MASK__SHIFT … #define SMU_SRBM_CONFIG__MSTR_CREDITS_MASK … #define SMU_SRBM_CONFIG__MSTR_CREDITS__SHIFT … #define MP_FPS_CNT_XBAR__FPS_CNT_MASK … #define MP_FPS_CNT_XBAR__FPS_CNT__SHIFT … #define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS_MASK … #define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS__SHIFT … #define MP_SRBM_CONTROL__ACC_VIO_EN_MASK … #define MP_SRBM_CONTROL__ACC_VIO_EN__SHIFT … #define MP_SRBM_CONTROL__ALLOW_NS_ACC_MASK … #define MP_SRBM_CONTROL__ALLOW_NS_ACC__SHIFT … #define MP_SRBM_CONTROL__SOFT_RST_MASK_MASK … #define MP_SRBM_CONTROL__SOFT_RST_MASK__SHIFT … #define MP_SRBM_CONTROL__SOFT_RST_STS_MASK … #define MP_SRBM_CONTROL__SOFT_RST_STS__SHIFT … #define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP_MASK … #define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT … #define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID_MASK … #define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID__SHIFT … #define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID_MASK … #define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT … #define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK … #define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT … #define MP_CRBBM_CONTROL__ACC_VIO_EN_MASK … #define MP_CRBBM_CONTROL__ACC_VIO_EN__SHIFT … #define MP_CRBBM_CONTROL__MP0_ACCESS_MASK … #define MP_CRBBM_CONTROL__MP0_ACCESS__SHIFT … #define MP_CRBBM_CONTROL__ALLOW_NS_ACC_MASK … #define MP_CRBBM_CONTROL__ALLOW_NS_ACC__SHIFT … #define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP_MASK … #define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT … #define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF_MASK … #define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF__SHIFT … #define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID_MASK … #define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT … #define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK … #define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL__tag_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL__tag__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL__urg_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL__urg__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL__stall_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL__stall__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL__priv_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL__priv__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL__cid_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL__cid__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL_1__vf_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL_1__vf__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL_1__physical_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL_1__physical__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL_1__inval_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL_1__inval__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL_1__op_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL_1__op__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL_1__swap_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL_1__swap__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL_1__atc_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL_1__atc__SHIFT … #define MP_DRAM_CNTL_WRREQ_CNTL_1__fed_MASK … #define MP_DRAM_CNTL_WRREQ_CNTL_1__fed__SHIFT … #define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr_MASK … #define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr__SHIFT … #define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37_MASK … #define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37__SHIFT … #define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved_MASK … #define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved__SHIFT … #define MP_DRAM_CNTL_WRREQ_MASK__mask_MASK … #define MP_DRAM_CNTL_WRREQ_MASK__mask__SHIFT … #define MP_DRAM_CNTL_WRREQ_DATA_0__data_MASK … #define MP_DRAM_CNTL_WRREQ_DATA_0__data__SHIFT … #define MP_DRAM_CNTL_WRREQ_DATA_1__data_MASK … #define MP_DRAM_CNTL_WRREQ_DATA_1__data__SHIFT … #define MP_DRAM_CNTL_WRREQ_DATA_2__data_MASK … #define MP_DRAM_CNTL_WRREQ_DATA_2__data__SHIFT … #define MP_DRAM_CNTL_WRREQ_DATA_3__data_MASK … #define MP_DRAM_CNTL_WRREQ_DATA_3__data__SHIFT … #define MP_DRAM_CNTL_WRREQ_DATA_4__data_MASK … #define MP_DRAM_CNTL_WRREQ_DATA_4__data__SHIFT … #define MP_DRAM_CNTL_WRREQ_DATA_5__data_MASK … #define MP_DRAM_CNTL_WRREQ_DATA_5__data__SHIFT … #define MP_DRAM_CNTL_WRREQ_DATA_6__data_MASK … #define MP_DRAM_CNTL_WRREQ_DATA_6__data__SHIFT … #define MP_DRAM_CNTL_WRREQ_DATA_7__data_MASK … #define MP_DRAM_CNTL_WRREQ_DATA_7__data__SHIFT … #define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter_MASK … #define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter__SHIFT … #define MP_DRAM_CNTL_WRREQ_STATUS__reserved0_MASK … #define MP_DRAM_CNTL_WRREQ_STATUS__reserved0__SHIFT … #define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty_MASK … #define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty__SHIFT … #define MP_DRAM_CNTL_WRREQ_STATUS__reserved1_MASK … #define MP_DRAM_CNTL_WRREQ_STATUS__reserved1__SHIFT … #define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer_MASK … #define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer__SHIFT … #define MP_DRAM_CNTL_WRREQ_STATUS__reserved2_MASK … #define MP_DRAM_CNTL_WRREQ_STATUS__reserved2__SHIFT … #define MP_DRAM_CNTL_WRRET_STATUS_0__valid_MASK … #define MP_DRAM_CNTL_WRRET_STATUS_0__valid__SHIFT … #define MP_DRAM_CNTL_WRRET_STATUS_0__nack_MASK … #define MP_DRAM_CNTL_WRRET_STATUS_0__nack__SHIFT … #define MP_DRAM_CNTL_WRRET_STATUS_0__reserved_MASK … #define MP_DRAM_CNTL_WRRET_STATUS_0__reserved__SHIFT … #define MP_DRAM_CNTL_WRRET_STATUS_0__tag_MASK … #define MP_DRAM_CNTL_WRRET_STATUS_0__tag__SHIFT … #define MP_DRAM_CNTL_RDREQ_ADDR__addr_MASK … #define MP_DRAM_CNTL_RDREQ_ADDR__addr__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL__tag_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL__tag__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL__mask_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL__mask__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__urg_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__urg__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__stall_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__stall__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__priv_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__priv__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__swap_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__swap__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__cid_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__cid__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__atc_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__atc__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__physical_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__physical__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__exe_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__exe__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__shared_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__shared__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__vf_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__vf__SHIFT … #define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid_MASK … #define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid__SHIFT … #define
Codebase Browser
linux