linux/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h

/*
 * Copyright (C) 2017  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef _thm_10_0_OFFSET_HEADER
#define _thm_10_0_OFFSET_HEADER



// addressBlock: thm_thm_SmuThmDec
// base address: 0x59800
#define mmTHM_TCON_CUR_TMP
#define mmTHM_TCON_CUR_TMP_BASE_IDX
#define mmTHM_TCON_HTC
#define mmTHM_TCON_HTC_BASE_IDX
#define mmTHM_TCON_THERM_TRIP
#define mmTHM_TCON_THERM_TRIP_BASE_IDX
#define mmTHM_CTF_DELAY
#define mmTHM_CTF_DELAY_BASE_IDX
#define mmTHM_GPIO_PROCHOT_CTRL
#define mmTHM_GPIO_PROCHOT_CTRL_BASE_IDX
#define mmTHM_THERMAL_INT_ENA
#define mmTHM_THERMAL_INT_ENA_BASE_IDX
#define mmTHM_THERMAL_INT_CTRL
#define mmTHM_THERMAL_INT_CTRL_BASE_IDX
#define mmTHM_THERMAL_INT_STATUS
#define mmTHM_THERMAL_INT_STATUS_BASE_IDX
#define mmTHM_TMON0_RDIL0_DATA
#define mmTHM_TMON0_RDIL0_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL1_DATA
#define mmTHM_TMON0_RDIL1_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL2_DATA
#define mmTHM_TMON0_RDIL2_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL3_DATA
#define mmTHM_TMON0_RDIL3_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL4_DATA
#define mmTHM_TMON0_RDIL4_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL5_DATA
#define mmTHM_TMON0_RDIL5_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL6_DATA
#define mmTHM_TMON0_RDIL6_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL7_DATA
#define mmTHM_TMON0_RDIL7_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL8_DATA
#define mmTHM_TMON0_RDIL8_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL9_DATA
#define mmTHM_TMON0_RDIL9_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL10_DATA
#define mmTHM_TMON0_RDIL10_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL11_DATA
#define mmTHM_TMON0_RDIL11_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL12_DATA
#define mmTHM_TMON0_RDIL12_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL13_DATA
#define mmTHM_TMON0_RDIL13_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL14_DATA
#define mmTHM_TMON0_RDIL14_DATA_BASE_IDX
#define mmTHM_TMON0_RDIL15_DATA
#define mmTHM_TMON0_RDIL15_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR0_DATA
#define mmTHM_TMON0_RDIR0_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR1_DATA
#define mmTHM_TMON0_RDIR1_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR2_DATA
#define mmTHM_TMON0_RDIR2_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR3_DATA
#define mmTHM_TMON0_RDIR3_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR4_DATA
#define mmTHM_TMON0_RDIR4_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR5_DATA
#define mmTHM_TMON0_RDIR5_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR6_DATA
#define mmTHM_TMON0_RDIR6_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR7_DATA
#define mmTHM_TMON0_RDIR7_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR8_DATA
#define mmTHM_TMON0_RDIR8_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR9_DATA
#define mmTHM_TMON0_RDIR9_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR10_DATA
#define mmTHM_TMON0_RDIR10_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR11_DATA
#define mmTHM_TMON0_RDIR11_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR12_DATA
#define mmTHM_TMON0_RDIR12_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR13_DATA
#define mmTHM_TMON0_RDIR13_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR14_DATA
#define mmTHM_TMON0_RDIR14_DATA_BASE_IDX
#define mmTHM_TMON0_RDIR15_DATA
#define mmTHM_TMON0_RDIR15_DATA_BASE_IDX
#define mmTHM_TMON0_INT_DATA
#define mmTHM_TMON0_INT_DATA_BASE_IDX
#define mmTHM_TMON0_CTRL
#define mmTHM_TMON0_CTRL_BASE_IDX
#define mmTHM_TMON0_CTRL2
#define mmTHM_TMON0_CTRL2_BASE_IDX
#define mmTHM_TMON0_DEBUG
#define mmTHM_TMON0_DEBUG_BASE_IDX
#define mmTHM_DIE1_TEMP
#define mmTHM_DIE1_TEMP_BASE_IDX
#define mmTHM_DIE2_TEMP
#define mmTHM_DIE2_TEMP_BASE_IDX
#define mmTHM_DIE3_TEMP
#define mmTHM_DIE3_TEMP_BASE_IDX
#define mmTHM_SW_TEMP
#define mmTHM_SW_TEMP_BASE_IDX
#define mmCG_MULT_THERMAL_CTRL
#define mmCG_MULT_THERMAL_CTRL_BASE_IDX
#define mmCG_MULT_THERMAL_STATUS
#define mmCG_MULT_THERMAL_STATUS_BASE_IDX
#define mmCG_THERMAL_RANGE
#define mmCG_THERMAL_RANGE_BASE_IDX
#define mmTHM_TMON_CONFIG
#define mmTHM_TMON_CONFIG_BASE_IDX
#define mmTHM_TMON_CONFIG2
#define mmTHM_TMON_CONFIG2_BASE_IDX
#define mmTHM_TMON0_COEFF
#define mmTHM_TMON0_COEFF_BASE_IDX
#define mmTHM_TCON_LOCAL0
#define mmTHM_TCON_LOCAL0_BASE_IDX
#define mmTHM_TCON_LOCAL1
#define mmTHM_TCON_LOCAL1_BASE_IDX
#define mmTHM_TCON_LOCAL2
#define mmTHM_TCON_LOCAL2_BASE_IDX
#define mmTHM_TCON_LOCAL3
#define mmTHM_TCON_LOCAL3_BASE_IDX
#define mmTHM_TCON_LOCAL4
#define mmTHM_TCON_LOCAL4_BASE_IDX
#define mmTHM_TCON_LOCAL5
#define mmTHM_TCON_LOCAL5_BASE_IDX
#define mmTHM_TCON_LOCAL6
#define mmTHM_TCON_LOCAL6_BASE_IDX
#define mmTHM_TCON_LOCAL7
#define mmTHM_TCON_LOCAL7_BASE_IDX
#define mmTHM_TCON_LOCAL8
#define mmTHM_TCON_LOCAL8_BASE_IDX
#define mmTHM_TCON_LOCAL9
#define mmTHM_TCON_LOCAL9_BASE_IDX
#define mmTHM_TCON_LOCAL10
#define mmTHM_TCON_LOCAL10_BASE_IDX
#define mmTHM_TCON_LOCAL11
#define mmTHM_TCON_LOCAL11_BASE_IDX
#define mmTHM_TCON_LOCAL12
#define mmTHM_TCON_LOCAL12_BASE_IDX
#define mmTHM_TCON_LOCAL13
#define mmTHM_TCON_LOCAL13_BASE_IDX
#define mmTHM_PWRMGT
#define mmTHM_PWRMGT_BASE_IDX
#define mmSMUSBI_SBIREGADDR
#define mmSMUSBI_SBIREGADDR_BASE_IDX
#define mmSMUSBI_SBIREGDATA
#define mmSMUSBI_SBIREGDATA_BASE_IDX
#define mmSMUSBI_ERRATA_STAT_REG
#define mmSMUSBI_ERRATA_STAT_REG_BASE_IDX
#define mmSMUSBI_SBICTRL
#define mmSMUSBI_SBICTRL_BASE_IDX
#define mmSMUSBI_CKNBIRESET
#define mmSMUSBI_CKNBIRESET_BASE_IDX
#define mmSMUSBI_TIMING
#define mmSMUSBI_TIMING_BASE_IDX
#define mmSMUSBI_HS_TIMING
#define mmSMUSBI_HS_TIMING_BASE_IDX
#define mmSBTSI_REMOTE_TEMP
#define mmSBTSI_REMOTE_TEMP_BASE_IDX
#define mmSBRMI_CONTROL
#define mmSBRMI_CONTROL_BASE_IDX
#define mmSBRMI_COMMAND
#define mmSBRMI_COMMAND_BASE_IDX
#define mmSBRMI_WRITE_DATA0
#define mmSBRMI_WRITE_DATA0_BASE_IDX
#define mmSBRMI_WRITE_DATA1
#define mmSBRMI_WRITE_DATA1_BASE_IDX
#define mmSBRMI_WRITE_DATA2
#define mmSBRMI_WRITE_DATA2_BASE_IDX
#define mmSBRMI_READ_DATA0
#define mmSBRMI_READ_DATA0_BASE_IDX
#define mmSBRMI_READ_DATA1
#define mmSBRMI_READ_DATA1_BASE_IDX
#define mmSBRMI_CORE_EN_NUMBER
#define mmSBRMI_CORE_EN_NUMBER_BASE_IDX
#define mmSBRMI_CORE_EN_STATUS0
#define mmSBRMI_CORE_EN_STATUS0_BASE_IDX
#define mmSBRMI_CORE_EN_STATUS1
#define mmSBRMI_CORE_EN_STATUS1_BASE_IDX
#define mmSBRMI_APIC_STATUS0
#define mmSBRMI_APIC_STATUS0_BASE_IDX
#define mmSBRMI_APIC_STATUS1
#define mmSBRMI_APIC_STATUS1_BASE_IDX
#define mmSBRMI_MCE_STATUS0
#define mmSBRMI_MCE_STATUS0_BASE_IDX
#define mmSBRMI_MCE_STATUS1
#define mmSBRMI_MCE_STATUS1_BASE_IDX
#define mmSMBUS_CNTL0
#define mmSMBUS_CNTL0_BASE_IDX
#define mmSMBUS_CNTL1
#define mmSMBUS_CNTL1_BASE_IDX
#define mmSMBUS_BLKWR_CMD_CTRL0
#define mmSMBUS_BLKWR_CMD_CTRL0_BASE_IDX
#define mmSMBUS_BLKWR_CMD_CTRL1
#define mmSMBUS_BLKWR_CMD_CTRL1_BASE_IDX
#define mmSMBUS_BLKRD_CMD_CTRL0
#define mmSMBUS_BLKRD_CMD_CTRL0_BASE_IDX
#define mmSMBUS_BLKRD_CMD_CTRL1
#define mmSMBUS_BLKRD_CMD_CTRL1_BASE_IDX
#define mmSMBUS_TIMING_CNTL0
#define mmSMBUS_TIMING_CNTL0_BASE_IDX
#define mmSMBUS_TIMING_CNTL1
#define mmSMBUS_TIMING_CNTL1_BASE_IDX
#define mmSMBUS_TIMING_CNTL2
#define mmSMBUS_TIMING_CNTL2_BASE_IDX
#define mmSMBUS_TRIGGER_CNTL
#define mmSMBUS_TRIGGER_CNTL_BASE_IDX
#define mmSMBUS_UDID_CNTL0
#define mmSMBUS_UDID_CNTL0_BASE_IDX
#define mmSMBUS_UDID_CNTL1
#define mmSMBUS_UDID_CNTL1_BASE_IDX
#define mmSMBUS_UDID_CNTL2
#define mmSMBUS_UDID_CNTL2_BASE_IDX
#define mmSMUSBI_SMBUS
#define mmSMUSBI_SMBUS_BASE_IDX
#define mmSMUSBI_ALERT
#define mmSMUSBI_ALERT_BASE_IDX
#define mmTHM_TMON0_REMOTE_START
#define mmTHM_TMON0_REMOTE_START_BASE_IDX
#define mmTHM_TMON0_REMOTE_END
#define mmTHM_TMON0_REMOTE_END_BASE_IDX
#define mmTHM_TMON1_REMOTE_START
#define mmTHM_TMON1_REMOTE_START_BASE_IDX
#define mmTHM_TMON1_REMOTE_END
#define mmTHM_TMON1_REMOTE_END_BASE_IDX
#define mmTHM_TMON2_REMOTE_START
#define mmTHM_TMON2_REMOTE_START_BASE_IDX
#define mmTHM_TMON2_REMOTE_END
#define mmTHM_TMON2_REMOTE_END_BASE_IDX
#define mmTHM_TMON3_REMOTE_START
#define mmTHM_TMON3_REMOTE_START_BASE_IDX
#define mmTHM_TMON3_REMOTE_END
#define mmTHM_TMON3_REMOTE_END_BASE_IDX

#endif