/* SPDX-License-Identifier: GPL-2.0 * * SuperH Pin Function Controller Support * * Copyright (c) 2008 Magnus Damm */ #ifndef __SH_PFC_H #define __SH_PFC_H #include <linux/bug.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/spinlock.h> #include <linux/stringify.h> enum { … }; #define SH_PFC_PIN_NONE … #define SH_PFC_PIN_CFG_INPUT … #define SH_PFC_PIN_CFG_OUTPUT … #define SH_PFC_PIN_CFG_PULL_UP … #define SH_PFC_PIN_CFG_PULL_DOWN … #define SH_PFC_PIN_CFG_PULL_UP_DOWN … #define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK … #define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 … #define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 … #define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 … #define SH_PFC_PIN_CFG_DRIVE_STRENGTH … #define SH_PFC_PIN_CFG_NO_GPIO … struct sh_pfc_pin { … }; #define SH_PFC_PIN_GROUP_ALIAS(alias, _name) … #define SH_PFC_PIN_GROUP(name) … /* * Define a pin group referring to a subset of an array of pins. */ #define SH_PFC_PIN_GROUP_SUBSET(_name, data, first, n) … /* * Define a pin group for the data pins of a resizable bus. * An optional 'suffix' argument is accepted, to be used when the same group * can appear on a different set of pins. */ #define BUS_DATA_PIN_GROUP(base, n, ...) … struct sh_pfc_pin_group { … }; #define SH_PFC_FUNCTION(n) … struct sh_pfc_function { … }; struct pinmux_func { … }; struct pinmux_cfg_reg { … }; #define GROUP(...) … /* * Describe a config register consisting of several fields of the same width * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) * - f_width: Width of the fixed-width register fields (in bits) * - ids: For each register field (from left to right, i.e. MSB to LSB), * 2^f_width enum IDs must be specified, one for each possible * combination of the register field bit values, all wrapped using * the GROUP() macro. */ #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) … /* * Describe a config register consisting of several fields of different widths * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) * - f_widths: List of widths of the register fields (in bits), from left * to right (i.e. MSB to LSB), wrapped using the GROUP() macro. * Reserved fields are indicated by negating the field width. * - ids: For each non-reserved register field (from left to right, i.e. MSB * to LSB), 2^f_widths[i] enum IDs must be specified, one for each * possible combination of the register field bit values, all wrapped * using the GROUP() macro. */ #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) … struct pinmux_drive_reg_field { … }; struct pinmux_drive_reg { … }; #define PINMUX_DRIVE_REG(name, r) … struct pinmux_bias_reg { … }; #define PINMUX_BIAS_REG(name1, r1, name2, r2) … struct pinmux_ioctrl_reg { … }; struct pinmux_data_reg { … }; /* * Describe a data register * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) * - ids: For each register bit (from left to right, i.e. MSB to LSB), one * enum ID must be specified, all wrapped using the GROUP() macro. */ #define PINMUX_DATA_REG(name, r, r_width, ids) … struct pinmux_irq { … }; /* * Describe the mapping from GPIOs to a single IRQ * - ids...: List of GPIOs that are mapped to the same IRQ */ #define PINMUX_IRQ(ids...) … struct pinmux_range { … }; struct sh_pfc_window { … }; struct sh_pfc_pin_range; struct sh_pfc { … }; struct sh_pfc_soc_operations { … }; struct sh_pfc_soc_info { … }; extern const struct sh_pfc_soc_info emev2_pinmux_info; extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; extern const struct sh_pfc_soc_info r8a7742_pinmux_info; extern const struct sh_pfc_soc_info r8a7743_pinmux_info; extern const struct sh_pfc_soc_info r8a7744_pinmux_info; extern const struct sh_pfc_soc_info r8a7745_pinmux_info; extern const struct sh_pfc_soc_info r8a77470_pinmux_info; extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; extern const struct sh_pfc_soc_info r8a774b1_pinmux_info; extern const struct sh_pfc_soc_info r8a774c0_pinmux_info; extern const struct sh_pfc_soc_info r8a774e1_pinmux_info; extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7792_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info r8a7794_pinmux_info; extern const struct sh_pfc_soc_info r8a77951_pinmux_info; extern const struct sh_pfc_soc_info r8a77960_pinmux_info; extern const struct sh_pfc_soc_info r8a77961_pinmux_info; extern const struct sh_pfc_soc_info r8a77965_pinmux_info; extern const struct sh_pfc_soc_info r8a77970_pinmux_info; extern const struct sh_pfc_soc_info r8a77980_pinmux_info; extern const struct sh_pfc_soc_info r8a77990_pinmux_info; extern const struct sh_pfc_soc_info r8a77995_pinmux_info; extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; extern const struct sh_pfc_soc_info r8a779f0_pinmux_info; extern const struct sh_pfc_soc_info r8a779g0_pinmux_info; extern const struct sh_pfc_soc_info r8a779h0_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; extern const struct sh_pfc_soc_info sh73a0_pinmux_info; extern const struct sh_pfc_soc_info sh7720_pinmux_info; extern const struct sh_pfc_soc_info sh7722_pinmux_info; extern const struct sh_pfc_soc_info sh7723_pinmux_info; extern const struct sh_pfc_soc_info sh7724_pinmux_info; extern const struct sh_pfc_soc_info sh7734_pinmux_info; extern const struct sh_pfc_soc_info sh7757_pinmux_info; extern const struct sh_pfc_soc_info sh7785_pinmux_info; extern const struct sh_pfc_soc_info sh7786_pinmux_info; extern const struct sh_pfc_soc_info shx3_pinmux_info; /* ----------------------------------------------------------------------------- * Helper macros to create pin and port lists */ /* * sh_pfc_soc_info pinmux_data array macros */ /* * Describe generic pinmux data * - data_or_mark: *_DATA or *_MARK enum ID * - ids...: List of enum IDs to associate with data_or_mark */ #define PINMUX_DATA(data_or_mark, ids...) … /* * Describe a pinmux configuration without GPIO function that needs * configuration in a Peripheral Function Select Register (IPSR) * - ipsr: IPSR field (unused, for documentation purposes only) * - fn: Function name, referring to a field in the IPSR */ #define PINMUX_IPSR_NOGP(ipsr, fn) … /* * Describe a pinmux configuration with GPIO function that needs configuration * in both a Peripheral Function Select Register (IPSR) and in a * GPIO/Peripheral Function Select Register (GPSR) * - ipsr: IPSR field * - fn: Function name, also referring to the IPSR field */ #define PINMUX_IPSR_GPSR(ipsr, fn) … /* * Describe a pinmux configuration without GPIO function that needs * configuration in a Peripheral Function Select Register (IPSR), and where the * pinmux function has a representation in a Module Select Register (MOD_SEL). * - ipsr: IPSR field (unused, for documentation purposes only) * - fn: Function name, also referring to the IPSR field * - msel: Module selector */ #define PINMUX_IPSR_NOGM(ipsr, fn, msel) … /* * Describe a pinmux configuration with GPIO function where the pinmux function * has no representation in a Peripheral Function Select Register (IPSR), but * instead solely depends on a group selection. * - gpsr: GPSR field * - fn: Function name, also referring to the GPSR field * - gsel: Group selector */ #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) … /* * Describe a pinmux configuration with GPIO function that needs configuration * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral * Function Select Register (GPSR), and where the pinmux function has a * representation in a Module Select Register (MOD_SEL). * - ipsr: IPSR field * - fn: Function name, also referring to the IPSR field * - msel: Module selector */ #define PINMUX_IPSR_MSEL(ipsr, fn, msel) … /* * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with * an additional select register that controls physical multiplexing * with another pin. * - ipsr: IPSR field * - fn: Function name, also referring to the IPSR field * - psel: Physical multiplexing selector * - msel: Module selector */ #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) … /* * Describe a pinmux configuration in which a pin is physically multiplexed * with other pins. * - ipsr: IPSR field * - fn: Function name * - psel: Physical multiplexing selector */ #define PINMUX_IPSR_PHYS(ipsr, fn, psel) … /* * Describe a pinmux configuration for a single-function pin with GPIO * capability. * - fn: Function name */ #define PINMUX_SINGLE(fn) … /* * GP port style (32 ports banks) */ #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) … #define PORT_GP_1(bank, pin, fn, sfx) … #define PORT_GP_CFG_2(bank, fn, sfx, cfg) … #define PORT_GP_2(bank, fn, sfx) … #define PORT_GP_CFG_4(bank, fn, sfx, cfg) … #define PORT_GP_4(bank, fn, sfx) … #define PORT_GP_CFG_6(bank, fn, sfx, cfg) … #define PORT_GP_6(bank, fn, sfx) … #define PORT_GP_CFG_7(bank, fn, sfx, cfg) … #define PORT_GP_7(bank, fn, sfx) … #define PORT_GP_CFG_8(bank, fn, sfx, cfg) … #define PORT_GP_8(bank, fn, sfx) … #define PORT_GP_CFG_9(bank, fn, sfx, cfg) … #define PORT_GP_9(bank, fn, sfx) … #define PORT_GP_CFG_10(bank, fn, sfx, cfg) … #define PORT_GP_10(bank, fn, sfx) … #define PORT_GP_CFG_11(bank, fn, sfx, cfg) … #define PORT_GP_11(bank, fn, sfx) … #define PORT_GP_CFG_12(bank, fn, sfx, cfg) … #define PORT_GP_12(bank, fn, sfx) … #define PORT_GP_CFG_13(bank, fn, sfx, cfg) … #define PORT_GP_13(bank, fn, sfx) … #define PORT_GP_CFG_14(bank, fn, sfx, cfg) … #define PORT_GP_14(bank, fn, sfx) … #define PORT_GP_CFG_15(bank, fn, sfx, cfg) … #define PORT_GP_15(bank, fn, sfx) … #define PORT_GP_CFG_16(bank, fn, sfx, cfg) … #define PORT_GP_16(bank, fn, sfx) … #define PORT_GP_CFG_17(bank, fn, sfx, cfg) … #define PORT_GP_17(bank, fn, sfx) … #define PORT_GP_CFG_18(bank, fn, sfx, cfg) … #define PORT_GP_18(bank, fn, sfx) … #define PORT_GP_CFG_19(bank, fn, sfx, cfg) … #define PORT_GP_19(bank, fn, sfx) … #define PORT_GP_CFG_20(bank, fn, sfx, cfg) … #define PORT_GP_20(bank, fn, sfx) … #define PORT_GP_CFG_21(bank, fn, sfx, cfg) … #define PORT_GP_21(bank, fn, sfx) … #define PORT_GP_CFG_22(bank, fn, sfx, cfg) … #define PORT_GP_22(bank, fn, sfx) … #define PORT_GP_CFG_23(bank, fn, sfx, cfg) … #define PORT_GP_23(bank, fn, sfx) … #define PORT_GP_CFG_24(bank, fn, sfx, cfg) … #define PORT_GP_24(bank, fn, sfx) … #define PORT_GP_CFG_25(bank, fn, sfx, cfg) … #define PORT_GP_25(bank, fn, sfx) … #define PORT_GP_CFG_26(bank, fn, sfx, cfg) … #define PORT_GP_26(bank, fn, sfx) … #define PORT_GP_CFG_27(bank, fn, sfx, cfg) … #define PORT_GP_27(bank, fn, sfx) … #define PORT_GP_CFG_28(bank, fn, sfx, cfg) … #define PORT_GP_28(bank, fn, sfx) … #define PORT_GP_CFG_29(bank, fn, sfx, cfg) … #define PORT_GP_29(bank, fn, sfx) … #define PORT_GP_CFG_30(bank, fn, sfx, cfg) … #define PORT_GP_30(bank, fn, sfx) … #define PORT_GP_CFG_31(bank, fn, sfx, cfg) … #define PORT_GP_31(bank, fn, sfx) … #define PORT_GP_CFG_32(bank, fn, sfx, cfg) … #define PORT_GP_32(bank, fn, sfx) … #define PORT_GP_32_REV(bank, fn, sfx) … /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ #define _GP_ALL(bank, pin, name, sfx, cfg) … #define GP_ALL(str) … /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ #define _GP_GPIO(bank, _pin, _name, sfx, cfg) … #define PINMUX_GPIO_GP_ALL() … /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ #define _GP_DATA(bank, pin, name, sfx, cfg) … #define PINMUX_DATA_GP_ALL() … /* * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin * * The largest GP pin index is obtained by taking the size of a union, * containing one array per GP pin, sized by the corresponding pin index. * As the fields in the CPU_ALL_GP() macro definition are separated by commas, * while the members of a union must be terminated by semicolons, the commas * are absorbed by wrapping them inside dummy attributes. */ #define _GP_ENTRY(bank, pin, name, sfx, cfg) … #define GP_ASSIGN_LAST() … /* * PORT style (linear pin space) */ #define PORT_1(pn, fn, pfx, sfx) … #define PORT_10(pn, fn, pfx, sfx) … #define PORT_90(pn, fn, pfx, sfx) … /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ #define _PORT_ALL(pn, pfx, sfx) … #define PORT_ALL(str) … /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ #define PINMUX_GPIO(_pin) … /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ #define SH_PFC_PIN_CFG(_pin, cfgs) … /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, * PORT_name_OUT, PORT_name_IN marks */ #define _PORT_DATA(pn, pfx, sfx) … #define PINMUX_DATA_ALL() … /* * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin * * The largest PORT pin index is obtained by taking the size of a union, * containing one array per PORT pin, sized by the corresponding pin index. * As the fields in the CPU_ALL_PORT() macro definition are separated by * commas, while the members of a union must be terminated by semicolons, the * commas are absorbed by wrapping them inside dummy attributes. */ #define _PORT_ENTRY(pn, pfx, sfx) … #define PORT_ASSIGN_LAST() … /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ #define PINMUX_GPIO_FN(gpio, base, data_or_mark) … #define GPIO_FN(str) … /* * Pins not associated with a GPIO port */ #define PIN_NOGP_CFG(pin, name, fn, cfg) … #define PIN_NOGP(pin, name, fn) … /* NOGP_ALL - Expand to a list of PIN_id */ #define _NOGP_ALL(pin, name, cfg) … #define NOGP_ALL() … /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */ #define _NOGP_PINMUX(_pin, _name, cfg) … #define PINMUX_NOGP_ALL() … /* * PORTnCR helper macro for SH-Mobile/R-Mobile */ #define PORTCR(nr, reg) … /* * GPIO number helper macro for R-Car */ #define RCAR_GP_PIN(bank, pin) … /* * Bias helpers */ const struct pinmux_bias_reg * rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, unsigned int *bit); unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); #endif /* __SH_PFC_H */
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