/* SPDX-License-Identifier: MIT */ #ifndef __NV04_FIFO_REGS_H__ #define __NV04_FIFO_REGS_H__ #define NV04_PFIFO_DELAY_0 … #define NV04_PFIFO_DMA_TIMESLICE … #define NV04_PFIFO_NEXT_CHANNEL … #define NV03_PFIFO_INTR_0 … #define NV03_PFIFO_INTR_EN_0 … #define NV_PFIFO_INTR_CACHE_ERROR … #define NV_PFIFO_INTR_RUNOUT … #define NV_PFIFO_INTR_RUNOUT_OVERFLOW … #define NV_PFIFO_INTR_DMA_PUSHER … #define NV_PFIFO_INTR_DMA_PT … #define NV_PFIFO_INTR_SEMAPHORE … #define NV_PFIFO_INTR_ACQUIRE_TIMEOUT … #define NV03_PFIFO_RAMHT … #define NV03_PFIFO_RAMFC … #define NV03_PFIFO_RAMRO … #define NV40_PFIFO_RAMFC … #define NV03_PFIFO_CACHES … #define NV04_PFIFO_MODE … #define NV04_PFIFO_DMA … #define NV04_PFIFO_SIZE … #define NV50_PFIFO_CTX_TABLE(c) … #define NV50_PFIFO_CTX_TABLE__SIZE … #define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED … #define NV50_PFIFO_CTX_TABLE_UNK30_BAD … #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 … #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 … #define NV03_PFIFO_CACHE0_PUSH0 … #define NV03_PFIFO_CACHE0_PULL0 … #define NV04_PFIFO_CACHE0_PULL0 … #define NV04_PFIFO_CACHE0_PULL1 … #define NV03_PFIFO_CACHE1_PUSH0 … #define NV03_PFIFO_CACHE1_PUSH1 … #define NV03_PFIFO_CACHE1_PUSH1_DMA … #define NV40_PFIFO_CACHE1_PUSH1_DMA … #define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK … #define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK … #define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK … #define NV03_PFIFO_CACHE1_PUT … #define NV04_PFIFO_CACHE1_DMA_PUSH … #define NV04_PFIFO_CACHE1_DMA_FETCH … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 … #define NV_PFIFO_CACHE1_ENDIAN … #define NV_PFIFO_CACHE1_LITTLE_ENDIAN … #define NV_PFIFO_CACHE1_BIG_ENDIAN … #define NV04_PFIFO_CACHE1_DMA_STATE … #define NV04_PFIFO_CACHE1_DMA_INSTANCE … #define NV04_PFIFO_CACHE1_DMA_CTL … #define NV04_PFIFO_CACHE1_DMA_PUT … #define NV04_PFIFO_CACHE1_DMA_GET … #define NV10_PFIFO_CACHE1_REF_CNT … #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE … #define NV03_PFIFO_CACHE1_PULL0 … #define NV04_PFIFO_CACHE1_PULL0 … #define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED … #define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY … #define NV03_PFIFO_CACHE1_PULL1 … #define NV04_PFIFO_CACHE1_PULL1 … #define NV04_PFIFO_CACHE1_HASH … #define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT … #define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP … #define NV10_PFIFO_CACHE1_ACQUIRE_VALUE … #define NV10_PFIFO_CACHE1_SEMAPHORE … #define NV03_PFIFO_CACHE1_GET … #define NV04_PFIFO_CACHE1_ENGINE … #define NV04_PFIFO_CACHE1_DMA_DCOUNT … #define NV40_PFIFO_GRCTX_INSTANCE … #define NV40_PFIFO_UNK32E4 … #define NV04_PFIFO_CACHE1_METHOD(i) … #define NV04_PFIFO_CACHE1_DATA(i) … #define NV40_PFIFO_CACHE1_METHOD(i) … #define NV40_PFIFO_CACHE1_DATA(i) … #endif
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