linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "gf100.h"
#include "ctxgf100.h"
#include "fuc/os.h"

#include <core/client.h>
#include <core/firmware.h>
#include <core/option.h>
#include <subdev/acr.h>
#include <subdev/fb.h>
#include <subdev/mc.h>
#include <subdev/pmu.h>
#include <subdev/therm.h>
#include <subdev/timer.h>
#include <engine/fifo.h>

#include <nvif/class.h>
#include <nvif/cl9097.h>
#include <nvif/if900d.h>
#include <nvif/unpack.h>

/*******************************************************************************
 * Zero Bandwidth Clear
 ******************************************************************************/

static void
gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
{ … }

static int
gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
		       const u32 ds[4], const u32 l2[4])
{ … }

static void
gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
{ … }

static int
gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
		       const u32 ds, const u32 l2)
{ … }

const struct gf100_gr_func_zbc
gf100_gr_zbc = …;

/*******************************************************************************
 * Graphics object classes
 ******************************************************************************/
#define gf100_gr_object(p) …

struct gf100_gr_object { … };

static int
gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
{ … }

static int
gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
{ … }

static int
gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{ … }

const struct nvkm_object_func
gf100_fermi = …;

static void
gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data)
{ … }

static bool
gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data)
{ … }

static const struct nvkm_object_func
gf100_gr_object_func = …;

static int
gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size,
		    struct nvkm_object **pobject)
{ … }

static int
gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass)
{ … }

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

static int
gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
		   int align, struct nvkm_gpuobj **pgpuobj)
{ … }

static void *
gf100_gr_chan_dtor(struct nvkm_object *object)
{ … }

static const struct nvkm_object_func
gf100_gr_chan = …;

static int
gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
		  const struct nvkm_oclass *oclass,
		  struct nvkm_object **pobject)
{ … }

/*******************************************************************************
 * PGRAPH register lists
 ******************************************************************************/

const struct gf100_gr_init
gf100_gr_init_main_0[] = …;

const struct gf100_gr_init
gf100_gr_init_fe_0[] = …;

const struct gf100_gr_init
gf100_gr_init_pri_0[] = …;

const struct gf100_gr_init
gf100_gr_init_rstr2d_0[] = …;

const struct gf100_gr_init
gf100_gr_init_pd_0[] = …;

const struct gf100_gr_init
gf100_gr_init_ds_0[] = …;

const struct gf100_gr_init
gf100_gr_init_scc_0[] = …;

const struct gf100_gr_init
gf100_gr_init_prop_0[] = …;

const struct gf100_gr_init
gf100_gr_init_gpc_unk_0[] = …;

const struct gf100_gr_init
gf100_gr_init_setup_0[] = …;

const struct gf100_gr_init
gf100_gr_init_crstr_0[] = …;

const struct gf100_gr_init
gf100_gr_init_setup_1[] = …;

const struct gf100_gr_init
gf100_gr_init_zcull_0[] = …;

const struct gf100_gr_init
gf100_gr_init_gpm_0[] = …;

const struct gf100_gr_init
gf100_gr_init_gpc_unk_1[] = …;

const struct gf100_gr_init
gf100_gr_init_gcc_0[] = …;

const struct gf100_gr_init
gf100_gr_init_tpccs_0[] = …;

const struct gf100_gr_init
gf100_gr_init_tex_0[] = …;

const struct gf100_gr_init
gf100_gr_init_pe_0[] = …;

const struct gf100_gr_init
gf100_gr_init_l1c_0[] = …;

const struct gf100_gr_init
gf100_gr_init_wwdx_0[] = …;

const struct gf100_gr_init
gf100_gr_init_tpccs_1[] = …;

const struct gf100_gr_init
gf100_gr_init_mpc_0[] = …;

static const struct gf100_gr_init
gf100_gr_init_sm_0[] = …;

const struct gf100_gr_init
gf100_gr_init_be_0[] = …;

const struct gf100_gr_init
gf100_gr_init_fe_1[] = …;

const struct gf100_gr_init
gf100_gr_init_pe_1[] = …;

static const struct gf100_gr_pack
gf100_gr_pack_mmio[] = …;

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

static u32
gf100_gr_ctxsw_inst(struct nvkm_gr *gr)
{ … }

static int
gf100_gr_fecs_ctrl_ctxsw(struct gf100_gr *gr, u32 mthd)
{ … }

static int
gf100_gr_fecs_start_ctxsw(struct nvkm_gr *base)
{ … }

static int
gf100_gr_fecs_stop_ctxsw(struct nvkm_gr *base)
{ … }

static int
gf100_gr_fecs_halt_pipeline(struct gf100_gr *gr)
{ … }

int
gf100_gr_fecs_wfi_golden_save(struct gf100_gr *gr, u32 inst)
{ … }

int
gf100_gr_fecs_bind_pointer(struct gf100_gr *gr, u32 inst)
{ … }

static int
gf100_gr_fecs_set_reglist_virtual_address(struct gf100_gr *gr, u64 addr)
{ … }

static int
gf100_gr_fecs_set_reglist_bind_instance(struct gf100_gr *gr, u32 inst)
{ … }

static int
gf100_gr_fecs_discover_reglist_image_size(struct gf100_gr *gr, u32 *psize)
{ … }

static int
gf100_gr_fecs_elpg_bind(struct gf100_gr *gr)
{ … }

static int
gf100_gr_fecs_discover_pm_image_size(struct gf100_gr *gr, u32 *psize)
{ … }

static int
gf100_gr_fecs_discover_zcull_image_size(struct gf100_gr *gr, u32 *psize)
{ … }

static int
gf100_gr_fecs_discover_image_size(struct gf100_gr *gr, u32 *psize)
{ … }

static void
gf100_gr_fecs_set_watchdog_timeout(struct gf100_gr *gr, u32 timeout)
{ … }

static bool
gf100_gr_chsw_load(struct nvkm_gr *base)
{ … }

int
gf100_gr_rops(struct gf100_gr *gr)
{ … }

void
gf100_gr_zbc_init(struct gf100_gr *gr)
{ … }

/*
 * Wait until GR goes idle. GR is considered idle if it is disabled by the
 * MC (0x200) register, or GR is not busy and a context switch is not in
 * progress.
 */
int
gf100_gr_wait_idle(struct gf100_gr *gr)
{ … }

void
gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{ … }

void
gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{ … }

void
gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{ … }

u64
gf100_gr_units(struct nvkm_gr *base)
{ … }

static const struct nvkm_bitfield gf100_dispatch_error[] = …;

static const struct nvkm_bitfield gf100_m2mf_error[] = …;

static const struct nvkm_bitfield gf100_unk6_error[] = …;

static const struct nvkm_bitfield gf100_ccache_error[] = …;

static const struct nvkm_bitfield gf100_macro_error[] = …;

static const struct nvkm_bitfield gk104_sked_error[] = …;

static const struct nvkm_bitfield gf100_gpc_rop_error[] = …;

static void
gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
{ … }

const struct nvkm_enum gf100_mp_warp_error[] = …;

const struct nvkm_bitfield gf100_mp_global_error[] = …;

void
gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
{ … }

static void
gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
{ … }

static void
gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
{ … }

static void
gf100_gr_trap_intr(struct gf100_gr *gr)
{ … }

static void
gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
{ … }

void
gf100_gr_ctxctl_debug(struct gf100_gr *gr)
{ … }

static void
gf100_gr_ctxctl_isr(struct gf100_gr *gr)
{ … }

static irqreturn_t
gf100_gr_intr(struct nvkm_inth *inth)
{ … }

static void
gf100_gr_init_fw(struct nvkm_falcon *falcon,
		 struct nvkm_blob *code, struct nvkm_blob *data)
{ … }

static void
gf100_gr_init_csdata(struct gf100_gr *gr,
		     const struct gf100_gr_pack *pack,
		     u32 falcon, u32 starstar, u32 base)
{ … }

/* Initialize context from an external (secure or not) firmware */
static int
gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
{ … }

static int
gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
{ … }

int
gf100_gr_init_ctxctl(struct gf100_gr *gr)
{ … }

int
gf100_gr_oneinit_sm_id(struct gf100_gr *gr)
{ … }

void
gf100_gr_oneinit_tiles(struct gf100_gr *gr)
{ … }

static int
gf100_gr_oneinit(struct nvkm_gr *base)
{ … }

static int
gf100_gr_init_(struct nvkm_gr *base)
{ … }

static int
gf100_gr_fini(struct nvkm_gr *base, bool suspend)
{ … }

static void *
gf100_gr_dtor(struct nvkm_gr *base)
{ … }

static const struct nvkm_falcon_func
gf100_gr_flcn = …;

void
gf100_gr_init_num_tpc_per_gpc(struct gf100_gr *gr, bool pd, bool ds)
{ … }

void
gf100_gr_init_400054(struct gf100_gr *gr)
{ … }

void
gf100_gr_init_exception2(struct gf100_gr *gr)
{ … }

void
gf100_gr_init_rop_exceptions(struct gf100_gr *gr)
{ … }

void
gf100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
{ … }

void
gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int gpc, int tpc)
{ … }

void
gf100_gr_init_419eb4(struct gf100_gr *gr)
{ … }

void
gf100_gr_init_419cc0(struct gf100_gr *gr)
{ … }

void
gf100_gr_init_40601c(struct gf100_gr *gr)
{ … }

void
gf100_gr_init_fecs_exceptions(struct gf100_gr *gr)
{ … }

void
gf100_gr_init_gpc_mmu(struct gf100_gr *gr)
{ … }

void
gf100_gr_init_num_active_ltcs(struct gf100_gr *gr)
{ … }

void
gf100_gr_init_zcull(struct gf100_gr *gr)
{ … }

void
gf100_gr_init_vsc_stream_master(struct gf100_gr *gr)
{ … }

static int
gf100_gr_reset(struct nvkm_gr *base)
{ … }

int
gf100_gr_init(struct gf100_gr *gr)
{ … }

void
gf100_gr_fecs_reset(struct gf100_gr *gr)
{ … }

#include "fuc/hubgf100.fuc3.h"

struct gf100_gr_ucode
gf100_gr_fecs_ucode = …;

#include "fuc/gpcgf100.fuc3.h"

struct gf100_gr_ucode
gf100_gr_gpccs_ucode = …;

static int
gf100_gr_nonstall(struct nvkm_gr *base)
{ … }

static const struct nvkm_gr_func
gf100_gr_ = …;

static const struct gf100_gr_func
gf100_gr = …;

int
gf100_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
{ … }

static int
gf100_gr_load_fw(struct gf100_gr *gr, const char *name,
		 struct nvkm_blob *blob)
{ … }

int
gf100_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
{ … }

static const struct gf100_gr_fwif
gf100_gr_fwif[] = …;

int
gf100_gr_new_(const struct gf100_gr_fwif *fwif, struct nvkm_device *device,
	      enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{ … }

int
gf100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{ … }