/* * Copyright 2008 Stuart Bennett * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef __NOUVEAU_HW_H__ #define __NOUVEAU_HW_H__ #include "disp.h" #include "nvreg.h" #include <subdev/bios/pll.h> #define MASK(field) … #define XLATE(src, srclowbit, outfield) … void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value); uint8_t NVReadVgaSeq(struct drm_device *, int head, uint8_t index); void NVWriteVgaGr(struct drm_device *, int head, uint8_t index, uint8_t value); uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index); void NVSetOwner(struct drm_device *, int owner); void NVBlankScreen(struct drm_device *, int head, bool blank); int nouveau_hw_get_pllvals(struct drm_device *, enum nvbios_pll_type plltype, struct nvkm_pll_vals *pllvals); int nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pllvals); int nouveau_hw_get_clock(struct drm_device *, enum nvbios_pll_type plltype); void nouveau_hw_save_vga_fonts(struct drm_device *, bool save); void nouveau_hw_save_state(struct drm_device *, int head, struct nv04_mode_state *state); void nouveau_hw_load_state(struct drm_device *, int head, struct nv04_mode_state *state); void nouveau_hw_load_state_palette(struct drm_device *, int head, struct nv04_mode_state *state); /* nouveau_calc.c */ extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp, int *burst, int *lwm); static inline uint32_t NVReadCRTC(struct drm_device *dev, int head, uint32_t reg) { … } static inline void NVWriteCRTC(struct drm_device *dev, int head, uint32_t reg, uint32_t val) { … } static inline uint32_t NVReadRAMDAC(struct drm_device *dev, int head, uint32_t reg) { … } static inline void NVWriteRAMDAC(struct drm_device *dev, int head, uint32_t reg, uint32_t val) { … } static inline uint8_t nv_read_tmds(struct drm_device *dev, int or, int dl, uint8_t address) { … } static inline void nv_write_tmds(struct drm_device *dev, int or, int dl, uint8_t address, uint8_t data) { … } static inline void NVWriteVgaCrtc(struct drm_device *dev, int head, uint8_t index, uint8_t value) { … } static inline uint8_t NVReadVgaCrtc(struct drm_device *dev, int head, uint8_t index) { … } /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58 * I suspect they in fact do nothing, but are merely a way to carry useful * per-head variables around * * Known uses: * CR57 CR58 * 0x00 index to the appropriate dcb entry (or 7f for inactive) * 0x02 dcb entry's "or" value (or 00 for inactive) * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too) * 0x08 or 0x09 pxclk in MHz * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT_0 strap * high nibble for xlat strap value */ static inline void NVWriteVgaCrtc5758(struct drm_device *dev, int head, uint8_t index, uint8_t value) { … } static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_t index) { … } static inline uint8_t NVReadPRMVIO(struct drm_device *dev, int head, uint32_t reg) { … } static inline void NVWritePRMVIO(struct drm_device *dev, int head, uint32_t reg, uint8_t value) { … } static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable) { … } static inline bool NVGetEnablePalette(struct drm_device *dev, int head) { … } static inline void NVWriteVgaAttr(struct drm_device *dev, int head, uint8_t index, uint8_t value) { … } static inline uint8_t NVReadVgaAttr(struct drm_device *dev, int head, uint8_t index) { … } static inline void NVVgaSeqReset(struct drm_device *dev, int head, bool start) { … } static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect) { … } static inline bool nv_heads_tied(struct drm_device *dev) { … } /* makes cr0-7 on the specified head read-only */ static inline bool nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock) { … } static inline void nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock) { … } /* renders the extended crtc regs (cr19+) on all crtcs impervious: * immutable and unreadable */ static inline bool NVLockVgaCrtcs(struct drm_device *dev, bool lock) { … } /* nv04 cursor max dimensions of 32x32 (A1R5G5B5) */ #define NV04_CURSOR_SIZE … /* limit nv10 cursors to 64x64 (ARGB8) (we could go to 64x255) */ #define NV10_CURSOR_SIZE … static inline int nv_cursor_width(struct drm_device *dev) { … } static inline void nv_fix_nv40_hw_cursor(struct drm_device *dev, int head) { … } static inline void nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset) { … } static inline void nv_show_cursor(struct drm_device *dev, int head, bool show) { … } static inline uint32_t nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp) { … } #endif /* __NOUVEAU_HW_H__ */
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