linux/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c

/*
 * Copyright (C) 2009 Francisco Jerez.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "nouveau_drv.h"
#include "nouveau_encoder.h"
#include "nouveau_crtc.h"
#include "hw.h"
#include "tvnv17.h"

const char * const nv17_tv_norm_names[NUM_TV_NORMS] =;

/* TV standard specific parameters */

struct nv17_tv_norm_params nv17_tv_norms[NUM_TV_NORMS] =;

/*
 * The following is some guesswork on how the TV encoder flicker
 * filter/rescaler works:
 *
 * It seems to use some sort of resampling filter, it is controlled
 * through the registers at NV_PTV_HFILTER and NV_PTV_VFILTER, they
 * control the horizontal and vertical stage respectively, there is
 * also NV_PTV_HFILTER2 the blob fills identically to NV_PTV_HFILTER,
 * but they seem to do nothing. A rough guess might be that they could
 * be used to independently control the filtering of each interlaced
 * field, but I don't know how they are enabled. The whole filtering
 * process seems to be disabled with bits 26:27 of PTV_200, but we
 * aren't doing that.
 *
 * The layout of both register sets is the same:
 *
 * A: [BASE+0x18]...[BASE+0x0] [BASE+0x58]..[BASE+0x40]
 * B: [BASE+0x34]...[BASE+0x1c] [BASE+0x74]..[BASE+0x5c]
 *
 * Each coefficient is stored in bits [31],[15:9] in two's complement
 * format. They seem to be some kind of weights used in a low-pass
 * filter. Both A and B coefficients are applied to the 14 nearest
 * samples on each side (Listed from nearest to furthermost.  They
 * roughly cover 2 framebuffer pixels on each side).  They are
 * probably multiplied with some more hardwired weights before being
 * used: B-coefficients are applied the same on both sides,
 * A-coefficients are inverted before being applied to the opposite
 * side.
 *
 * After all the hassle, I got the following formula by empirical
 * means...
 */

#define calc_overscan(o)

#define id1
#define id2
#define id3
#define id4
#define id5

static struct filter_params{} fparams[2][4] =;

static void tv_setup_filter(struct drm_encoder *encoder)
{}

/* Hardware state saving/restoring */

static void tv_save_filter(struct drm_device *dev, uint32_t base,
			   uint32_t regs[4][7])
{}

static void tv_load_filter(struct drm_device *dev, uint32_t base,
			   uint32_t regs[4][7])
{}

void nv17_tv_state_save(struct drm_device *dev, struct nv17_tv_state *state)
{}

void nv17_tv_state_load(struct drm_device *dev, struct nv17_tv_state *state)
{}

/* Timings similar to the ones the blob sets */

const struct drm_display_mode nv17_tv_modes[] =;

void nv17_tv_update_properties(struct drm_encoder *encoder)
{}

void nv17_tv_update_rescaler(struct drm_encoder *encoder)
{}

void nv17_ctv_update_rescaler(struct drm_encoder *encoder)
{}