/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * twl4030.h - header for TWL4030 PM and audio CODEC device * * Copyright (C) 2005-2006 Texas Instruments, Inc. * * Based on tlv320aic23.c: * Copyright (c) by Kai Svahn <[email protected]> */ #ifndef __TWL_H_ #define __TWL_H_ #include <linux/types.h> #include <linux/input/matrix_keypad.h> /* * Using the twl4030 core we address registers using a pair * { module id, relative register offset } * which that core then maps to the relevant * { i2c slave, absolute register address } * * The module IDs are meaningful only to the twl4030 core code, * which uses them as array indices to look up the first register * address each module uses within a given i2c slave. */ /* Module IDs for similar functionalities found in twl4030/twl6030 */ enum twl_module_ids { … }; /* Modules only available in twl4030 series */ enum twl4030_module_ids { … }; /* Modules only available in twl6030 series */ enum twl6030_module_ids { … }; /* Until the clients has been converted to use TWL_MODULE_LED */ #define TWL4030_MODULE_LED … #define GPIO_INTR_OFFSET … #define KEYPAD_INTR_OFFSET … #define BCI_INTR_OFFSET … #define MADC_INTR_OFFSET … #define USB_INTR_OFFSET … #define CHARGERFAULT_INTR_OFFSET … #define BCI_PRES_INTR_OFFSET … #define USB_PRES_INTR_OFFSET … #define RTC_INTR_OFFSET … /* * Offset from TWL6030_IRQ_BASE / pdata->irq_base */ #define PWR_INTR_OFFSET … #define HOTDIE_INTR_OFFSET … #define SMPSLDO_INTR_OFFSET … #define BATDETECT_INTR_OFFSET … #define SIMDETECT_INTR_OFFSET … #define MMCDETECT_INTR_OFFSET … #define GASGAUGE_INTR_OFFSET … #define USBOTG_INTR_OFFSET … #define CHARGER_INTR_OFFSET … #define RSV_INTR_OFFSET … /* INT register offsets */ #define REG_INT_STS_A … #define REG_INT_STS_B … #define REG_INT_STS_C … #define REG_INT_MSK_LINE_A … #define REG_INT_MSK_LINE_B … #define REG_INT_MSK_LINE_C … #define REG_INT_MSK_STS_A … #define REG_INT_MSK_STS_B … #define REG_INT_MSK_STS_C … /* MASK INT REG GROUP A */ #define TWL6030_PWR_INT_MASK … #define TWL6030_RTC_INT_MASK … #define TWL6030_HOTDIE_INT_MASK … #define TWL6030_SMPSLDOA_INT_MASK … /* MASK INT REG GROUP B */ #define TWL6030_SMPSLDOB_INT_MASK … #define TWL6030_BATDETECT_INT_MASK … #define TWL6030_SIMDETECT_INT_MASK … #define TWL6030_MMCDETECT_INT_MASK … #define TWL6030_GPADC_INT_MASK … #define TWL6030_GASGAUGE_INT_MASK … /* MASK INT REG GROUP C */ #define TWL6030_USBOTG_INT_MASK … #define TWL6030_CHARGER_CTRL_INT_MASK … #define TWL6030_CHARGER_FAULT_INT_MASK … #define TWL6030_MMCCTRL … #define VMMC_AUTO_OFF … #define SW_FC … #define STS_MMC … #define TWL6030_CFG_INPUT_PUPD3 … #define MMC_PU … #define MMC_PD … #define TWL_SIL_TYPE(rev) … #define TWL_SIL_REV(rev) … #define TWL_SIL_5030 … #define TWL5030_REV_1_0 … #define TWL5030_REV_1_1 … #define TWL5030_REV_1_2 … #define TWL4030_CLASS_ID … #define TWL6030_CLASS_ID … unsigned int twl_rev(void); #define GET_TWL_REV … #define TWL_CLASS_IS(class, id) … TWL_CLASS_IS(4030, TWL4030_CLASS_ID) TWL_CLASS_IS(6030, TWL6030_CLASS_ID) /* Set the regcache bypass for the regmap associated with the nodule */ int twl_set_regcache_bypass(u8 mod_no, bool enable); /* * Read and write several 8-bit registers at once. */ int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); /* * Read and write single 8-bit registers */ static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) { … } static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) { … } static inline int twl_i2c_write_u16(u8 mod_no, u16 val, u8 reg) { … } static inline int twl_i2c_read_u16(u8 mod_no, u16 *val, u8 reg) { … } int twl_get_type(void); int twl_get_version(void); int twl_get_hfclk_rate(void); int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); int twl6030_interrupt_mask(u8 bit_mask, u8 offset); /* Card detect Configuration for MMC1 Controller on OMAP4 */ #ifdef CONFIG_TWL4030_CORE int twl6030_mmc_card_detect_config(void); #else static inline int twl6030_mmc_card_detect_config(void) { pr_debug("twl6030_mmc_card_detect_config not supported\n"); return 0; } #endif /* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */ #ifdef CONFIG_TWL4030_CORE int twl6030_mmc_card_detect(struct device *dev, int slot); #else static inline int twl6030_mmc_card_detect(struct device *dev, int slot) { pr_debug("Call back twl6030_mmc_card_detect not supported\n"); return -EIO; } #endif /*----------------------------------------------------------------------*/ /* * NOTE: at up to 1024 registers, this is a big chip. * * Avoid putting register declarations in this file, instead of into * a driver-private file, unless some of the registers in a block * need to be shared with other drivers. One example is blocks that * have Secondary IRQ Handler (SIH) registers. */ #define TWL4030_SIH_CTRL_EXCLEN_MASK … #define TWL4030_SIH_CTRL_PENDDIS_MASK … #define TWL4030_SIH_CTRL_COR_MASK … /*----------------------------------------------------------------------*/ /* * GPIO Block Register offsets (use TWL4030_MODULE_GPIO) */ #define REG_GPIODATAIN1 … #define REG_GPIODATAIN2 … #define REG_GPIODATAIN3 … #define REG_GPIODATADIR1 … #define REG_GPIODATADIR2 … #define REG_GPIODATADIR3 … #define REG_GPIODATAOUT1 … #define REG_GPIODATAOUT2 … #define REG_GPIODATAOUT3 … #define REG_CLEARGPIODATAOUT1 … #define REG_CLEARGPIODATAOUT2 … #define REG_CLEARGPIODATAOUT3 … #define REG_SETGPIODATAOUT1 … #define REG_SETGPIODATAOUT2 … #define REG_SETGPIODATAOUT3 … #define REG_GPIO_DEBEN1 … #define REG_GPIO_DEBEN2 … #define REG_GPIO_DEBEN3 … #define REG_GPIO_CTRL … #define REG_GPIOPUPDCTR1 … #define REG_GPIOPUPDCTR2 … #define REG_GPIOPUPDCTR3 … #define REG_GPIOPUPDCTR4 … #define REG_GPIOPUPDCTR5 … #define REG_GPIO_ISR1A … #define REG_GPIO_ISR2A … #define REG_GPIO_ISR3A … #define REG_GPIO_IMR1A … #define REG_GPIO_IMR2A … #define REG_GPIO_IMR3A … #define REG_GPIO_ISR1B … #define REG_GPIO_ISR2B … #define REG_GPIO_ISR3B … #define REG_GPIO_IMR1B … #define REG_GPIO_IMR2B … #define REG_GPIO_IMR3B … #define REG_GPIO_EDR1 … #define REG_GPIO_EDR2 … #define REG_GPIO_EDR3 … #define REG_GPIO_EDR4 … #define REG_GPIO_EDR5 … #define REG_GPIO_SIH_CTRL … /* Up to 18 signals are available as GPIOs, when their * pins are not assigned to another use (such as ULPI/USB). */ #define TWL4030_GPIO_MAX … /*----------------------------------------------------------------------*/ /*Interface Bit Register (INTBR) offsets *(Use TWL_4030_MODULE_INTBR) */ #define REG_IDCODE_7_0 … #define REG_IDCODE_15_8 … #define REG_IDCODE_16_23 … #define REG_IDCODE_31_24 … #define REG_GPPUPDCTR1 … #define REG_UNLOCK_TEST_REG … /*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */ #define I2C_SCL_CTRL_PU … #define I2C_SDA_CTRL_PU … #define SR_I2C_SCL_CTRL_PU … #define SR_I2C_SDA_CTRL_PU … #define TWL_EEPROM_R_UNLOCK … /*----------------------------------------------------------------------*/ /* * Keypad register offsets (use TWL4030_MODULE_KEYPAD) * ... SIH/interrupt only */ #define TWL4030_KEYPAD_KEYP_ISR1 … #define TWL4030_KEYPAD_KEYP_IMR1 … #define TWL4030_KEYPAD_KEYP_ISR2 … #define TWL4030_KEYPAD_KEYP_IMR2 … #define TWL4030_KEYPAD_KEYP_SIR … #define TWL4030_KEYPAD_KEYP_EDR … #define TWL4030_KEYPAD_KEYP_SIH_CTRL … /*----------------------------------------------------------------------*/ /* * Multichannel ADC register offsets (use TWL4030_MODULE_MADC) * ... SIH/interrupt only */ #define TWL4030_MADC_ISR1 … #define TWL4030_MADC_IMR1 … #define TWL4030_MADC_ISR2 … #define TWL4030_MADC_IMR2 … #define TWL4030_MADC_SIR … #define TWL4030_MADC_EDR … #define TWL4030_MADC_SIH_CTRL … /*----------------------------------------------------------------------*/ /* * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS) */ #define TWL4030_INTERRUPTS_BCIISR1A … #define TWL4030_INTERRUPTS_BCIISR2A … #define TWL4030_INTERRUPTS_BCIIMR1A … #define TWL4030_INTERRUPTS_BCIIMR2A … #define TWL4030_INTERRUPTS_BCIISR1B … #define TWL4030_INTERRUPTS_BCIISR2B … #define TWL4030_INTERRUPTS_BCIIMR1B … #define TWL4030_INTERRUPTS_BCIIMR2B … #define TWL4030_INTERRUPTS_BCISIR1 … #define TWL4030_INTERRUPTS_BCISIR2 … #define TWL4030_INTERRUPTS_BCIEDR1 … #define TWL4030_INTERRUPTS_BCIEDR2 … #define TWL4030_INTERRUPTS_BCIEDR3 … #define TWL4030_INTERRUPTS_BCISIHCTRL … /*----------------------------------------------------------------------*/ /* * Power Interrupt block register offsets (use TWL4030_MODULE_INT) */ #define TWL4030_INT_PWR_ISR1 … #define TWL4030_INT_PWR_IMR1 … #define TWL4030_INT_PWR_ISR2 … #define TWL4030_INT_PWR_IMR2 … #define TWL4030_INT_PWR_SIR … #define TWL4030_INT_PWR_EDR1 … #define TWL4030_INT_PWR_EDR2 … #define TWL4030_INT_PWR_SIH_CTRL … /*----------------------------------------------------------------------*/ /* * Accessory Interrupts */ #define TWL5031_ACIIMR_LSB … #define TWL5031_ACIIMR_MSB … #define TWL5031_ACIIDR_LSB … #define TWL5031_ACIIDR_MSB … #define TWL5031_ACCISR1 … #define TWL5031_ACCIMR1 … #define TWL5031_ACCISR2 … #define TWL5031_ACCIMR2 … #define TWL5031_ACCSIR … #define TWL5031_ACCEDR1 … #define TWL5031_ACCSIHCTRL … /*----------------------------------------------------------------------*/ /* * Battery Charger Controller */ #define TWL5031_INTERRUPTS_BCIISR1 … #define TWL5031_INTERRUPTS_BCIIMR1 … #define TWL5031_INTERRUPTS_BCIISR2 … #define TWL5031_INTERRUPTS_BCIIMR2 … #define TWL5031_INTERRUPTS_BCISIR … #define TWL5031_INTERRUPTS_BCIEDR1 … #define TWL5031_INTERRUPTS_BCIEDR2 … #define TWL5031_INTERRUPTS_BCISIHCTRL … /*----------------------------------------------------------------------*/ /* * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER) */ #define TWL4030_PM_MASTER_CFG_P1_TRANSITION … #define TWL4030_PM_MASTER_CFG_P2_TRANSITION … #define TWL4030_PM_MASTER_CFG_P3_TRANSITION … #define TWL4030_PM_MASTER_CFG_P123_TRANSITION … #define TWL4030_PM_MASTER_STS_BOOT … #define TWL4030_PM_MASTER_CFG_BOOT … #define TWL4030_PM_MASTER_SHUNDAN … #define TWL4030_PM_MASTER_BOOT_BCI … #define TWL4030_PM_MASTER_CFG_PWRANA1 … #define TWL4030_PM_MASTER_CFG_PWRANA2 … #define TWL4030_PM_MASTER_BACKUP_MISC_STS … #define TWL4030_PM_MASTER_BACKUP_MISC_CFG … #define TWL4030_PM_MASTER_BACKUP_MISC_TST … #define TWL4030_PM_MASTER_PROTECT_KEY … #define TWL4030_PM_MASTER_STS_HW_CONDITIONS … #define TWL4030_PM_MASTER_P1_SW_EVENTS … #define TWL4030_PM_MASTER_P2_SW_EVENTS … #define TWL4030_PM_MASTER_P3_SW_EVENTS … #define TWL4030_PM_MASTER_STS_P123_STATE … #define TWL4030_PM_MASTER_PB_CFG … #define TWL4030_PM_MASTER_PB_WORD_MSB … #define TWL4030_PM_MASTER_PB_WORD_LSB … #define TWL4030_PM_MASTER_SEQ_ADD_W2P … #define TWL4030_PM_MASTER_SEQ_ADD_P2A … #define TWL4030_PM_MASTER_SEQ_ADD_A2W … #define TWL4030_PM_MASTER_SEQ_ADD_A2S … #define TWL4030_PM_MASTER_SEQ_ADD_S2A12 … #define TWL4030_PM_MASTER_SEQ_ADD_S2A3 … #define TWL4030_PM_MASTER_SEQ_ADD_WARM … #define TWL4030_PM_MASTER_MEMORY_ADDRESS … #define TWL4030_PM_MASTER_MEMORY_DATA … #define TWL4030_PM_MASTER_KEY_CFG1 … #define TWL4030_PM_MASTER_KEY_CFG2 … #define TWL4030_PM_MASTER_KEY_TST1 … #define TWL4030_PM_MASTER_KEY_TST2 … #define TWL4030_PM_MASTER_GLOBAL_TST … #define TWL6030_PHOENIX_DEV_ON … /*----------------------------------------------------------------------*/ /* Power bus message definitions */ /* The TWL4030/5030 splits its power-management resources (the various * regulators, clock and reset lines) into 3 processor groups - P1, P2 and * P3. These groups can then be configured to transition between sleep, wait-on * and active states by sending messages to the power bus. See Section 5.4.2 * Power Resources of TWL4030 TRM */ /* Processor groups */ #define DEV_GRP_NULL … #define DEV_GRP_P1 … #define DEV_GRP_P2 … #define DEV_GRP_P3 … /* Resource groups */ #define RES_GRP_RES … #define RES_GRP_PP … #define RES_GRP_RC … #define RES_GRP_PP_RC … #define RES_GRP_PR … #define RES_GRP_PP_PR … #define RES_GRP_RC_PR … #define RES_GRP_ALL … #define RES_TYPE2_R0 … #define RES_TYPE2_R1 … #define RES_TYPE2_R2 … #define RES_TYPE_R0 … #define RES_TYPE_ALL … /* Resource states */ #define RES_STATE_WRST … #define RES_STATE_ACTIVE … #define RES_STATE_SLEEP … #define RES_STATE_OFF … /* Power resources */ /* Power providers */ #define RES_VAUX1 … #define RES_VAUX2 … #define RES_VAUX3 … #define RES_VAUX4 … #define RES_VMMC1 … #define RES_VMMC2 … #define RES_VPLL1 … #define RES_VPLL2 … #define RES_VSIM … #define RES_VDAC … #define RES_VINTANA1 … #define RES_VINTANA2 … #define RES_VINTDIG … #define RES_VIO … #define RES_VDD1 … #define RES_VDD2 … #define RES_VUSB_1V5 … #define RES_VUSB_1V8 … #define RES_VUSB_3V1 … #define RES_VUSBCP … #define RES_REGEN … /* Reset and control */ #define RES_NRES_PWRON … #define RES_CLKEN … #define RES_SYSEN … #define RES_HFCLKOUT … #define RES_32KCLKOUT … #define RES_RESET … /* Power Reference */ #define RES_MAIN_REF … #define TOTAL_RESOURCES … /* * Power Bus Message Format ... these can be sent individually by Linux, * but are usually part of downloaded scripts that are run when various * power events are triggered. * * Broadcast Message (16 Bits): * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] * RES_STATE[3:0] * * Singular Message (16 Bits): * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] */ #define MSG_BROADCAST(devgrp, grp, type, type2, state) … #define MSG_SINGULAR(devgrp, id, state) … #define MSG_BROADCAST_ALL(devgrp, state) … #define MSG_BROADCAST_REF … #define MSG_BROADCAST_PROV … #define MSG_BROADCAST__CLK_RST … /*----------------------------------------------------------------------*/ struct twl4030_clock_init_data { … }; struct twl4030_bci_platform_data { … }; /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */ struct twl4030_gpio_platform_data { … }; struct twl4030_madc_platform_data { … }; /* Boards have unique mappings of {row, col} --> keycode. * Column and row are 8 bits each, but range only from 0..7. * a PERSISTENT_KEY is "always on" and never reported. */ #define PERSISTENT_KEY(r, c) … struct twl4030_keypad_data { … }; enum twl4030_usb_mode { … }; struct twl4030_usb_data { … }; struct twl4030_ins { … }; struct twl4030_script { … }; struct twl4030_resconfig { … }; struct twl4030_power_data { … }; extern int twl4030_remove_script(u8 flags); extern void twl4030_power_off(void); struct twl4030_codec_data { … }; struct twl4030_vibra_data { … }; struct twl4030_audio_data { … }; struct twl_regulator_driver_data { … }; /* chip-specific feature flags, for twl_regulator_driver_data.features */ #define TWL4030_VAUX2 … #define TPS_SUBSET … #define TWL5031 … #define TWL6030_CLASS … #define TWL6032_SUBCLASS … #define TWL4030_ALLOW_UNSUPPORTED … /*----------------------------------------------------------------------*/ int twl4030_sih_setup(struct device *dev, int module, int irq_base); /* Offsets to Power Registers */ #define TWL4030_VDAC_DEV_GRP … #define TWL4030_VDAC_DEDICATED … #define TWL4030_VAUX1_DEV_GRP … #define TWL4030_VAUX1_DEDICATED … #define TWL4030_VAUX2_DEV_GRP … #define TWL4030_VAUX2_DEDICATED … #define TWL4030_VAUX3_DEV_GRP … #define TWL4030_VAUX3_DEDICATED … /*----------------------------------------------------------------------*/ /* Linux-specific regulator identifiers ... for now, we only support * the LDOs, and leave the three buck converters alone. VDD1 and VDD2 * need to tie into hardware based voltage scaling (cpufreq etc), while * VIO is generally fixed. */ /* TWL4030 SMPS/LDO's */ /* EXTERNAL dc-to-dc buck converters */ #define TWL4030_REG_VDD1 … #define TWL4030_REG_VDD2 … #define TWL4030_REG_VIO … /* EXTERNAL LDOs */ #define TWL4030_REG_VDAC … #define TWL4030_REG_VPLL1 … #define TWL4030_REG_VPLL2 … #define TWL4030_REG_VMMC1 … #define TWL4030_REG_VMMC2 … #define TWL4030_REG_VSIM … #define TWL4030_REG_VAUX1 … #define TWL4030_REG_VAUX2_4030 … #define TWL4030_REG_VAUX2 … #define TWL4030_REG_VAUX3 … #define TWL4030_REG_VAUX4 … /* INTERNAL LDOs */ #define TWL4030_REG_VINTANA1 … #define TWL4030_REG_VINTANA2 … #define TWL4030_REG_VINTDIG … #define TWL4030_REG_VUSB1V5 … #define TWL4030_REG_VUSB1V8 … #define TWL4030_REG_VUSB3V1 … /* TWL6030 SMPS/LDO's */ /* EXTERNAL dc-to-dc buck convertor controllable via SR */ #define TWL6030_REG_VDD1 … #define TWL6030_REG_VDD2 … #define TWL6030_REG_VDD3 … /* Non SR compliant dc-to-dc buck convertors */ #define TWL6030_REG_VMEM … #define TWL6030_REG_V2V1 … #define TWL6030_REG_V1V29 … #define TWL6030_REG_V1V8 … /* EXTERNAL LDOs */ #define TWL6030_REG_VAUX1_6030 … #define TWL6030_REG_VAUX2_6030 … #define TWL6030_REG_VAUX3_6030 … #define TWL6030_REG_VMMC … #define TWL6030_REG_VPP … #define TWL6030_REG_VUSIM … #define TWL6030_REG_VANA … #define TWL6030_REG_VCXIO … #define TWL6030_REG_VDAC … #define TWL6030_REG_VUSB … /* INTERNAL LDOs */ #define TWL6030_REG_VRTC … #define TWL6030_REG_CLK32KG … /* LDOs on 6025 have different names */ #define TWL6032_REG_LDO2 … #define TWL6032_REG_LDO4 … #define TWL6032_REG_LDO3 … #define TWL6032_REG_LDO5 … #define TWL6032_REG_LDO1 … #define TWL6032_REG_LDO7 … #define TWL6032_REG_LDO6 … #define TWL6032_REG_LDOLN … #define TWL6032_REG_LDOUSB … /* 6025 DCDC supplies */ #define TWL6032_REG_SMPS3 … #define TWL6032_REG_SMPS4 … #define TWL6032_REG_VIO … #endif /* End of __TWL4030_H */
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