/* SPDX-License-Identifier: GPL-2.0-or-later */ /* atlx_hw.h -- common hardware definitions for Attansic network drivers * * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. * Copyright(c) 2006 - 2007 Chris Snook <[email protected]> * Copyright(c) 2006 - 2008 Jay Cliburn <[email protected]> * Copyright(c) 2007 Atheros Corporation. All rights reserved. * * Derived from Intel e1000 driver * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. */ #ifndef ATLX_H #define ATLX_H #include <linux/module.h> #include <linux/types.h> #define ATLX_ERR_PHY … #define ATLX_ERR_PHY_SPEED … #define ATLX_ERR_PHY_RES … #define SPEED_0 … #define SPEED_10 … #define SPEED_100 … #define SPEED_1000 … #define HALF_DUPLEX … #define FULL_DUPLEX … #define MEDIA_TYPE_AUTO_SENSOR … /* register definitions */ #define REG_PM_CTRLSTAT … #define REG_PCIE_CAP_LIST … #define REG_VPD_CAP … #define VPD_CAP_ID_MASK … #define VPD_CAP_ID_SHIFT … #define VPD_CAP_NEXT_PTR_MASK … #define VPD_CAP_NEXT_PTR_SHIFT … #define VPD_CAP_VPD_ADDR_MASK … #define VPD_CAP_VPD_ADDR_SHIFT … #define VPD_CAP_VPD_FLAG … #define REG_VPD_DATA … #define REG_SPI_FLASH_CTRL … #define SPI_FLASH_CTRL_STS_NON_RDY … #define SPI_FLASH_CTRL_STS_WEN … #define SPI_FLASH_CTRL_STS_WPEN … #define SPI_FLASH_CTRL_DEV_STS_MASK … #define SPI_FLASH_CTRL_DEV_STS_SHIFT … #define SPI_FLASH_CTRL_INS_MASK … #define SPI_FLASH_CTRL_INS_SHIFT … #define SPI_FLASH_CTRL_START … #define SPI_FLASH_CTRL_EN_VPD … #define SPI_FLASH_CTRL_LDSTART … #define SPI_FLASH_CTRL_CS_HI_MASK … #define SPI_FLASH_CTRL_CS_HI_SHIFT … #define SPI_FLASH_CTRL_CS_HOLD_MASK … #define SPI_FLASH_CTRL_CS_HOLD_SHIFT … #define SPI_FLASH_CTRL_CLK_LO_MASK … #define SPI_FLASH_CTRL_CLK_LO_SHIFT … #define SPI_FLASH_CTRL_CLK_HI_MASK … #define SPI_FLASH_CTRL_CLK_HI_SHIFT … #define SPI_FLASH_CTRL_CS_SETUP_MASK … #define SPI_FLASH_CTRL_CS_SETUP_SHIFT … #define SPI_FLASH_CTRL_EROM_PGSZ_MASK … #define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT … #define SPI_FLASH_CTRL_WAIT_READY … #define REG_SPI_ADDR … #define REG_SPI_DATA … #define REG_SPI_FLASH_CONFIG … #define SPI_FLASH_CONFIG_LD_ADDR_MASK … #define SPI_FLASH_CONFIG_LD_ADDR_SHIFT … #define SPI_FLASH_CONFIG_VPD_ADDR_MASK … #define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT … #define SPI_FLASH_CONFIG_LD_EXIST … #define REG_SPI_FLASH_OP_PROGRAM … #define REG_SPI_FLASH_OP_SC_ERASE … #define REG_SPI_FLASH_OP_CHIP_ERASE … #define REG_SPI_FLASH_OP_RDID … #define REG_SPI_FLASH_OP_WREN … #define REG_SPI_FLASH_OP_RDSR … #define REG_SPI_FLASH_OP_WRSR … #define REG_SPI_FLASH_OP_READ … #define REG_TWSI_CTRL … #define TWSI_CTRL_LD_OFFSET_MASK … #define TWSI_CTRL_LD_OFFSET_SHIFT … #define TWSI_CTRL_LD_SLV_ADDR_MASK … #define TWSI_CTRL_LD_SLV_ADDR_SHIFT … #define TWSI_CTRL_SW_LDSTART … #define TWSI_CTRL_HW_LDSTART … #define TWSI_CTRL_SMB_SLV_ADDR_MASK … #define TWSI_CTRL_SMB_SLV_ADDR_SHIFT … #define TWSI_CTRL_LD_EXIST … #define TWSI_CTRL_READ_FREQ_SEL_MASK … #define TWSI_CTRL_READ_FREQ_SEL_SHIFT … #define TWSI_CTRL_FREQ_SEL_100K … #define TWSI_CTRL_FREQ_SEL_200K … #define TWSI_CTRL_FREQ_SEL_300K … #define TWSI_CTRL_FREQ_SEL_400K … #define TWSI_CTRL_SMB_SLV_ADDR … #define TWSI_CTRL_WRITE_FREQ_SEL_MASK … #define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT … #define REG_PCIE_DEV_MISC_CTRL … #define PCIE_DEV_MISC_CTRL_EXT_PIPE … #define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS … #define PCIE_DEV_MISC_CTRL_SPIROM_EXIST … #define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN … #define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN … #define REG_PCIE_PHYMISC … #define PCIE_PHYMISC_FORCE_RCV_DET … #define REG_PCIE_DLL_TX_CTRL1 … #define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK … #define PCIE_DLL_TX_CTRL1_DEF … #define REG_LTSSM_TEST_MODE … #define LTSSM_TEST_MODE_DEF … /* Master Control Register */ #define REG_MASTER_CTRL … #define MASTER_CTRL_SOFT_RST … #define MASTER_CTRL_MTIMER_EN … #define MASTER_CTRL_ITIMER_EN … #define MASTER_CTRL_MANUAL_INT … #define MASTER_CTRL_REV_NUM_SHIFT … #define MASTER_CTRL_REV_NUM_MASK … #define MASTER_CTRL_DEV_ID_SHIFT … #define MASTER_CTRL_DEV_ID_MASK … /* Timer Initial Value Register */ #define REG_MANUAL_TIMER_INIT … /* IRQ Moderator Timer Initial Value Register */ #define REG_IRQ_MODU_TIMER_INIT … #define REG_PHY_ENABLE … /* IRQ Anti-Lost Timer Initial Value Register */ #define REG_CMBDISDMA_TIMER … /* Block IDLE Status Register */ #define REG_IDLE_STATUS … /* MDIO Control Register */ #define REG_MDIO_CTRL … #define MDIO_DATA_MASK … #define MDIO_DATA_SHIFT … #define MDIO_REG_ADDR_MASK … #define MDIO_REG_ADDR_SHIFT … #define MDIO_RW … #define MDIO_SUP_PREAMBLE … #define MDIO_START … #define MDIO_CLK_SEL_SHIFT … #define MDIO_CLK_25_4 … #define MDIO_CLK_25_6 … #define MDIO_CLK_25_8 … #define MDIO_CLK_25_10 … #define MDIO_CLK_25_14 … #define MDIO_CLK_25_20 … #define MDIO_CLK_25_28 … #define MDIO_BUSY … /* MII PHY Status Register */ #define REG_PHY_STATUS … /* BIST Control and Status Register0 (for the Packet Memory) */ #define REG_BIST0_CTRL … #define BIST0_NOW … #define BIST0_SRAM_FAIL … #define BIST0_FUSE_FLAG … #define REG_BIST1_CTRL … #define BIST1_NOW … #define BIST1_SRAM_FAIL … #define BIST1_FUSE_FLAG … /* SerDes Lock Detect Control and Status Register */ #define REG_SERDES_LOCK … #define SERDES_LOCK_DETECT … #define SERDES_LOCK_DETECT_EN … /* MAC Control Register */ #define REG_MAC_CTRL … #define MAC_CTRL_TX_EN … #define MAC_CTRL_RX_EN … #define MAC_CTRL_TX_FLOW … #define MAC_CTRL_RX_FLOW … #define MAC_CTRL_LOOPBACK … #define MAC_CTRL_DUPLX … #define MAC_CTRL_ADD_CRC … #define MAC_CTRL_PAD … #define MAC_CTRL_LENCHK … #define MAC_CTRL_HUGE_EN … #define MAC_CTRL_PRMLEN_SHIFT … #define MAC_CTRL_PRMLEN_MASK … #define MAC_CTRL_RMV_VLAN … #define MAC_CTRL_PROMIS_EN … #define MAC_CTRL_MC_ALL_EN … #define MAC_CTRL_BC_EN … /* MAC IPG/IFG Control Register */ #define REG_MAC_IPG_IFG … #define MAC_IPG_IFG_IPGT_SHIFT … #define MAC_IPG_IFG_IPGT_MASK … #define MAC_IPG_IFG_MIFG_SHIFT … #define MAC_IPG_IFG_MIFG_MASK … #define MAC_IPG_IFG_IPGR1_SHIFT … #define MAC_IPG_IFG_IPGR1_MASK … #define MAC_IPG_IFG_IPGR2_SHIFT … #define MAC_IPG_IFG_IPGR2_MASK … /* MAC STATION ADDRESS */ #define REG_MAC_STA_ADDR … /* Hash table for multicast address */ #define REG_RX_HASH_TABLE … /* MAC Half-Duplex Control Register */ #define REG_MAC_HALF_DUPLX_CTRL … #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT … #define MAC_HALF_DUPLX_CTRL_LCOL_MASK … #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT … #define MAC_HALF_DUPLX_CTRL_RETRY_MASK … #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN … #define MAC_HALF_DUPLX_CTRL_NO_BACK_C … #define MAC_HALF_DUPLX_CTRL_NO_BACK_P … #define MAC_HALF_DUPLX_CTRL_ABEBE … #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT … #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK … #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT … #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK … /* Maximum Frame Length Control Register */ #define REG_MTU … /* Wake-On-Lan control register */ #define REG_WOL_CTRL … #define WOL_PATTERN_EN … #define WOL_PATTERN_PME_EN … #define WOL_MAGIC_EN … #define WOL_MAGIC_PME_EN … #define WOL_LINK_CHG_EN … #define WOL_LINK_CHG_PME_EN … #define WOL_PATTERN_ST … #define WOL_MAGIC_ST … #define WOL_LINKCHG_ST … #define WOL_PT0_EN … #define WOL_PT1_EN … #define WOL_PT2_EN … #define WOL_PT3_EN … #define WOL_PT4_EN … #define WOL_PT0_MATCH … #define WOL_PT1_MATCH … #define WOL_PT2_MATCH … #define WOL_PT3_MATCH … #define WOL_PT4_MATCH … /* Internal SRAM Partition Register, high 32 bits */ #define REG_SRAM_RFD_ADDR … /* Descriptor Control register, high 32 bits */ #define REG_DESC_BASE_ADDR_HI … /* Interrupt Status Register */ #define REG_ISR … #define ISR_UR_DETECTED … #define ISR_FERR_DETECTED … #define ISR_NFERR_DETECTED … #define ISR_CERR_DETECTED … #define ISR_PHY_LINKDOWN … #define ISR_DIS_INT … /* Interrupt Mask Register */ #define REG_IMR … #define REG_RFD_RRD_IDX … #define REG_TPD_IDX … /* MII definitions */ /* PHY Common Register */ #define MII_ATLX_CR … #define MII_ATLX_SR … #define MII_ATLX_ESR … #define MII_ATLX_PSCR … #define MII_ATLX_PSSR … /* PHY Control Register */ #define MII_CR_SPEED_SELECT_MSB … #define MII_CR_COLL_TEST_ENABLE … #define MII_CR_FULL_DUPLEX … #define MII_CR_RESTART_AUTO_NEG … #define MII_CR_ISOLATE … #define MII_CR_POWER_DOWN … #define MII_CR_AUTO_NEG_EN … #define MII_CR_SPEED_SELECT_LSB … #define MII_CR_LOOPBACK … #define MII_CR_RESET … #define MII_CR_SPEED_MASK … #define MII_CR_SPEED_1000 … #define MII_CR_SPEED_100 … #define MII_CR_SPEED_10 … /* PHY Status Register */ #define MII_SR_EXTENDED_CAPS … #define MII_SR_JABBER_DETECT … #define MII_SR_LINK_STATUS … #define MII_SR_AUTONEG_CAPS … #define MII_SR_REMOTE_FAULT … #define MII_SR_AUTONEG_COMPLETE … #define MII_SR_PREAMBLE_SUPPRESS … #define MII_SR_EXTENDED_STATUS … #define MII_SR_100T2_HD_CAPS … #define MII_SR_100T2_FD_CAPS … #define MII_SR_10T_HD_CAPS … #define MII_SR_10T_FD_CAPS … #define MII_SR_100X_HD_CAPS … #define MII_SR_100X_FD_CAPS … #define MII_SR_100T4_CAPS … /* Link partner ability register */ #define MII_LPA_SLCT … #define MII_LPA_10HALF … #define MII_LPA_10FULL … #define MII_LPA_100HALF … #define MII_LPA_100FULL … #define MII_LPA_100BASE4 … #define MII_LPA_PAUSE … #define MII_LPA_ASYPAUSE … #define MII_LPA_RFAULT … #define MII_LPA_LPACK … #define MII_LPA_NPAGE … /* Autoneg Advertisement Register */ #define MII_AR_SELECTOR_FIELD … #define MII_AR_10T_HD_CAPS … #define MII_AR_10T_FD_CAPS … #define MII_AR_100TX_HD_CAPS … #define MII_AR_100TX_FD_CAPS … #define MII_AR_100T4_CAPS … #define MII_AR_PAUSE … #define MII_AR_ASM_DIR … #define MII_AR_REMOTE_FAULT … #define MII_AR_NEXT_PAGE … #define MII_AR_SPEED_MASK … #define MII_AR_DEFAULT_CAP_MASK … /* 1000BASE-T Control Register */ #define MII_ATLX_CR_1000T_HD_CAPS … #define MII_ATLX_CR_1000T_FD_CAPS … #define MII_ATLX_CR_1000T_REPEATER_DTE … #define MII_ATLX_CR_1000T_MS_VALUE … #define MII_ATLX_CR_1000T_MS_ENABLE … #define MII_ATLX_CR_1000T_TEST_MODE_NORMAL … #define MII_ATLX_CR_1000T_TEST_MODE_1 … #define MII_ATLX_CR_1000T_TEST_MODE_2 … #define MII_ATLX_CR_1000T_TEST_MODE_3 … #define MII_ATLX_CR_1000T_TEST_MODE_4 … #define MII_ATLX_CR_1000T_SPEED_MASK … #define MII_ATLX_CR_1000T_DEFAULT_CAP_MASK … /* 1000BASE-T Status Register */ #define MII_ATLX_SR_1000T_LP_HD_CAPS … #define MII_ATLX_SR_1000T_LP_FD_CAPS … #define MII_ATLX_SR_1000T_REMOTE_RX_STATUS … #define MII_ATLX_SR_1000T_LOCAL_RX_STATUS … #define MII_ATLX_SR_1000T_MS_CONFIG_RES … #define MII_ATLX_SR_1000T_MS_CONFIG_FAULT … #define MII_ATLX_SR_1000T_REMOTE_RX_STATUS_SHIFT … #define MII_ATLX_SR_1000T_LOCAL_RX_STATUS_SHIFT … /* Extended Status Register */ #define MII_ATLX_ESR_1000T_HD_CAPS … #define MII_ATLX_ESR_1000T_FD_CAPS … #define MII_ATLX_ESR_1000X_HD_CAPS … #define MII_ATLX_ESR_1000X_FD_CAPS … /* ATLX PHY Specific Control Register */ #define MII_ATLX_PSCR_JABBER_DISABLE … #define MII_ATLX_PSCR_POLARITY_REVERSAL … #define MII_ATLX_PSCR_SQE_TEST … #define MII_ATLX_PSCR_MAC_POWERDOWN … #define MII_ATLX_PSCR_CLK125_DISABLE … #define MII_ATLX_PSCR_MDI_MANUAL_MODE … #define MII_ATLX_PSCR_MDIX_MANUAL_MODE … #define MII_ATLX_PSCR_AUTO_X_1000T … #define MII_ATLX_PSCR_AUTO_X_MODE … #define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE … #define MII_ATLX_PSCR_MII_5BIT_ENABLE … #define MII_ATLX_PSCR_SCRAMBLER_DISABLE … #define MII_ATLX_PSCR_FORCE_LINK_GOOD … #define MII_ATLX_PSCR_ASSERT_CRS_ON_TX … #define MII_ATLX_PSCR_POLARITY_REVERSAL_SHIFT … #define MII_ATLX_PSCR_AUTO_X_MODE_SHIFT … #define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE_SHIFT … /* ATLX PHY Specific Status Register */ #define MII_ATLX_PSSR_SPD_DPLX_RESOLVED … #define MII_ATLX_PSSR_DPLX … #define MII_ATLX_PSSR_SPEED … #define MII_ATLX_PSSR_10MBS … #define MII_ATLX_PSSR_100MBS … #define MII_ATLX_PSSR_1000MBS … #define MII_DBG_ADDR … #define MII_DBG_DATA … /* PCI Command Register Bit Definitions */ #define PCI_REG_COMMAND … #define CMD_IO_SPACE … #define CMD_MEMORY_SPACE … #define CMD_BUS_MASTER … /* Wake Up Filter Control */ #define ATLX_WUFC_LNKC … #define ATLX_WUFC_MAG … #define ATLX_WUFC_EX … #define ATLX_WUFC_MC … #define ATLX_WUFC_BC … #define ADVERTISE_10_HALF … #define ADVERTISE_10_FULL … #define ADVERTISE_100_HALF … #define ADVERTISE_100_FULL … #define ADVERTISE_1000_HALF … #define ADVERTISE_1000_FULL … #define AUTONEG_ADVERTISE_10_100_ALL … #define AUTONEG_ADVERTISE_10_ALL … #define PHY_AUTO_NEG_TIME … #define PHY_FORCE_TIME … /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA */ #define EEPROM_SUM … struct atlx_spi_flash_dev { … }; #endif /* ATLX_H */
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