/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. * * Derived from Intel e1000 driver * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. */ #ifndef _ATL1C_HW_H_ #define _ATL1C_HW_H_ #include <linux/types.h> #include <linux/mii.h> #define FIELD_GETX(_x, _name) … #define FIELD_SETX(_x, _name, _v) … #define FIELDX(_name, _v) … struct atl1c_adapter; struct atl1c_hw; /* function prototype */ void atl1c_phy_disable(struct atl1c_hw *hw); void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr); int atl1c_phy_reset(struct atl1c_hw *hw); int atl1c_read_mac_addr(struct atl1c_hw *hw); bool atl1c_get_link_status(struct atl1c_hw *hw); int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex); u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr); void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value); int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data); bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value); int atl1c_phy_init(struct atl1c_hw *hw); int atl1c_check_eeprom_exist(struct atl1c_hw *hw); int atl1c_restart_autoneg(struct atl1c_hw *hw); int atl1c_phy_to_ps_link(struct atl1c_hw *hw); int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc); bool atl1c_wait_mdio_idle(struct atl1c_hw *hw); void atl1c_stop_phy_polling(struct atl1c_hw *hw); void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel); int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, u16 reg, u16 *phy_data); int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, u16 reg, u16 phy_data); int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr, u16 reg_addr, u16 *phy_data); int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr, u16 reg_addr, u16 phy_data); int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data); void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); /* hw-ids */ #define PCI_DEVICE_ID_ATTANSIC_L2C … #define PCI_DEVICE_ID_ATTANSIC_L1C … #define PCI_DEVICE_ID_ATHEROS_L2C_B … #define PCI_DEVICE_ID_ATHEROS_L2C_B2 … #define PCI_DEVICE_ID_ATHEROS_L1D … #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 … #define L2CB_V10 … #define L2CB_V11 … #define L2CB_V20 … #define L2CB_V21 … /* register definition */ #define REG_DEVICE_CAP … #define DEVICE_CAP_MAX_PAYLOAD_MASK … #define DEVICE_CAP_MAX_PAYLOAD_SHIFT … #define DEVICE_CTRL_MAXRRS_MIN … #define REG_LINK_CTRL … #define LINK_CTRL_L0S_EN … #define LINK_CTRL_L1_EN … #define LINK_CTRL_EXT_SYNC … #define REG_PCIE_IND_ACC_ADDR … #define REG_PCIE_IND_ACC_DATA … #define REG_DEV_SERIALNUM_CTRL … #define REG_DEV_MAC_SEL_MASK … #define REG_DEV_MAC_SEL_SHIFT … #define REG_DEV_SERIAL_NUM_EN_MASK … #define REG_DEV_SERIAL_NUM_EN_SHIFT … #define REG_TWSI_CTRL … #define TWSI_CTLR_FREQ_MASK … #define TWSI_CTRL_FREQ_SHIFT … #define TWSI_CTRL_FREQ_100K … #define TWSI_CTRL_FREQ_200K … #define TWSI_CTRL_FREQ_300K … #define TWSI_CTRL_FREQ_400K … #define TWSI_CTRL_LD_EXIST … #define TWSI_CTRL_HW_LDSTAT … #define TWSI_CTRL_SW_LDSTART … #define TWSI_CTRL_LD_OFFSET_MASK … #define TWSI_CTRL_LD_OFFSET_SHIFT … #define REG_PCIE_DEV_MISC_CTRL … #define PCIE_DEV_MISC_EXT_PIPE … #define PCIE_DEV_MISC_RETRY_BUFDIS … #define PCIE_DEV_MISC_SPIROM_EXIST … #define PCIE_DEV_MISC_SERDES_ENDIAN … #define PCIE_DEV_MISC_SERDES_SEL_DIN … #define REG_PCIE_PHYMISC … #define PCIE_PHYMISC_FORCE_RCV_DET … #define PCIE_PHYMISC_NFTS_MASK … #define PCIE_PHYMISC_NFTS_SHIFT … #define REG_PCIE_PHYMISC2 … #define PCIE_PHYMISC2_L0S_TH_MASK … #define PCIE_PHYMISC2_L0S_TH_SHIFT … #define L2CB1_PCIE_PHYMISC2_L0S_TH … #define PCIE_PHYMISC2_CDR_BW_MASK … #define PCIE_PHYMISC2_CDR_BW_SHIFT … #define L2CB1_PCIE_PHYMISC2_CDR_BW … #define REG_TWSI_DEBUG … #define TWSI_DEBUG_DEV_EXIST … #define REG_DMA_DBG … #define DMA_DBG_VENDOR_MSG … #define REG_EEPROM_CTRL … #define EEPROM_CTRL_DATA_HI_MASK … #define EEPROM_CTRL_DATA_HI_SHIFT … #define EEPROM_CTRL_ADDR_MASK … #define EEPROM_CTRL_ADDR_SHIFT … #define EEPROM_CTRL_ACK … #define EEPROM_CTRL_RW … #define REG_EEPROM_DATA_LO … #define REG_OTP_CTRL … #define OTP_CTRL_CLK_EN … #define REG_PM_CTRL … #define PM_CTRL_HOTRST … #define PM_CTRL_MAC_ASPM_CHK … #define PM_CTRL_SA_DLY_EN … #define PM_CTRL_L0S_BUFSRX_EN … #define PM_CTRL_LCKDET_TIMER_MASK … #define PM_CTRL_LCKDET_TIMER_SHIFT … #define PM_CTRL_LCKDET_TIMER_DEF … #define PM_CTRL_PM_REQ_TIMER_MASK … #define PM_CTRL_PM_REQ_TIMER_SHIFT … #define PM_CTRL_PM_REQ_TO_DEF … #define PMCTRL_TXL1_AFTER_L0S … #define L1D_PMCTRL_L1_ENTRY_TM_MASK … #define L1D_PMCTRL_L1_ENTRY_TM_SHIFT … #define L1D_PMCTRL_L1_ENTRY_TM_DIS … #define L1D_PMCTRL_L1_ENTRY_TM_2US … #define L1D_PMCTRL_L1_ENTRY_TM_4US … #define L1D_PMCTRL_L1_ENTRY_TM_8US … #define L1D_PMCTRL_L1_ENTRY_TM_16US … #define L1D_PMCTRL_L1_ENTRY_TM_24US … #define L1D_PMCTRL_L1_ENTRY_TM_32US … #define L1D_PMCTRL_L1_ENTRY_TM_63US … #define PM_CTRL_L1_ENTRY_TIMER_MASK … #define PM_CTRL_L1_ENTRY_TIMER_SHIFT … #define L2CB1_PM_CTRL_L1_ENTRY_TM … #define L1C_PM_CTRL_L1_ENTRY_TM … #define PM_CTRL_RCVR_WT_TIMER … #define PM_CTRL_CLK_PWM_VER1_1 … #define PM_CTRL_CLK_SWH_L1 … #define PM_CTRL_ASPM_L0S_EN … #define PM_CTRL_RXL1_AFTER_L0S … #define L1D_PMCTRL_L0S_TIMER_MASK … #define L1D_PMCTRL_L0S_TIMER_SHIFT … #define PM_CTRL_L0S_ENTRY_TIMER_MASK … #define PM_CTRL_L0S_ENTRY_TIMER_SHIFT … #define PM_CTRL_SERDES_BUFS_RX_L1_EN … #define PM_CTRL_SERDES_PD_EX_L1 … #define PM_CTRL_SERDES_PLL_L1_EN … #define PM_CTRL_SERDES_L1_EN … #define PM_CTRL_ASPM_L1_EN … #define PM_CTRL_CLK_REQ_EN … #define PM_CTRL_RBER_EN … #define PM_CTRL_SPRSDWER_EN … #define REG_LTSSM_ID_CTRL … #define LTSSM_ID_EN_WRO … /* Selene Master Control Register */ #define REG_MASTER_CTRL … #define MASTER_CTRL_OTP_SEL … #define MASTER_DEV_NUM_MASK … #define MASTER_DEV_NUM_SHIFT … #define MASTER_REV_NUM_MASK … #define MASTER_REV_NUM_SHIFT … #define MASTER_CTRL_INT_RDCLR … #define MASTER_CTRL_CLK_SEL_DIS … #define MASTER_CTRL_RX_ITIMER_EN … #define MASTER_CTRL_TX_ITIMER_EN … #define MASTER_CTRL_MANU_INT … #define MASTER_CTRL_MANUTIMER_EN … #define MASTER_CTRL_SA_TIMER_EN … #define MASTER_CTRL_OOB_DIS … #define MASTER_CTRL_WAKEN_25M … #define MASTER_CTRL_BERT_START … #define MASTER_PCIE_TSTMOD_MASK … #define MASTER_PCIE_TSTMOD_SHIFT … #define MASTER_PCIE_RST … #define MASTER_CTRL_SOFT_RST … #define DMA_MAC_RST_TO … /* Timer Initial Value Register */ #define REG_MANUAL_TIMER_INIT … /* IRQ ModeratorTimer Initial Value Register */ #define REG_IRQ_MODRT_TIMER_INIT … #define IRQ_MODRT_TIMER_MASK … #define IRQ_MODRT_TX_TIMER_SHIFT … #define IRQ_MODRT_RX_TIMER_SHIFT … #define REG_GPHY_CTRL … #define GPHY_CTRL_ADDR_MASK … #define GPHY_CTRL_ADDR_SHIFT … #define GPHY_CTRL_BP_VLTGSW … #define GPHY_CTRL_100AB_EN … #define GPHY_CTRL_10AB_EN … #define GPHY_CTRL_PHY_PLL_BYPASS … #define GPHY_CTRL_PWDOWN_HW … #define GPHY_CTRL_PHY_PLL_ON … #define GPHY_CTRL_SEL_ANA_RST … #define GPHY_CTRL_HIB_PULSE … #define GPHY_CTRL_HIB_EN … #define GPHY_CTRL_GIGA_DIS … #define GPHY_CTRL_PHY_IDDQ_DIS … #define GPHY_CTRL_PHY_IDDQ … #define GPHY_CTRL_LPW_EXIT … #define GPHY_CTRL_GATE_25M_EN … #define GPHY_CTRL_REV_ANEG … #define GPHY_CTRL_ANEG_NOW … #define GPHY_CTRL_LED_MODE … #define GPHY_CTRL_RTL_MODE … #define GPHY_CTRL_EXT_RESET … #define GPHY_CTRL_EXT_RST_TO … #define GPHY_CTRL_CLS … /* Block IDLE Status Register */ #define REG_IDLE_STATUS … #define IDLE_STATUS_SFORCE_MASK … #define IDLE_STATUS_SFORCE_SHIFT … #define IDLE_STATUS_CALIB_DONE … #define IDLE_STATUS_CALIB_RES_MASK … #define IDLE_STATUS_CALIB_RES_SHIFT … #define IDLE_STATUS_CALIBERR_MASK … #define IDLE_STATUS_CALIBERR_SHIFT … #define IDLE_STATUS_TXQ_BUSY … #define IDLE_STATUS_RXQ_BUSY … #define IDLE_STATUS_TXMAC_BUSY … #define IDLE_STATUS_RXMAC_BUSY … #define IDLE_STATUS_MASK … /* MDIO Control Register */ #define REG_MDIO_CTRL … #define MDIO_CTRL_MODE_EXT … #define MDIO_CTRL_POST_READ … #define MDIO_CTRL_AP_EN … #define MDIO_CTRL_BUSY … #define MDIO_CTRL_CLK_SEL_MASK … #define MDIO_CTRL_CLK_SEL_SHIFT … #define MDIO_CTRL_CLK_25_4 … #define MDIO_CTRL_CLK_25_6 … #define MDIO_CTRL_CLK_25_8 … #define MDIO_CTRL_CLK_25_10 … #define MDIO_CTRL_CLK_25_32 … #define MDIO_CTRL_CLK_25_64 … #define MDIO_CTRL_CLK_25_128 … #define MDIO_CTRL_START … #define MDIO_CTRL_SPRES_PRMBL … #define MDIO_CTRL_OP_READ … #define MDIO_CTRL_REG_MASK … #define MDIO_CTRL_REG_SHIFT … #define MDIO_CTRL_DATA_MASK … #define MDIO_CTRL_DATA_SHIFT … #define MDIO_MAX_AC_TO … /* for extension reg access */ #define REG_MDIO_EXTN … #define MDIO_EXTN_PORTAD_MASK … #define MDIO_EXTN_PORTAD_SHIFT … #define MDIO_EXTN_DEVAD_MASK … #define MDIO_EXTN_DEVAD_SHIFT … #define MDIO_EXTN_REG_MASK … #define MDIO_EXTN_REG_SHIFT … /* BIST Control and Status Register0 (for the Packet Memory) */ #define REG_BIST0_CTRL … #define BIST0_NOW … #define BIST0_SRAM_FAIL … #define BIST0_FUSE_FLAG … /* BIST Control and Status Register1(for the retry buffer of PCI Express) */ #define REG_BIST1_CTRL … #define BIST1_NOW … #define BIST1_SRAM_FAIL … #define BIST1_FUSE_FLAG … /* SerDes Lock Detect Control and Status Register */ #define REG_SERDES … #define SERDES_PHY_CLK_SLOWDOWN … #define SERDES_MAC_CLK_SLOWDOWN … #define SERDES_SELFB_PLL_MASK … #define SERDES_SELFB_PLL_SHIFT … #define SERDES_PHYCLK_SEL_GTX … #define SERDES_PCIECLK_SEL_SRDS … #define SERDES_BUFS_RX_EN … #define SERDES_PD_RX … #define SERDES_PLL_EN … #define SERDES_EN … #define SERDES_SELFB_PLL_SEL_CSR … #define SERDES_SELFB_PLL_CSR_MASK … #define SERDES_SELFB_PLL_CSR_SHIFT … #define SERDES_SELFB_PLL_CSR_4 … #define SERDES_SELFB_PLL_CSR_0 … #define SERDES_SELFB_PLL_CSR_12 … #define SERDES_SELFB_PLL_CSR_18 … #define SERDES_VCO_SLOW … #define SERDES_VCO_FAST … #define SERDES_LOCK_DETECT_EN … #define SERDES_LOCK_DETECT … #define REG_LPI_DECISN_TIMER … #define L2CB_LPI_DESISN_TIMER … #define REG_LPI_CTRL … #define LPI_CTRL_CHK_DA … #define LPI_CTRL_ENH_TO_MASK … #define LPI_CTRL_ENH_TO_SHIFT … #define LPI_CTRL_ENH_TH_MASK … #define LPI_CTRL_ENH_TH_SHIFT … #define LPI_CTRL_ENH_EN … #define LPI_CTRL_CHK_RX … #define LPI_CTRL_CHK_STATE … #define LPI_CTRL_GMII … #define LPI_CTRL_TO_PHY … #define LPI_CTRL_EN … #define REG_LPI_WAIT … #define LPI_WAIT_TIMER_MASK … #define LPI_WAIT_TIMER_SHIFT … /* MAC Control Register */ #define REG_MAC_CTRL … #define MAC_CTRL_SPEED_MODE_SW … #define MAC_CTRL_HASH_ALG_CRC32 … #define MAC_CTRL_SINGLE_PAUSE_EN … #define MAC_CTRL_DBG … #define MAC_CTRL_BC_EN … #define MAC_CTRL_MC_ALL_EN … #define MAC_CTRL_RX_CHKSUM_EN … #define MAC_CTRL_TX_HUGE … #define MAC_CTRL_DBG_TX_BKPRESURE … #define MAC_CTRL_SPEED_MASK … #define MAC_CTRL_SPEED_SHIFT … #define MAC_CTRL_SPEED_10_100 … #define MAC_CTRL_SPEED_1000 … #define MAC_CTRL_TX_SIMURST … #define MAC_CTRL_SCNT … #define MAC_CTRL_TX_PAUSE … #define MAC_CTRL_PROMIS_EN … #define MAC_CTRL_RMV_VLAN … #define MAC_CTRL_PRMLEN_MASK … #define MAC_CTRL_PRMLEN_SHIFT … #define MAC_CTRL_HUGE_EN … #define MAC_CTRL_LENCHK … #define MAC_CTRL_PAD … #define MAC_CTRL_ADD_CRC … #define MAC_CTRL_DUPLX … #define MAC_CTRL_LOOPBACK … #define MAC_CTRL_RX_FLOW … #define MAC_CTRL_TX_FLOW … #define MAC_CTRL_RX_EN … #define MAC_CTRL_TX_EN … /* MAC IPG/IFG Control Register */ #define REG_MAC_IPG_IFG … #define MAC_IPG_IFG_IPGT_SHIFT … #define MAC_IPG_IFG_IPGT_MASK … #define MAC_IPG_IFG_MIFG_SHIFT … #define MAC_IPG_IFG_MIFG_MASK … #define MAC_IPG_IFG_IPGR1_SHIFT … #define MAC_IPG_IFG_IPGR1_MASK … #define MAC_IPG_IFG_IPGR2_SHIFT … #define MAC_IPG_IFG_IPGR2_MASK … /* MAC STATION ADDRESS */ #define REG_MAC_STA_ADDR … /* Hash table for multicast address */ #define REG_RX_HASH_TABLE … /* MAC Half-Duplex Control Register */ #define REG_MAC_HALF_DUPLX_CTRL … #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT … #define MAC_HALF_DUPLX_CTRL_LCOL_MASK … #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT … #define MAC_HALF_DUPLX_CTRL_RETRY_MASK … #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN … #define MAC_HALF_DUPLX_CTRL_NO_BACK_C … #define MAC_HALF_DUPLX_CTRL_NO_BACK_P … #define MAC_HALF_DUPLX_CTRL_ABEBE … #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT … #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK … #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT … #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK … /* Maximum Frame Length Control Register */ #define REG_MTU … /* Wake-On-Lan control register */ #define REG_WOL_CTRL … #define WOL_PT7_MATCH … #define WOL_PT6_MATCH … #define WOL_PT5_MATCH … #define WOL_PT4_MATCH … #define WOL_PT3_MATCH … #define WOL_PT2_MATCH … #define WOL_PT1_MATCH … #define WOL_PT0_MATCH … #define WOL_PT7_EN … #define WOL_PT6_EN … #define WOL_PT5_EN … #define WOL_PT4_EN … #define WOL_PT3_EN … #define WOL_PT2_EN … #define WOL_PT1_EN … #define WOL_PT0_EN … #define WOL_LNKCHG_ST … #define WOL_MAGIC_ST … #define WOL_PATTERN_ST … #define WOL_OOB_EN … #define WOL_LINK_CHG_PME_EN … #define WOL_LINK_CHG_EN … #define WOL_MAGIC_PME_EN … #define WOL_MAGIC_EN … #define WOL_PATTERN_PME_EN … #define WOL_PATTERN_EN … /* WOL Length ( 2 DWORD ) */ #define REG_WOL_PTLEN1 … #define WOL_PTLEN1_3_MASK … #define WOL_PTLEN1_3_SHIFT … #define WOL_PTLEN1_2_MASK … #define WOL_PTLEN1_2_SHIFT … #define WOL_PTLEN1_1_MASK … #define WOL_PTLEN1_1_SHIFT … #define WOL_PTLEN1_0_MASK … #define WOL_PTLEN1_0_SHIFT … #define REG_WOL_PTLEN2 … #define WOL_PTLEN2_7_MASK … #define WOL_PTLEN2_7_SHIFT … #define WOL_PTLEN2_6_MASK … #define WOL_PTLEN2_6_SHIFT … #define WOL_PTLEN2_5_MASK … #define WOL_PTLEN2_5_SHIFT … #define WOL_PTLEN2_4_MASK … #define WOL_PTLEN2_4_SHIFT … /* Internal SRAM Partition Register */ #define RFDX_HEAD_ADDR_MASK … #define RFDX_HARD_ADDR_SHIFT … #define RFDX_TAIL_ADDR_MASK … #define RFDX_TAIL_ADDR_SHIFT … #define REG_SRAM_RFD0_INFO … #define REG_SRAM_RFD1_INFO … #define REG_SRAM_RFD2_INFO … #define REG_SRAM_RFD3_INFO … #define REG_RFD_NIC_LEN … #define RFD_NIC_LEN_MASK … #define REG_SRAM_TRD_ADDR … #define TPD_HEAD_ADDR_MASK … #define TPD_HEAD_ADDR_SHIFT … #define TPD_TAIL_ADDR_MASK … #define TPD_TAIL_ADDR_SHIFT … #define REG_SRAM_TRD_LEN … #define TPD_NIC_LEN_MASK … #define REG_SRAM_RXF_ADDR … #define REG_SRAM_RXF_LEN … #define REG_SRAM_TXF_ADDR … #define REG_SRAM_TXF_LEN … #define REG_SRAM_TCPH_ADDR … #define REG_SRAM_PKTH_ADDR … /* * Load Ptr Register * Software sets this bit after the initialization of the head and tail */ #define REG_LOAD_PTR … /* * addresses of all descriptors, as well as the following descriptor * control register, which triggers each function block to load the head * pointer to prepare for the operation. This bit is then self-cleared * after one cycle. */ #define REG_RX_BASE_ADDR_HI … #define REG_TX_BASE_ADDR_HI … #define REG_RFD0_HEAD_ADDR_LO … #define REG_RFD1_HEAD_ADDR_LO … #define REG_RFD2_HEAD_ADDR_LO … #define REG_RFD3_HEAD_ADDR_LO … #define REG_RFD_RING_SIZE … #define RFD_RING_SIZE_MASK … #define REG_RX_BUF_SIZE … #define RX_BUF_SIZE_MASK … #define REG_RRD0_HEAD_ADDR_LO … #define REG_RRD1_HEAD_ADDR_LO … #define REG_RRD2_HEAD_ADDR_LO … #define REG_RRD3_HEAD_ADDR_LO … #define REG_RRD_RING_SIZE … #define RRD_RING_SIZE_MASK … #define REG_TPD_PRI1_ADDR_LO … #define REG_TPD_PRI0_ADDR_LO … #define REG_TPD_PRI2_ADDR_LO … #define REG_TPD_PRI3_ADDR_LO … #define REG_TPD_RING_SIZE … #define TPD_RING_SIZE_MASK … /* TXQ Control Register */ #define REG_TXQ_CTRL … #define TXQ_TXF_BURST_NUM_MASK … #define TXQ_TXF_BURST_NUM_SHIFT … #define L1C_TXQ_TXF_BURST_PREF … #define L2CB_TXQ_TXF_BURST_PREF … #define TXQ_CTRL_PEDING_CLR … #define TXQ_CTRL_LS_8023_EN … #define TXQ_CTRL_ENH_MODE … #define TXQ_CTRL_EN … #define TXQ_CTRL_IP_OPTION_EN … #define TXQ_NUM_TPD_BURST_MASK … #define TXQ_NUM_TPD_BURST_SHIFT … #define TXQ_NUM_TPD_BURST_DEF … #define TXQ_CFGV … #define L1C_TXQ_CFGV … #define L2CB_TXQ_CFGV … /* Jumbo packet Threshold for task offload */ #define REG_TX_TSO_OFFLOAD_THRESH … #define TX_TSO_OFFLOAD_THRESH_MASK … #define MAX_TSO_FRAME_SIZE … #define REG_TXF_WATER_MARK … #define TXF_WATER_MARK_MASK … #define TXF_LOW_WATER_MARK_SHIFT … #define TXF_HIGH_WATER_MARK_SHIFT … #define TXQ_CTRL_BURST_MODE_EN … #define REG_THRUPUT_MON_CTRL … #define THRUPUT_MON_RATE_MASK … #define THRUPUT_MON_RATE_SHIFT … #define THRUPUT_MON_EN … /* RXQ Control Register */ #define REG_RXQ_CTRL … #define ASPM_THRUPUT_LIMIT_MASK … #define ASPM_THRUPUT_LIMIT_SHIFT … #define ASPM_THRUPUT_LIMIT_NO … #define ASPM_THRUPUT_LIMIT_1M … #define ASPM_THRUPUT_LIMIT_10M … #define ASPM_THRUPUT_LIMIT_100M … #define IPV6_CHKSUM_CTRL_EN … #define RXQ_RFD_BURST_NUM_MASK … #define RXQ_RFD_BURST_NUM_SHIFT … #define RXQ_NUM_RFD_PREF_DEF … #define RSS_MODE_MASK … #define RSS_MODE_SHIFT … #define RSS_MODE_DIS … #define RSS_MODE_SQSI … #define RSS_MODE_MQSI … #define RSS_MODE_MQMI … #define RSS_NIP_QUEUE_SEL … #define RRS_HASH_CTRL_EN … #define RX_CUT_THRU_EN … #define RXQ_CTRL_EN … #define REG_RFD_FREE_THRESH … #define RFD_FREE_THRESH_MASK … #define RFD_FREE_HI_THRESH_SHIFT … #define RFD_FREE_LO_THRESH_SHIFT … /* RXF flow control register */ #define REG_RXQ_RXF_PAUSE_THRESH … #define RXQ_RXF_PAUSE_TH_HI_SHIFT … #define RXQ_RXF_PAUSE_TH_HI_MASK … #define RXQ_RXF_PAUSE_TH_LO_SHIFT … #define RXQ_RXF_PAUSE_TH_LO_MASK … #define REG_RXD_DMA_CTRL … #define RXD_DMA_THRESH_MASK … #define RXD_DMA_THRESH_SHIFT … #define RXD_DMA_DOWN_TIMER_MASK … #define RXD_DMA_DOWN_TIMER_SHIFT … /* DMA Engine Control Register */ #define REG_DMA_CTRL … #define DMA_CTRL_SMB_NOW … #define DMA_CTRL_WPEND_CLR … #define DMA_CTRL_RPEND_CLR … #define DMA_CTRL_WDLY_CNT_MASK … #define DMA_CTRL_WDLY_CNT_SHIFT … #define DMA_CTRL_WDLY_CNT_DEF … #define DMA_CTRL_RDLY_CNT_MASK … #define DMA_CTRL_RDLY_CNT_SHIFT … #define DMA_CTRL_RDLY_CNT_DEF … #define DMA_CTRL_RREQ_PRI_DATA … #define DMA_CTRL_WREQ_BLEN_MASK … #define DMA_CTRL_WREQ_BLEN_SHIFT … #define DMA_CTRL_RREQ_BLEN_MASK … #define DMA_CTRL_RREQ_BLEN_SHIFT … #define L1C_CTRL_DMA_RCB_LEN128 … #define DMA_CTRL_RORDER_MODE_MASK … #define DMA_CTRL_RORDER_MODE_SHIFT … #define DMA_CTRL_RORDER_MODE_OUT … #define DMA_CTRL_RORDER_MODE_ENHANCE … #define DMA_CTRL_RORDER_MODE_IN … /* INT-triggle/SMB Control Register */ #define REG_SMB_STAT_TIMER … #define SMB_STAT_TIMER_MASK … #define REG_TINT_TPD_THRESH … /* Mail box */ #define MB_RFDX_PROD_IDX_MASK … #define REG_MB_RFD0_PROD_IDX … #define REG_MB_RFD1_PROD_IDX … #define REG_MB_RFD2_PROD_IDX … #define REG_MB_RFD3_PROD_IDX … #define REG_TPD_PRI1_PIDX … #define REG_TPD_PRI0_PIDX … #define REG_TPD_PRI1_CIDX … #define REG_TPD_PRI0_CIDX … #define REG_TPD_PRI3_PIDX … #define REG_TPD_PRI2_PIDX … #define REG_TPD_PRI3_CIDX … #define REG_TPD_PRI2_CIDX … #define REG_MB_RFD01_CONS_IDX … #define MB_RFD0_CONS_IDX_MASK … #define MB_RFD1_CONS_IDX_MASK … #define REG_MB_RFD23_CONS_IDX … #define MB_RFD2_CONS_IDX_MASK … #define MB_RFD3_CONS_IDX_MASK … /* Interrupt Status Register */ #define REG_ISR … #define ISR_SMB … #define ISR_TIMER … /* * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set * in Table 51 Selene Master Control Register (Offset 0x1400). */ #define ISR_MANUAL … #define ISR_HW_RXF_OV … #define ISR_RFD0_UR … #define ISR_RFD1_UR … #define ISR_RFD2_UR … #define ISR_RFD3_UR … #define ISR_TXF_UR … #define ISR_DMAR_TO_RST … #define ISR_DMAW_TO_RST … #define ISR_TX_CREDIT … #define ISR_GPHY … /* GPHY low power state interrupt */ #define ISR_GPHY_LPW … #define ISR_TXQ_TO_RST … #define ISR_TX_PKT_0 … #define ISR_RX_PKT_0 … #define ISR_RX_PKT_1 … #define ISR_RX_PKT_2 … #define ISR_RX_PKT_3 … #define ISR_MAC_RX … #define ISR_MAC_TX … #define ISR_UR_DETECTED … #define ISR_FERR_DETECTED … #define ISR_NFERR_DETECTED … #define ISR_CERR_DETECTED … #define ISR_PHY_LINKDOWN … #define ISR_TX_PKT_1 … #define ISR_TX_PKT_2 … #define ISR_TX_PKT_3 … #define ISR_DIS_INT … /* Interrupt Mask Register */ #define REG_IMR … #define IMR_NORMAL_MASK … #define ISR_TX_PKT … #define ISR_RX_PKT … #define ISR_OVER … #define ISR_ERROR … #define REG_INT_RETRIG_TIMER … #define INT_RETRIG_TIMER_MASK … #define REG_MAC_RX_STATUS_BIN … #define REG_MAC_RX_STATUS_END … #define REG_MAC_TX_STATUS_BIN … #define REG_MAC_TX_STATUS_END … #define REG_CLK_GATING_CTRL … #define CLK_GATING_DMAW_EN … #define CLK_GATING_DMAR_EN … #define CLK_GATING_TXQ_EN … #define CLK_GATING_RXQ_EN … #define CLK_GATING_TXMAC_EN … #define CLK_GATING_RXMAC_EN … #define CLK_GATING_EN_ALL … /* DEBUG ADDR */ #define REG_DEBUG_DATA0 … #define REG_DEBUG_DATA1 … #define REG_MT_MAGIC … #define REG_MT_MODE … #define REG_MT_SPEED … #define REG_MT_VERSION … #define MT_MAGIC … #define MT_MODE_4Q … #define L1D_MPW_PHYID1 … #define L1D_MPW_PHYID2 … #define L1D_MPW_PHYID3 … /* Autoneg Advertisement Register */ #define ADVERTISE_DEFAULT_CAP … /* 1000BASE-T Control Register */ #define GIGA_CR_1000T_REPEATER_DTE … #define GIGA_CR_1000T_MS_VALUE … #define GIGA_CR_1000T_MS_ENABLE … #define GIGA_CR_1000T_TEST_MODE_NORMAL … #define GIGA_CR_1000T_TEST_MODE_1 … #define GIGA_CR_1000T_TEST_MODE_2 … #define GIGA_CR_1000T_TEST_MODE_3 … #define GIGA_CR_1000T_TEST_MODE_4 … #define GIGA_CR_1000T_SPEED_MASK … #define GIGA_CR_1000T_DEFAULT_CAP … /* PHY Specific Status Register */ #define MII_GIGA_PSSR … #define GIGA_PSSR_SPD_DPLX_RESOLVED … #define GIGA_PSSR_DPLX … #define GIGA_PSSR_SPEED … #define GIGA_PSSR_10MBS … #define GIGA_PSSR_100MBS … #define GIGA_PSSR_1000MBS … /* PHY Interrupt Enable Register */ #define MII_IER … #define IER_LINK_UP … #define IER_LINK_DOWN … /* PHY Interrupt Status Register */ #define MII_ISR … #define ISR_LINK_UP … #define ISR_LINK_DOWN … /* Cable-Detect-Test Control Register */ #define MII_CDTC … #define CDTC_EN_OFF … #define CDTC_EN_BITS … #define CDTC_PAIR_OFF … #define CDTC_PAIR_BIT … /* Cable-Detect-Test Status Register */ #define MII_CDTS … #define CDTS_STATUS_OFF … #define CDTS_STATUS_BITS … #define CDTS_STATUS_NORMAL … #define CDTS_STATUS_SHORT … #define CDTS_STATUS_OPEN … #define CDTS_STATUS_INVALID … #define MII_DBG_ADDR … #define MII_DBG_DATA … /***************************** debug port *************************************/ #define MIIDBG_ANACTRL … #define ANACTRL_CLK125M_DELAY_EN … #define ANACTRL_VCO_FAST … #define ANACTRL_VCO_SLOW … #define ANACTRL_AFE_MODE_EN … #define ANACTRL_LCKDET_PHY … #define ANACTRL_LCKDET_EN … #define ANACTRL_OEN_125M … #define ANACTRL_HBIAS_EN … #define ANACTRL_HB_EN … #define ANACTRL_SEL_HSP … #define ANACTRL_CLASSA_EN … #define ANACTRL_MANUSWON_SWR_MASK … #define ANACTRL_MANUSWON_SWR_SHIFT … #define ANACTRL_MANUSWON_SWR_2V … #define ANACTRL_MANUSWON_SWR_1P9V … #define ANACTRL_MANUSWON_SWR_1P8V … #define ANACTRL_MANUSWON_SWR_1P7V … #define ANACTRL_MANUSWON_BW3_4M … #define ANACTRL_RESTART_CAL … #define ANACTRL_DEF … #define MIIDBG_SYSMODCTRL … #define SYSMODCTRL_IECHOADJ_PFMH_PHY … #define SYSMODCTRL_IECHOADJ_BIASGEN … #define SYSMODCTRL_IECHOADJ_PFML_PHY … #define SYSMODCTRL_IECHOADJ_PS_MASK … #define SYSMODCTRL_IECHOADJ_PS_SHIFT … #define SYSMODCTRL_IECHOADJ_PS_40 … #define SYSMODCTRL_IECHOADJ_PS_20 … #define SYSMODCTRL_IECHOADJ_PS_0 … #define SYSMODCTRL_IECHOADJ_10BT_100MV … #define SYSMODCTRL_IECHOADJ_HLFAP_MASK … #define SYSMODCTRL_IECHOADJ_HLFAP_SHIFT … #define SYSMODCTRL_IECHOADJ_VDFULBW … #define SYSMODCTRL_IECHOADJ_VDBIASHLF … #define SYSMODCTRL_IECHOADJ_VDAMPHLF … #define SYSMODCTRL_IECHOADJ_VDLANSW … #define SYSMODCTRL_IECHOADJ_DEF … /* for l1d & l2cb */ #define SYSMODCTRL_IECHOADJ_CUR_ADD … #define SYSMODCTRL_IECHOADJ_CUR_MASK … #define SYSMODCTRL_IECHOADJ_CUR_SHIFT … #define SYSMODCTRL_IECHOADJ_VOL_MASK … #define SYSMODCTRL_IECHOADJ_VOL_SHIFT … #define SYSMODCTRL_IECHOADJ_VOL_17ALL … #define SYSMODCTRL_IECHOADJ_VOL_100M15 … #define SYSMODCTRL_IECHOADJ_VOL_10M17 … #define SYSMODCTRL_IECHOADJ_BIAS1_MASK … #define SYSMODCTRL_IECHOADJ_BIAS1_SHIFT … #define SYSMODCTRL_IECHOADJ_BIAS2_MASK … #define SYSMODCTRL_IECHOADJ_BIAS2_SHIFT … #define L1D_SYSMODCTRL_IECHOADJ_DEF … #define MIIDBG_SRDSYSMOD … #define SRDSYSMOD_LCKDET_EN … #define SRDSYSMOD_PLL_EN … #define SRDSYSMOD_SEL_HSP … #define SRDSYSMOD_HLFTXDR … #define SRDSYSMOD_TXCLK_DELAY_EN … #define SRDSYSMOD_TXELECIDLE … #define SRDSYSMOD_DEEMP_EN … #define SRDSYSMOD_MS_PAD … #define SRDSYSMOD_CDR_ADC_VLTG … #define SRDSYSMOD_CDR_DAC_1MA … #define SRDSYSMOD_DEF … #define MIIDBG_CFGLPSPD … #define CFGLPSPD_RSTCNT_MASK … #define CFGLPSPD_RSTCNT_SHIFT … #define CFGLPSPD_RSTCNT_CLK125SW … #define MIIDBG_HIBNEG … #define HIBNEG_PSHIB_EN … #define HIBNEG_WAKE_BOTH … #define HIBNEG_ONOFF_ANACHG_SUDEN … #define HIBNEG_HIB_PULSE … #define HIBNEG_GATE_25M_EN … #define HIBNEG_RST_80U … #define HIBNEG_RST_TIMER_MASK … #define HIBNEG_RST_TIMER_SHIFT … #define HIBNEG_GTX_CLK_DELAY_MASK … #define HIBNEG_GTX_CLK_DELAY_SHIFT … #define HIBNEG_BYPSS_BRKTIMER … #define HIBNEG_DEF … #define MIIDBG_TST10BTCFG … #define TST10BTCFG_INTV_TIMER_MASK … #define TST10BTCFG_INTV_TIMER_SHIFT … #define TST10BTCFG_TRIGER_TIMER_MASK … #define TST10BTCFG_TRIGER_TIMER_SHIFT … #define TST10BTCFG_DIV_MAN_MLT3_EN … #define TST10BTCFG_OFF_DAC_IDLE … #define TST10BTCFG_LPBK_DEEP … #define TST10BTCFG_DEF … #define MIIDBG_AZ_ANADECT … #define AZ_ANADECT_10BTRX_TH … #define AZ_ANADECT_BOTH_01CHNL … #define AZ_ANADECT_INTV_MASK … #define AZ_ANADECT_INTV_SHIFT … #define AZ_ANADECT_THRESH_MASK … #define AZ_ANADECT_THRESH_SHIFT … #define AZ_ANADECT_CHNL_MASK … #define AZ_ANADECT_CHNL_SHIFT … #define AZ_ANADECT_DEF … #define AZ_ANADECT_LONG … #define MIIDBG_MSE16DB … #define L1D_MSE16DB_UP … #define L1D_MSE16DB_DOWN … #define MIIDBG_LEGCYPS … #define LEGCYPS_EN … #define LEGCYPS_DAC_AMP1000_MASK … #define LEGCYPS_DAC_AMP1000_SHIFT … #define LEGCYPS_DAC_AMP100_MASK … #define LEGCYPS_DAC_AMP100_SHIFT … #define LEGCYPS_DAC_AMP10_MASK … #define LEGCYPS_DAC_AMP10_SHIFT … #define LEGCYPS_UNPLUG_TIMER_MASK … #define LEGCYPS_UNPLUG_TIMER_SHIFT … #define LEGCYPS_UNPLUG_DECT_EN … #define LEGCYPS_ECNC_PS_EN … #define L1D_LEGCYPS_DEF … #define L1C_LEGCYPS_DEF … #define MIIDBG_TST100BTCFG … #define TST100BTCFG_NORMAL_BW_EN … #define TST100BTCFG_BADLNK_BYPASS … #define TST100BTCFG_SHORTCABL_TH_MASK … #define TST100BTCFG_SHORTCABL_TH_SHIFT … #define TST100BTCFG_LITCH_EN … #define TST100BTCFG_VLT_SW … #define TST100BTCFG_LONGCABL_TH_MASK … #define TST100BTCFG_LONGCABL_TH_SHIFT … #define TST100BTCFG_DEF … #define MIIDBG_VOLT_CTRL … #define VOLT_CTRL_CABLE1TH_MASK … #define VOLT_CTRL_CABLE1TH_SHIFT … #define VOLT_CTRL_AMPCTRL_MASK … #define VOLT_CTRL_AMPCTRL_SHIFT … #define VOLT_CTRL_SW_BYPASS … #define VOLT_CTRL_SWLOWEST … #define VOLT_CTRL_DACAMP10_MASK … #define VOLT_CTRL_DACAMP10_SHIFT … #define MIIDBG_CABLE1TH_DET … #define CABLE1TH_DET_EN … /******* dev 3 *********/ #define MIIEXT_PCS … #define MIIEXT_CLDCTRL3 … #define CLDCTRL3_BP_CABLE1TH_DET_GT … #define CLDCTRL3_AZ_DISAMP … #define L2CB_CLDCTRL3 … #define L1D_CLDCTRL3 … #define MIIEXT_CLDCTRL6 … #define CLDCTRL6_CAB_LEN_MASK … #define CLDCTRL6_CAB_LEN_SHIFT … #define CLDCTRL6_CAB_LEN_SHORT … /********* dev 7 **********/ #define MIIEXT_ANEG … #define MIIEXT_LOCAL_EEEADV … #define LOCAL_EEEADV_1000BT … #define LOCAL_EEEADV_100BT … #define MIIEXT_REMOTE_EEEADV … #define REMOTE_EEEADV_1000BT … #define REMOTE_EEEADV_100BT … #define MIIEXT_EEE_ANEG … #define EEE_ANEG_1000M … #define EEE_ANEG_100M … #endif /*_ATL1C_HW_H_*/
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