/* bnx2x_init.h: Qlogic Everest network driver. * Structures and macroes needed during the initialization. * * Copyright (c) 2007-2013 Broadcom Corporation * Copyright (c) 2014 QLogic Corporation All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. * * Maintained by: Ariel Elior <[email protected]> * Written by: Eliezer Tamir * Modified by: Vladislav Zolotarov */ #ifndef BNX2X_INIT_H #define BNX2X_INIT_H /* Init operation types and structures */ enum { … }; enum { … }; /* Returns the index of start or end of a specific block stage in ops array*/ #define BLOCK_OPS_IDX(block, stage, end) … /* structs for the various opcodes */ struct raw_op { … }; struct op_read { … }; struct op_write { … }; struct op_arr_write { … }; struct op_zero { … }; struct op_if_mode { … }; init_op; /* Init Phases */ enum { … }; /* Init Modes */ enum { … }; /* Init Blocks */ enum { … }; /* QM queue numbers */ #define BNX2X_ETH_Q … #define BNX2X_TOE_Q … #define BNX2X_TOE_ACK_Q … #define BNX2X_ISCSI_Q … #define BNX2X_ISCSI_ACK_Q … #define BNX2X_FCOE_Q … /* Vnics per mode */ #define BNX2X_PORT2_MODE_NUM_VNICS … #define BNX2X_PORT4_MODE_NUM_VNICS … /* COS offset for port1 in E3 B0 4port mode */ #define BNX2X_E3B0_PORT1_COS_OFFSET … /* QM Register addresses */ #define BNX2X_Q_VOQ_REG_ADDR(pf_q_num) … #define BNX2X_VOQ_Q_REG_ADDR(cos, pf_q_num) … #define BNX2X_Q_CMDQ_REG_ADDR(pf_q_num) … /* extracts the QM queue number for the specified port and vnic */ #define BNX2X_PF_Q_NUM(q_num, port, vnic) … /* Maps the specified queue to the specified COS */ static inline void bnx2x_map_q_cos(struct bnx2x *bp, u32 q_num, u32 new_cos) { … } /* Configures the QM according to the specified per-traffic-type COSes */ static inline void bnx2x_dcb_config_qm(struct bnx2x *bp, enum cos_mode mode, struct priority_cos *traffic_cos) { … } /* congestion management port init api description * the api works as follows: * the driver should pass the cmng_init_input struct, the port_init function * will prepare the required internal ram structure which will be passed back * to the driver (cmng_init) that will write it into the internal ram. * * IMPORTANT REMARKS: * 1. the cmng_init struct does not represent the contiguous internal ram * structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET * offset in order to write the port sub struct and the * PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other * words - don't use memcpy!). * 2. although the cmng_init struct is filled for the maximal vnic number * possible, the driver should only write the valid vnics into the internal * ram according to the appropriate port mode. */ /* CMNG constants, as derived from system spec calculations */ /* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */ #define DEF_MIN_RATE … /* resolution of the rate shaping timer - 400 usec */ #define RS_PERIODIC_TIMEOUT_USEC … /* number of bytes in single QM arbitration cycle - * coefficient for calculating the fairness timer */ #define QM_ARB_BYTES … /* resolution of Min algorithm 1:100 */ #define MIN_RES … /* how many bytes above threshold for * the minimal credit of Min algorithm */ #define MIN_ABOVE_THRESH … /* Fairness algorithm integration time coefficient - * for calculating the actual Tfair */ #define T_FAIR_COEF … /* Memory of fairness algorithm - 2 cycles */ #define FAIR_MEM … #define SAFC_TIMEOUT_USEC … #define SDM_TICKS … static inline void bnx2x_init_max(const struct cmng_init_input *input_data, u32 r_param, struct cmng_init *ram_data) { … } static inline void bnx2x_init_min(const struct cmng_init_input *input_data, u32 r_param, struct cmng_init *ram_data) { … } static inline void bnx2x_init_fw_wrr(const struct cmng_init_input *input_data, u32 r_param, struct cmng_init *ram_data) { … } static inline void bnx2x_init_safc(const struct cmng_init_input *input_data, struct cmng_init *ram_data) { … } /* Congestion management port init */ static inline void bnx2x_init_cmng(const struct cmng_init_input *input_data, struct cmng_init *ram_data) { … } /* Returns the index of start or end of a specific block stage in ops array */ #define BLOCK_OPS_IDX(block, stage, end) … #define INITOP_SET … #define INITOP_CLEAR … #define INITOP_INIT … /**************************************************************************** * ILT management ****************************************************************************/ struct ilt_line { … }; struct ilt_client_info { … }; struct bnx2x_ilt { … }; /**************************************************************************** * SRC configuration ****************************************************************************/ struct src_ent { … }; /**************************************************************************** * Parity configuration ****************************************************************************/ #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) … #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) … #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) … static const struct { … } bnx2x_blocks_parity_data[] = …; /* [28] MCP Latched rom_parity * [29] MCP Latched ump_rx_parity * [30] MCP Latched ump_tx_parity * [31] MCP Latched scpad_parity */ #define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS … #define MISC_AEU_ENABLE_MCP_PRTY_BITS … /* Below registers control the MCP parity attention output. When * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are * enabled, when cleared - disabled. */ static const struct { … } mcp_attn_ctl_regs[] = …; static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable) { … } static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx) { … } static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp) { … } /* Clear the parity error status registers. */ static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp) { … } static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp) { … } #endif /* BNX2X_INIT_H */
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