/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _B44_H #define _B44_H #include <linux/brcmphy.h> /* Register layout. (These correspond to struct _bcmenettregs in bcm4400.) */ #define B44_DEVCTRL … #define DEVCTRL_MPM … #define DEVCTRL_PFE … #define DEVCTRL_IPP … #define DEVCTRL_EPR … #define DEVCTRL_PME … #define DEVCTRL_PMCE … #define DEVCTRL_PADDR … #define DEVCTRL_PADDR_SHIFT … #define B44_BIST_STAT … #define B44_WKUP_LEN … #define WKUP_LEN_P0_MASK … #define WKUP_LEN_D0 … #define WKUP_LEN_P1_MASK … #define WKUP_LEN_P1_SHIFT … #define WKUP_LEN_D1 … #define WKUP_LEN_P2_MASK … #define WKUP_LEN_P2_SHIFT … #define WKUP_LEN_D2 … #define WKUP_LEN_P3_MASK … #define WKUP_LEN_P3_SHIFT … #define WKUP_LEN_D3 … #define WKUP_LEN_DISABLE … #define WKUP_LEN_ENABLE_TWO … #define WKUP_LEN_ENABLE_THREE … #define B44_ISTAT … #define ISTAT_LS … #define ISTAT_PME … #define ISTAT_TO … #define ISTAT_DSCE … #define ISTAT_DATAE … #define ISTAT_DPE … #define ISTAT_RDU … #define ISTAT_RFO … #define ISTAT_TFU … #define ISTAT_RX … #define ISTAT_TX … #define ISTAT_EMAC … #define ISTAT_MII_WRITE … #define ISTAT_MII_READ … #define ISTAT_ERRORS … #define B44_IMASK … #define IMASK_DEF … #define B44_GPTIMER … #define B44_ADDR_LO … #define B44_ADDR_HI … #define B44_FILT_ADDR … #define B44_FILT_DATA … #define B44_TXBURST … #define B44_RXBURST … #define B44_MAC_CTRL … #define MAC_CTRL_CRC32_ENAB … #define MAC_CTRL_PHY_PDOWN … #define MAC_CTRL_PHY_EDET … #define MAC_CTRL_PHY_LEDCTRL … #define MAC_CTRL_PHY_LEDCTRL_SHIFT … #define B44_MAC_FLOW … #define MAC_FLOW_RX_HI_WATER … #define MAC_FLOW_PAUSE_ENAB … #define B44_RCV_LAZY … #define RCV_LAZY_TO_MASK … #define RCV_LAZY_FC_MASK … #define RCV_LAZY_FC_SHIFT … #define B44_DMATX_CTRL … #define DMATX_CTRL_ENABLE … #define DMATX_CTRL_SUSPEND … #define DMATX_CTRL_LPBACK … #define DMATX_CTRL_FAIRPRIOR … #define DMATX_CTRL_FLUSH … #define B44_DMATX_ADDR … #define B44_DMATX_PTR … #define B44_DMATX_STAT … #define DMATX_STAT_CDMASK … #define DMATX_STAT_SMASK … #define DMATX_STAT_SDISABLED … #define DMATX_STAT_SACTIVE … #define DMATX_STAT_SIDLE … #define DMATX_STAT_SSTOPPED … #define DMATX_STAT_SSUSP … #define DMATX_STAT_EMASK … #define DMATX_STAT_ENONE … #define DMATX_STAT_EDPE … #define DMATX_STAT_EDFU … #define DMATX_STAT_EBEBR … #define DMATX_STAT_EBEDA … #define DMATX_STAT_FLUSHED … #define B44_DMARX_CTRL … #define DMARX_CTRL_ENABLE … #define DMARX_CTRL_ROMASK … #define DMARX_CTRL_ROSHIFT … #define B44_DMARX_ADDR … #define B44_DMARX_PTR … #define B44_DMARX_STAT … #define DMARX_STAT_CDMASK … #define DMARX_STAT_SMASK … #define DMARX_STAT_SDISABLED … #define DMARX_STAT_SACTIVE … #define DMARX_STAT_SIDLE … #define DMARX_STAT_SSTOPPED … #define DMARX_STAT_EMASK … #define DMARX_STAT_ENONE … #define DMARX_STAT_EDPE … #define DMARX_STAT_EDFO … #define DMARX_STAT_EBEBW … #define DMARX_STAT_EBEDA … #define B44_DMAFIFO_AD … #define DMAFIFO_AD_OMASK … #define DMAFIFO_AD_SMASK … #define DMAFIFO_AD_SXDD … #define DMAFIFO_AD_SXDP … #define DMAFIFO_AD_SRDD … #define DMAFIFO_AD_SRDP … #define DMAFIFO_AD_SXFD … #define DMAFIFO_AD_SXFP … #define DMAFIFO_AD_SRFD … #define DMAFIFO_AD_SRFP … #define B44_DMAFIFO_LO … #define B44_DMAFIFO_HI … #define B44_RXCONFIG … #define RXCONFIG_DBCAST … #define RXCONFIG_ALLMULTI … #define RXCONFIG_NORX_WHILE_TX … #define RXCONFIG_PROMISC … #define RXCONFIG_LPBACK … #define RXCONFIG_FLOW … #define RXCONFIG_FLOW_ACCEPT … #define RXCONFIG_RFILT … #define RXCONFIG_CAM_ABSENT … #define B44_RXMAXLEN … #define B44_TXMAXLEN … #define B44_MDIO_CTRL … #define MDIO_CTRL_MAXF_MASK … #define MDIO_CTRL_PREAMBLE … #define B44_MDIO_DATA … #define MDIO_DATA_DATA … #define MDIO_DATA_TA_MASK … #define MDIO_DATA_TA_SHIFT … #define MDIO_TA_VALID … #define MDIO_DATA_RA_MASK … #define MDIO_DATA_RA_SHIFT … #define MDIO_DATA_PMD_MASK … #define MDIO_DATA_PMD_SHIFT … #define MDIO_DATA_OP_MASK … #define MDIO_DATA_OP_SHIFT … #define MDIO_OP_WRITE … #define MDIO_OP_READ … #define MDIO_DATA_SB_MASK … #define MDIO_DATA_SB_SHIFT … #define MDIO_DATA_SB_START … #define B44_EMAC_IMASK … #define B44_EMAC_ISTAT … #define EMAC_INT_MII … #define EMAC_INT_MIB … #define EMAC_INT_FLOW … #define B44_CAM_DATA_LO … #define B44_CAM_DATA_HI … #define CAM_DATA_HI_VALID … #define B44_CAM_CTRL … #define CAM_CTRL_ENABLE … #define CAM_CTRL_MSEL … #define CAM_CTRL_READ … #define CAM_CTRL_WRITE … #define CAM_CTRL_INDEX_MASK … #define CAM_CTRL_INDEX_SHIFT … #define CAM_CTRL_BUSY … #define B44_ENET_CTRL … #define ENET_CTRL_ENABLE … #define ENET_CTRL_DISABLE … #define ENET_CTRL_SRST … #define ENET_CTRL_EPSEL … #define B44_TX_CTRL … #define TX_CTRL_DUPLEX … #define TX_CTRL_FMODE … #define TX_CTRL_SBENAB … #define TX_CTRL_SMALL_SLOT … #define B44_TX_WMARK … #define B44_MIB_CTRL … #define MIB_CTRL_CLR_ON_READ … #define B44_TX_GOOD_O … #define B44_TX_GOOD_P … #define B44_TX_O … #define B44_TX_P … #define B44_TX_BCAST … #define B44_TX_MCAST … #define B44_TX_64 … #define B44_TX_65_127 … #define B44_TX_128_255 … #define B44_TX_256_511 … #define B44_TX_512_1023 … #define B44_TX_1024_MAX … #define B44_TX_JABBER … #define B44_TX_OSIZE … #define B44_TX_FRAG … #define B44_TX_URUNS … #define B44_TX_TCOLS … #define B44_TX_SCOLS … #define B44_TX_MCOLS … #define B44_TX_ECOLS … #define B44_TX_LCOLS … #define B44_TX_DEFERED … #define B44_TX_CLOST … #define B44_TX_PAUSE … #define B44_RX_GOOD_O … #define B44_RX_GOOD_P … #define B44_RX_O … #define B44_RX_P … #define B44_RX_BCAST … #define B44_RX_MCAST … #define B44_RX_64 … #define B44_RX_65_127 … #define B44_RX_128_255 … #define B44_RX_256_511 … #define B44_RX_512_1023 … #define B44_RX_1024_MAX … #define B44_RX_JABBER … #define B44_RX_OSIZE … #define B44_RX_FRAG … #define B44_RX_MISS … #define B44_RX_CRCA … #define B44_RX_USIZE … #define B44_RX_CRC … #define B44_RX_ALIGN … #define B44_RX_SYM … #define B44_RX_PAUSE … #define B44_RX_NPAUSE … /* 4400 PHY registers */ #define B44_MII_AUXCTRL … #define MII_AUXCTRL_DUPLEX … #define MII_AUXCTRL_SPEED … #define MII_AUXCTRL_FORCED … #define B44_MII_ALEDCTRL … #define MII_ALEDCTRL_ALLMSK … #define B44_MII_TLEDCTRL … #define MII_TLEDCTRL_ENABLE … struct dma_desc { … }; /* There are only 12 bits in the DMA engine for descriptor offsetting * so the table must be aligned on a boundary of this. */ #define DMA_TABLE_BYTES … #define DESC_CTRL_LEN … #define DESC_CTRL_CMASK … #define DESC_CTRL_EOT … #define DESC_CTRL_IOC … #define DESC_CTRL_EOF … #define DESC_CTRL_SOF … #define RX_COPY_THRESHOLD … struct rx_header { … }; #define RX_HEADER_LEN … #define RX_FLAG_OFIFO … #define RX_FLAG_CRCERR … #define RX_FLAG_SERR … #define RX_FLAG_ODD … #define RX_FLAG_LARGE … #define RX_FLAG_MCAST … #define RX_FLAG_BCAST … #define RX_FLAG_MISS … #define RX_FLAG_LAST … #define RX_FLAG_ERRORS … struct ring_info { … }; #define B44_MCAST_TABLE_SIZE … /* no local phy regs, e.g: Broadcom switches pseudo-PHY */ #define B44_PHY_ADDR_NO_LOCAL_PHY … /* no phy present at all */ #define B44_PHY_ADDR_NO_PHY … #define B44_MDC_RATIO … #define B44_STAT_REG_DECLARE … /* SW copy of device statistics, kept up to date by periodic timer * which probes HW values. Check b44_stats_update if you mess with * the layout */ struct b44_hw_stats { … }; #define B44_BOARDFLAG_ROBO … #define B44_BOARDFLAG_ADM … struct ssb_device; struct b44 { … }; #endif /* _B44_H */
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