/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __BCM4908_ENET_H #define __BCM4908_ENET_H #define ENET_CONTROL … #define ENET_MIB_CTRL … #define ENET_MIB_CTRL_CLR_MIB … #define ENET_RX_ERR_MASK … #define ENET_MIB_MAX_PKT_SIZE … #define ENET_MIB_MAX_PKT_SIZE_VAL … #define ENET_DIAG_OUT … #define ENET_ENABLE_DROP_PKT … #define ENET_IRQ_ENABLE … #define ENET_IRQ_ENABLE_OVFL … #define ENET_GMAC_STATUS … #define ENET_GMAC_STATUS_ETH_SPEED_MASK … #define ENET_GMAC_STATUS_ETH_SPEED_10 … #define ENET_GMAC_STATUS_ETH_SPEED_100 … #define ENET_GMAC_STATUS_ETH_SPEED_1000 … #define ENET_GMAC_STATUS_HD … #define ENET_GMAC_STATUS_AUTO_CFG_EN … #define ENET_GMAC_STATUS_LINK_UP … #define ENET_IRQ_STATUS … #define ENET_IRQ_STATUS_OVFL … #define ENET_OVERFLOW_COUNTER … #define ENET_FLUSH … #define ENET_FLUSH_RXFIFO_FLUSH … #define ENET_FLUSH_TXFIFO_FLUSH … #define ENET_RSV_SELECT … #define ENET_BP_FORCE … #define ENET_BP_FORCE_FORCE … #define ENET_DMA_RX_OK_TO_SEND_COUNT … #define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL … #define ENET_TX_CRC_CTRL … #define ENET_MIB … #define ENET_UNIMAC … #define ENET_DMA … #define ENET_DMA_CONTROLLER_CFG … #define ENET_DMA_CTRL_CFG_MASTER_EN … #define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN … #define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN … #define ENET_DMA_FLOWCTL_CH1_THRESH_LO … #define ENET_DMA_FLOWCTL_CH1_THRESH_HI … #define ENET_DMA_FLOWCTL_CH1_ALLOC … #define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE … #define ENET_DMA_FLOWCTL_CH3_THRESH_LO … #define ENET_DMA_FLOWCTL_CH3_THRESH_HI … #define ENET_DMA_FLOWCTL_CH3_ALLOC … #define ENET_DMA_FLOWCTL_CH5_THRESH_LO … #define ENET_DMA_FLOWCTL_CH5_THRESH_HI … #define ENET_DMA_FLOWCTL_CH5_ALLOC … #define ENET_DMA_FLOWCTL_CH7_THRESH_LO … #define ENET_DMA_FLOWCTL_CH7_THRESH_HI … #define ENET_DMA_FLOWCTL_CH7_ALLOC … #define ENET_DMA_CTRL_CHANNEL_RESET … #define ENET_DMA_CTRL_CHANNEL_DEBUG … #define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS … #define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK … #define ENET_DMA_CH0_CFG … #define ENET_DMA_CH1_CFG … #define ENET_DMA_CH0_STATE_RAM … #define ENET_DMA_CH1_STATE_RAM … #define ENET_DMA_CH_CFG … #define ENET_DMA_CH_CFG_ENABLE … #define ENET_DMA_CH_CFG_PKT_HALT … #define ENET_DMA_CH_CFG_BURST_HALT … #define ENET_DMA_CH_CFG_INT_STAT … #define ENET_DMA_CH_CFG_INT_MASK … #define ENET_DMA_CH_CFG_INT_BUFF_DONE … #define ENET_DMA_CH_CFG_INT_DONE … #define ENET_DMA_CH_CFG_INT_NO_DESC … #define ENET_DMA_CH_CFG_INT_RX_ERROR … #define ENET_DMA_CH_CFG_MAX_BURST … #define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL … #define ENET_DMA_CH_CFG_SIZE … #define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR … #define ENET_DMA_CH_STATE_RAM_STATE_DATA … #define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS … #define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR … #define ENET_DMA_CH_STATE_RAM_SIZE … #define DMA_CTL_STATUS_APPEND_CRC … #define DMA_CTL_STATUS_APPEND_BRCM_TAG … #define DMA_CTL_STATUS_PRIO … #define DMA_CTL_STATUS_WRAP … #define DMA_CTL_STATUS_SOP … #define DMA_CTL_STATUS_EOP … #define DMA_CTL_STATUS_OWN … #define DMA_CTL_LEN_DESC_BUFLENGTH … #define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT … #define DMA_CTL_LEN_DESC_MULTICAST … #define DMA_CTL_LEN_DESC_USEFPM … #endif
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