/* SPDX-License-Identifier: GPL-2.0 */ /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $ * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. * * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller ([email protected]) * Copyright (C) 2001 Jeff Garzik ([email protected]) * Copyright (C) 2004 Sun Microsystems Inc. * Copyright (C) 2007-2016 Broadcom Corporation. * Copyright (C) 2016-2017 Broadcom Limited. * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom" * refers to Broadcom Inc. and/or its subsidiaries. */ #ifndef _T3_H #define _T3_H #define TG3_64BIT_REG_HIGH … #define TG3_64BIT_REG_LOW … /* Descriptor block info. */ #define TG3_BDINFO_HOST_ADDR … #define TG3_BDINFO_MAXLEN_FLAGS … #define BDINFO_FLAGS_USE_EXT_RECV … #define BDINFO_FLAGS_DISABLED … #define BDINFO_FLAGS_MAXLEN_MASK … #define BDINFO_FLAGS_MAXLEN_SHIFT … #define TG3_BDINFO_NIC_ADDR … #define TG3_BDINFO_SIZE … #define TG3_RX_STD_MAX_SIZE_5700 … #define TG3_RX_STD_MAX_SIZE_5717 … #define TG3_RX_JMB_MAX_SIZE_5700 … #define TG3_RX_JMB_MAX_SIZE_5717 … #define TG3_RX_RET_MAX_SIZE_5700 … #define TG3_RX_RET_MAX_SIZE_5705 … #define TG3_RX_RET_MAX_SIZE_5717 … #define TG3_RSS_INDIR_TBL_SIZE … /* First 256 bytes are a mirror of PCI config space. */ #define TG3PCI_VENDOR … #define TG3PCI_VENDOR_BROADCOM … #define TG3PCI_DEVICE … #define TG3PCI_DEVICE_TIGON3_1 … #define TG3PCI_DEVICE_TIGON3_2 … #define TG3PCI_DEVICE_TIGON3_3 … #define TG3PCI_DEVICE_TIGON3_4 … #define TG3PCI_DEVICE_TIGON3_5761S … #define TG3PCI_DEVICE_TIGON3_5761SE … #define TG3PCI_DEVICE_TIGON3_57780 … #define TG3PCI_DEVICE_TIGON3_5787M … #define TG3PCI_DEVICE_TIGON3_57760 … #define TG3PCI_DEVICE_TIGON3_57790 … #define TG3PCI_DEVICE_TIGON3_57788 … #define TG3PCI_DEVICE_TIGON3_5785_G … #define TG3PCI_DEVICE_TIGON3_5785_F … #define TG3PCI_DEVICE_TIGON3_5717 … #define TG3PCI_DEVICE_TIGON3_5717_C … #define TG3PCI_DEVICE_TIGON3_5718 … #define TG3PCI_DEVICE_TIGON3_57781 … #define TG3PCI_DEVICE_TIGON3_57785 … #define TG3PCI_DEVICE_TIGON3_57761 … #define TG3PCI_DEVICE_TIGON3_57765 … #define TG3PCI_DEVICE_TIGON3_57791 … #define TG3PCI_DEVICE_TIGON3_57795 … #define TG3PCI_DEVICE_TIGON3_5719 … #define TG3PCI_DEVICE_TIGON3_5720 … #define TG3PCI_DEVICE_TIGON3_57762 … #define TG3PCI_DEVICE_TIGON3_57766 … #define TG3PCI_DEVICE_TIGON3_57786 … #define TG3PCI_DEVICE_TIGON3_57782 … #define TG3PCI_DEVICE_TIGON3_5762 … #define TG3PCI_DEVICE_TIGON3_5725 … #define TG3PCI_DEVICE_TIGON3_5727 … #define TG3PCI_DEVICE_TIGON3_57764 … #define TG3PCI_DEVICE_TIGON3_57767 … #define TG3PCI_DEVICE_TIGON3_57787 … /* 0x04 --> 0x2c unused */ #define TG3PCI_SUBVENDOR_ID_BROADCOM … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 … #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 … #define TG3PCI_SUBVENDOR_ID_3COM … #define TG3PCI_SUBDEVICE_ID_3COM_3C996T … #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT … #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX … #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T … #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 … #define TG3PCI_SUBVENDOR_ID_DELL … #define TG3PCI_SUBDEVICE_ID_DELL_VIPER … #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR … #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT … #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT … #define TG3PCI_SUBDEVICE_ID_DELL_5762 … #define TG3PCI_SUBVENDOR_ID_COMPAQ … #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE … #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 … #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING … #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 … #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 … #define TG3PCI_SUBVENDOR_ID_IBM … #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 … #define TG3PCI_SUBDEVICE_ID_ACER_57780_A … #define TG3PCI_SUBDEVICE_ID_ACER_57780_B … #define TG3PCI_SUBDEVICE_ID_LENOVO_5787M … /* 0x30 --> 0x64 unused */ #define TG3PCI_MSI_DATA … /* 0x66 --> 0x68 unused */ #define TG3PCI_MISC_HOST_CTRL … #define MISC_HOST_CTRL_CLEAR_INT … #define MISC_HOST_CTRL_MASK_PCI_INT … #define MISC_HOST_CTRL_BYTE_SWAP … #define MISC_HOST_CTRL_WORD_SWAP … #define MISC_HOST_CTRL_PCISTATE_RW … #define MISC_HOST_CTRL_CLKREG_RW … #define MISC_HOST_CTRL_REGWORD_SWAP … #define MISC_HOST_CTRL_INDIR_ACCESS … #define MISC_HOST_CTRL_IRQ_MASK_MODE … #define MISC_HOST_CTRL_TAGGED_STATUS … #define MISC_HOST_CTRL_CHIPREV … #define MISC_HOST_CTRL_CHIPREV_SHIFT … #define CHIPREV_ID_5700_A0 … #define CHIPREV_ID_5700_A1 … #define CHIPREV_ID_5700_B0 … #define CHIPREV_ID_5700_B1 … #define CHIPREV_ID_5700_B3 … #define CHIPREV_ID_5700_ALTIMA … #define CHIPREV_ID_5700_C0 … #define CHIPREV_ID_5701_A0 … #define CHIPREV_ID_5701_B0 … #define CHIPREV_ID_5701_B2 … #define CHIPREV_ID_5701_B5 … #define CHIPREV_ID_5703_A0 … #define CHIPREV_ID_5703_A1 … #define CHIPREV_ID_5703_A2 … #define CHIPREV_ID_5703_A3 … #define CHIPREV_ID_5704_A0 … #define CHIPREV_ID_5704_A1 … #define CHIPREV_ID_5704_A2 … #define CHIPREV_ID_5704_A3 … #define CHIPREV_ID_5705_A0 … #define CHIPREV_ID_5705_A1 … #define CHIPREV_ID_5705_A2 … #define CHIPREV_ID_5705_A3 … #define CHIPREV_ID_5750_A0 … #define CHIPREV_ID_5750_A1 … #define CHIPREV_ID_5750_A3 … #define CHIPREV_ID_5750_C2 … #define CHIPREV_ID_5752_A0_HW … #define CHIPREV_ID_5752_A0 … #define CHIPREV_ID_5752_A1 … #define CHIPREV_ID_5714_A2 … #define CHIPREV_ID_5906_A1 … #define CHIPREV_ID_57780_A0 … #define CHIPREV_ID_57780_A1 … #define CHIPREV_ID_5717_A0 … #define CHIPREV_ID_5717_C0 … #define CHIPREV_ID_57765_A0 … #define CHIPREV_ID_5719_A0 … #define CHIPREV_ID_5720_A0 … #define CHIPREV_ID_5762_A0 … #define ASIC_REV_5700 … #define ASIC_REV_5701 … #define ASIC_REV_5703 … #define ASIC_REV_5704 … #define ASIC_REV_5705 … #define ASIC_REV_5750 … #define ASIC_REV_5752 … #define ASIC_REV_5780 … #define ASIC_REV_5714 … #define ASIC_REV_5755 … #define ASIC_REV_5787 … #define ASIC_REV_5906 … #define ASIC_REV_USE_PROD_ID_REG … #define ASIC_REV_5784 … #define ASIC_REV_5761 … #define ASIC_REV_5785 … #define ASIC_REV_57780 … #define ASIC_REV_5717 … #define ASIC_REV_57765 … #define ASIC_REV_5719 … #define ASIC_REV_5720 … #define ASIC_REV_57766 … #define ASIC_REV_5762 … #define CHIPREV_5700_AX … #define CHIPREV_5700_BX … #define CHIPREV_5700_CX … #define CHIPREV_5701_AX … #define CHIPREV_5703_AX … #define CHIPREV_5704_AX … #define CHIPREV_5704_BX … #define CHIPREV_5750_AX … #define CHIPREV_5750_BX … #define CHIPREV_5784_AX … #define CHIPREV_5761_AX … #define CHIPREV_57765_AX … #define METAL_REV_A0 … #define METAL_REV_A1 … #define METAL_REV_B0 … #define METAL_REV_B1 … #define METAL_REV_B2 … #define TG3PCI_DMA_RW_CTRL … #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT … #define DMA_RWCTRL_TAGGED_STAT_WA … #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK … #define DMA_RWCTRL_READ_BNDRY_MASK … #define DMA_RWCTRL_READ_BNDRY_DISAB … #define DMA_RWCTRL_READ_BNDRY_16 … #define DMA_RWCTRL_READ_BNDRY_128_PCIX … #define DMA_RWCTRL_READ_BNDRY_32 … #define DMA_RWCTRL_READ_BNDRY_256_PCIX … #define DMA_RWCTRL_READ_BNDRY_64 … #define DMA_RWCTRL_READ_BNDRY_384_PCIX … #define DMA_RWCTRL_READ_BNDRY_128 … #define DMA_RWCTRL_READ_BNDRY_256 … #define DMA_RWCTRL_READ_BNDRY_512 … #define DMA_RWCTRL_READ_BNDRY_1024 … #define DMA_RWCTRL_WRITE_BNDRY_MASK … #define DMA_RWCTRL_WRITE_BNDRY_DISAB … #define DMA_RWCTRL_WRITE_BNDRY_16 … #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX … #define DMA_RWCTRL_WRITE_BNDRY_32 … #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX … #define DMA_RWCTRL_WRITE_BNDRY_64 … #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX … #define DMA_RWCTRL_WRITE_BNDRY_128 … #define DMA_RWCTRL_WRITE_BNDRY_256 … #define DMA_RWCTRL_WRITE_BNDRY_512 … #define DMA_RWCTRL_WRITE_BNDRY_1024 … #define DMA_RWCTRL_ONE_DMA … #define DMA_RWCTRL_READ_WATER … #define DMA_RWCTRL_READ_WATER_SHIFT … #define DMA_RWCTRL_WRITE_WATER … #define DMA_RWCTRL_WRITE_WATER_SHIFT … #define DMA_RWCTRL_USE_MEM_READ_MULT … #define DMA_RWCTRL_ASSERT_ALL_BE … #define DMA_RWCTRL_PCI_READ_CMD … #define DMA_RWCTRL_PCI_READ_CMD_SHIFT … #define DMA_RWCTRL_PCI_WRITE_CMD … #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT … #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE … #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE … #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE … #define TG3PCI_PCISTATE … #define PCISTATE_FORCE_RESET … #define PCISTATE_INT_NOT_ACTIVE … #define PCISTATE_CONV_PCI_MODE … #define PCISTATE_BUS_SPEED_HIGH … #define PCISTATE_BUS_32BIT … #define PCISTATE_ROM_ENABLE … #define PCISTATE_ROM_RETRY_ENABLE … #define PCISTATE_FLAT_VIEW … #define PCISTATE_RETRY_SAME_DMA … #define PCISTATE_ALLOW_APE_CTLSPC_WR … #define PCISTATE_ALLOW_APE_SHMEM_WR … #define PCISTATE_ALLOW_APE_PSPACE_WR … #define TG3PCI_CLOCK_CTRL … #define CLOCK_CTRL_CORECLK_DISABLE … #define CLOCK_CTRL_RXCLK_DISABLE … #define CLOCK_CTRL_TXCLK_DISABLE … #define CLOCK_CTRL_ALTCLK … #define CLOCK_CTRL_PWRDOWN_PLL133 … #define CLOCK_CTRL_44MHZ_CORE … #define CLOCK_CTRL_625_CORE … #define CLOCK_CTRL_FORCE_CLKRUN … #define CLOCK_CTRL_CLKRUN_OENABLE … #define CLOCK_CTRL_DELAY_PCI_GRANT … #define TG3PCI_REG_BASE_ADDR … #define TG3PCI_MEM_WIN_BASE_ADDR … #define TG3PCI_REG_DATA … #define TG3PCI_MEM_WIN_DATA … #define TG3PCI_MISC_LOCAL_CTRL … /* 0x94 --> 0x98 unused */ #define TG3PCI_STD_RING_PROD_IDX … #define TG3PCI_RCV_RET_RING_CON_IDX … /* 0xa8 --> 0xb8 unused */ #define TG3PCI_DEV_STATUS_CTRL … #define MAX_READ_REQ_SIZE_2048 … #define MAX_READ_REQ_MASK … #define TG3PCI_DUAL_MAC_CTRL … #define DUAL_MAC_CTRL_CH_MASK … #define DUAL_MAC_CTRL_ID … #define TG3PCI_PRODID_ASICREV … #define PROD_ID_ASIC_REV_MASK … /* 0xc0 --> 0xf4 unused */ #define TG3PCI_GEN2_PRODID_ASICREV … #define TG3PCI_GEN15_PRODID_ASICREV … /* 0xf8 --> 0x200 unused */ #define TG3_CORR_ERR_STAT … #define TG3_CORR_ERR_STAT_CLEAR … /* 0x114 --> 0x200 unused */ /* Mailbox registers */ #define MAILBOX_INTERRUPT_0 … #define MAILBOX_INTERRUPT_1 … #define MAILBOX_INTERRUPT_2 … #define MAILBOX_INTERRUPT_3 … #define MAILBOX_GENERAL_0 … #define MAILBOX_GENERAL_1 … #define MAILBOX_GENERAL_2 … #define MAILBOX_GENERAL_3 … #define MAILBOX_GENERAL_4 … #define MAILBOX_GENERAL_5 … #define MAILBOX_GENERAL_6 … #define MAILBOX_GENERAL_7 … #define MAILBOX_RELOAD_STAT … #define MAILBOX_RCV_STD_PROD_IDX … #define TG3_RX_STD_PROD_IDX_REG … #define MAILBOX_RCV_JUMBO_PROD_IDX … #define TG3_RX_JMB_PROD_IDX_REG … #define MAILBOX_RCV_MINI_PROD_IDX … #define MAILBOX_RCVRET_CON_IDX_0 … #define MAILBOX_RCVRET_CON_IDX_1 … #define MAILBOX_RCVRET_CON_IDX_2 … #define MAILBOX_RCVRET_CON_IDX_3 … #define MAILBOX_RCVRET_CON_IDX_4 … #define MAILBOX_RCVRET_CON_IDX_5 … #define MAILBOX_RCVRET_CON_IDX_6 … #define MAILBOX_RCVRET_CON_IDX_7 … #define MAILBOX_RCVRET_CON_IDX_8 … #define MAILBOX_RCVRET_CON_IDX_9 … #define MAILBOX_RCVRET_CON_IDX_10 … #define MAILBOX_RCVRET_CON_IDX_11 … #define MAILBOX_RCVRET_CON_IDX_12 … #define MAILBOX_RCVRET_CON_IDX_13 … #define MAILBOX_RCVRET_CON_IDX_14 … #define MAILBOX_RCVRET_CON_IDX_15 … #define MAILBOX_SNDHOST_PROD_IDX_0 … #define MAILBOX_SNDHOST_PROD_IDX_1 … #define MAILBOX_SNDHOST_PROD_IDX_2 … #define MAILBOX_SNDHOST_PROD_IDX_3 … #define MAILBOX_SNDHOST_PROD_IDX_4 … #define MAILBOX_SNDHOST_PROD_IDX_5 … #define MAILBOX_SNDHOST_PROD_IDX_6 … #define MAILBOX_SNDHOST_PROD_IDX_7 … #define MAILBOX_SNDHOST_PROD_IDX_8 … #define MAILBOX_SNDHOST_PROD_IDX_9 … #define MAILBOX_SNDHOST_PROD_IDX_10 … #define MAILBOX_SNDHOST_PROD_IDX_11 … #define MAILBOX_SNDHOST_PROD_IDX_12 … #define MAILBOX_SNDHOST_PROD_IDX_13 … #define MAILBOX_SNDHOST_PROD_IDX_14 … #define MAILBOX_SNDHOST_PROD_IDX_15 … #define MAILBOX_SNDNIC_PROD_IDX_0 … #define MAILBOX_SNDNIC_PROD_IDX_1 … #define MAILBOX_SNDNIC_PROD_IDX_2 … #define MAILBOX_SNDNIC_PROD_IDX_3 … #define MAILBOX_SNDNIC_PROD_IDX_4 … #define MAILBOX_SNDNIC_PROD_IDX_5 … #define MAILBOX_SNDNIC_PROD_IDX_6 … #define MAILBOX_SNDNIC_PROD_IDX_7 … #define MAILBOX_SNDNIC_PROD_IDX_8 … #define MAILBOX_SNDNIC_PROD_IDX_9 … #define MAILBOX_SNDNIC_PROD_IDX_10 … #define MAILBOX_SNDNIC_PROD_IDX_11 … #define MAILBOX_SNDNIC_PROD_IDX_12 … #define MAILBOX_SNDNIC_PROD_IDX_13 … #define MAILBOX_SNDNIC_PROD_IDX_14 … #define MAILBOX_SNDNIC_PROD_IDX_15 … /* MAC control registers */ #define MAC_MODE … #define MAC_MODE_RESET … #define MAC_MODE_HALF_DUPLEX … #define MAC_MODE_PORT_MODE_MASK … #define MAC_MODE_PORT_MODE_TBI … #define MAC_MODE_PORT_MODE_GMII … #define MAC_MODE_PORT_MODE_MII … #define MAC_MODE_PORT_MODE_NONE … #define MAC_MODE_PORT_INT_LPBACK … #define MAC_MODE_TAGGED_MAC_CTRL … #define MAC_MODE_TX_BURSTING … #define MAC_MODE_MAX_DEFER … #define MAC_MODE_LINK_POLARITY … #define MAC_MODE_RXSTAT_ENABLE … #define MAC_MODE_RXSTAT_CLEAR … #define MAC_MODE_RXSTAT_FLUSH … #define MAC_MODE_TXSTAT_ENABLE … #define MAC_MODE_TXSTAT_CLEAR … #define MAC_MODE_TXSTAT_FLUSH … #define MAC_MODE_SEND_CONFIGS … #define MAC_MODE_MAGIC_PKT_ENABLE … #define MAC_MODE_ACPI_ENABLE … #define MAC_MODE_MIP_ENABLE … #define MAC_MODE_TDE_ENABLE … #define MAC_MODE_RDE_ENABLE … #define MAC_MODE_FHDE_ENABLE … #define MAC_MODE_KEEP_FRAME_IN_WOL … #define MAC_MODE_APE_RX_EN … #define MAC_MODE_APE_TX_EN … #define MAC_STATUS … #define MAC_STATUS_PCS_SYNCED … #define MAC_STATUS_SIGNAL_DET … #define MAC_STATUS_RCVD_CFG … #define MAC_STATUS_CFG_CHANGED … #define MAC_STATUS_SYNC_CHANGED … #define MAC_STATUS_PORT_DEC_ERR … #define MAC_STATUS_LNKSTATE_CHANGED … #define MAC_STATUS_MI_COMPLETION … #define MAC_STATUS_MI_INTERRUPT … #define MAC_STATUS_AP_ERROR … #define MAC_STATUS_ODI_ERROR … #define MAC_STATUS_RXSTAT_OVERRUN … #define MAC_STATUS_TXSTAT_OVERRUN … #define MAC_EVENT … #define MAC_EVENT_PORT_DECODE_ERR … #define MAC_EVENT_LNKSTATE_CHANGED … #define MAC_EVENT_MI_COMPLETION … #define MAC_EVENT_MI_INTERRUPT … #define MAC_EVENT_AP_ERROR … #define MAC_EVENT_ODI_ERROR … #define MAC_EVENT_RXSTAT_OVERRUN … #define MAC_EVENT_TXSTAT_OVERRUN … #define MAC_LED_CTRL … #define LED_CTRL_LNKLED_OVERRIDE … #define LED_CTRL_1000MBPS_ON … #define LED_CTRL_100MBPS_ON … #define LED_CTRL_10MBPS_ON … #define LED_CTRL_TRAFFIC_OVERRIDE … #define LED_CTRL_TRAFFIC_BLINK … #define LED_CTRL_TRAFFIC_LED … #define LED_CTRL_1000MBPS_STATUS … #define LED_CTRL_100MBPS_STATUS … #define LED_CTRL_10MBPS_STATUS … #define LED_CTRL_TRAFFIC_STATUS … #define LED_CTRL_MODE_MAC … #define LED_CTRL_MODE_PHY_1 … #define LED_CTRL_MODE_PHY_2 … #define LED_CTRL_MODE_SHASTA_MAC … #define LED_CTRL_MODE_SHARED … #define LED_CTRL_MODE_COMBO … #define LED_CTRL_BLINK_RATE_MASK … #define LED_CTRL_BLINK_RATE_SHIFT … #define LED_CTRL_BLINK_PER_OVERRIDE … #define LED_CTRL_BLINK_RATE_OVERRIDE … #define MAC_ADDR_0_HIGH … #define MAC_ADDR_0_LOW … #define MAC_ADDR_1_HIGH … #define MAC_ADDR_1_LOW … #define MAC_ADDR_2_HIGH … #define MAC_ADDR_2_LOW … #define MAC_ADDR_3_HIGH … #define MAC_ADDR_3_LOW … #define MAC_ACPI_MBUF_PTR … #define MAC_ACPI_LEN_OFFSET … #define ACPI_LENOFF_LEN_MASK … #define ACPI_LENOFF_LEN_SHIFT … #define ACPI_LENOFF_OFF_MASK … #define ACPI_LENOFF_OFF_SHIFT … #define MAC_TX_BACKOFF_SEED … #define TX_BACKOFF_SEED_MASK … #define MAC_RX_MTU_SIZE … #define RX_MTU_SIZE_MASK … #define MAC_PCS_TEST … #define PCS_TEST_PATTERN_MASK … #define PCS_TEST_PATTERN_SHIFT … #define PCS_TEST_ENABLE … #define MAC_TX_AUTO_NEG … #define TX_AUTO_NEG_MASK … #define TX_AUTO_NEG_SHIFT … #define MAC_RX_AUTO_NEG … #define RX_AUTO_NEG_MASK … #define RX_AUTO_NEG_SHIFT … #define MAC_MI_COM … #define MI_COM_CMD_MASK … #define MI_COM_CMD_WRITE … #define MI_COM_CMD_READ … #define MI_COM_READ_FAILED … #define MI_COM_START … #define MI_COM_BUSY … #define MI_COM_PHY_ADDR_MASK … #define MI_COM_PHY_ADDR_SHIFT … #define MI_COM_REG_ADDR_MASK … #define MI_COM_REG_ADDR_SHIFT … #define MI_COM_DATA_MASK … #define MAC_MI_STAT … #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB … #define MAC_MI_STAT_10MBPS_MODE … #define MAC_MI_MODE … #define MAC_MI_MODE_CLK_10MHZ … #define MAC_MI_MODE_SHORT_PREAMBLE … #define MAC_MI_MODE_AUTO_POLL … #define MAC_MI_MODE_500KHZ_CONST … #define MAC_MI_MODE_BASE … #define MAC_AUTO_POLL_STATUS … #define MAC_AUTO_POLL_ERROR … #define MAC_TX_MODE … #define TX_MODE_RESET … #define TX_MODE_ENABLE … #define TX_MODE_FLOW_CTRL_ENABLE … #define TX_MODE_BIG_BCKOFF_ENABLE … #define TX_MODE_LONG_PAUSE_ENABLE … #define TX_MODE_MBUF_LOCKUP_FIX … #define TX_MODE_JMB_FRM_LEN … #define TX_MODE_CNT_DN_MODE … #define MAC_TX_STATUS … #define TX_STATUS_XOFFED … #define TX_STATUS_SENT_XOFF … #define TX_STATUS_SENT_XON … #define TX_STATUS_LINK_UP … #define TX_STATUS_ODI_UNDERRUN … #define TX_STATUS_ODI_OVERRUN … #define MAC_TX_LENGTHS … #define TX_LENGTHS_SLOT_TIME_MASK … #define TX_LENGTHS_SLOT_TIME_SHIFT … #define TX_LENGTHS_IPG_MASK … #define TX_LENGTHS_IPG_SHIFT … #define TX_LENGTHS_IPG_CRS_MASK … #define TX_LENGTHS_IPG_CRS_SHIFT … #define TX_LENGTHS_JMB_FRM_LEN_MSK … #define TX_LENGTHS_CNT_DWN_VAL_MSK … #define MAC_RX_MODE … #define RX_MODE_RESET … #define RX_MODE_ENABLE … #define RX_MODE_FLOW_CTRL_ENABLE … #define RX_MODE_KEEP_MAC_CTRL … #define RX_MODE_KEEP_PAUSE … #define RX_MODE_ACCEPT_OVERSIZED … #define RX_MODE_ACCEPT_RUNTS … #define RX_MODE_LEN_CHECK … #define RX_MODE_PROMISC … #define RX_MODE_NO_CRC_CHECK … #define RX_MODE_KEEP_VLAN_TAG … #define RX_MODE_RSS_IPV4_HASH_EN … #define RX_MODE_RSS_TCP_IPV4_HASH_EN … #define RX_MODE_RSS_IPV6_HASH_EN … #define RX_MODE_RSS_TCP_IPV6_HASH_EN … #define RX_MODE_RSS_ITBL_HASH_BITS_7 … #define RX_MODE_RSS_ENABLE … #define RX_MODE_IPV6_CSUM_ENABLE … #define RX_MODE_IPV4_FRAG_FIX … #define MAC_RX_STATUS … #define RX_STATUS_REMOTE_TX_XOFFED … #define RX_STATUS_XOFF_RCVD … #define RX_STATUS_XON_RCVD … #define MAC_HASH_REG_0 … #define MAC_HASH_REG_1 … #define MAC_HASH_REG_2 … #define MAC_HASH_REG_3 … #define MAC_RCV_RULE_0 … #define MAC_RCV_VALUE_0 … #define MAC_RCV_RULE_1 … #define MAC_RCV_VALUE_1 … #define MAC_RCV_RULE_2 … #define MAC_RCV_VALUE_2 … #define MAC_RCV_RULE_3 … #define MAC_RCV_VALUE_3 … #define MAC_RCV_RULE_4 … #define MAC_RCV_VALUE_4 … #define MAC_RCV_RULE_5 … #define MAC_RCV_VALUE_5 … #define MAC_RCV_RULE_6 … #define MAC_RCV_VALUE_6 … #define MAC_RCV_RULE_7 … #define MAC_RCV_VALUE_7 … #define MAC_RCV_RULE_8 … #define MAC_RCV_VALUE_8 … #define MAC_RCV_RULE_9 … #define MAC_RCV_VALUE_9 … #define MAC_RCV_RULE_10 … #define MAC_RCV_VALUE_10 … #define MAC_RCV_RULE_11 … #define MAC_RCV_VALUE_11 … #define MAC_RCV_RULE_12 … #define MAC_RCV_VALUE_12 … #define MAC_RCV_RULE_13 … #define MAC_RCV_VALUE_13 … #define MAC_RCV_RULE_14 … #define MAC_RCV_VALUE_14 … #define MAC_RCV_RULE_15 … #define MAC_RCV_VALUE_15 … #define RCV_RULE_DISABLE_MASK … #define MAC_RCV_RULE_CFG … #define RCV_RULE_CFG_DEFAULT_CLASS … #define MAC_LOW_WMARK_MAX_RX_FRAME … /* 0x508 --> 0x520 unused */ #define MAC_HASHREGU_0 … #define MAC_HASHREGU_1 … #define MAC_HASHREGU_2 … #define MAC_HASHREGU_3 … #define MAC_EXTADDR_0_HIGH … #define MAC_EXTADDR_0_LOW … #define MAC_EXTADDR_1_HIGH … #define MAC_EXTADDR_1_LOW … #define MAC_EXTADDR_2_HIGH … #define MAC_EXTADDR_2_LOW … #define MAC_EXTADDR_3_HIGH … #define MAC_EXTADDR_3_LOW … #define MAC_EXTADDR_4_HIGH … #define MAC_EXTADDR_4_LOW … #define MAC_EXTADDR_5_HIGH … #define MAC_EXTADDR_5_LOW … #define MAC_EXTADDR_6_HIGH … #define MAC_EXTADDR_6_LOW … #define MAC_EXTADDR_7_HIGH … #define MAC_EXTADDR_7_LOW … #define MAC_EXTADDR_8_HIGH … #define MAC_EXTADDR_8_LOW … #define MAC_EXTADDR_9_HIGH … #define MAC_EXTADDR_9_LOW … #define MAC_EXTADDR_10_HIGH … #define MAC_EXTADDR_10_LOW … #define MAC_EXTADDR_11_HIGH … #define MAC_EXTADDR_11_LOW … #define MAC_SERDES_CFG … #define MAC_SERDES_CFG_EDGE_SELECT … #define MAC_SERDES_STAT … /* 0x598 --> 0x5a0 unused */ #define MAC_PHYCFG1 … #define MAC_PHYCFG1_RGMII_INT … #define MAC_PHYCFG1_RXCLK_TO_MASK … #define MAC_PHYCFG1_RXCLK_TIMEOUT … #define MAC_PHYCFG1_TXCLK_TO_MASK … #define MAC_PHYCFG1_TXCLK_TIMEOUT … #define MAC_PHYCFG1_RGMII_EXT_RX_DEC … #define MAC_PHYCFG1_RGMII_SND_STAT_EN … #define MAC_PHYCFG1_TXC_DRV … #define MAC_PHYCFG2 … #define MAC_PHYCFG2_INBAND_ENABLE … #define MAC_PHYCFG2_EMODE_MASK_MASK … #define MAC_PHYCFG2_EMODE_MASK_AC131 … #define MAC_PHYCFG2_EMODE_MASK_50610 … #define MAC_PHYCFG2_EMODE_MASK_RT8211 … #define MAC_PHYCFG2_EMODE_MASK_RT8201 … #define MAC_PHYCFG2_EMODE_COMP_MASK … #define MAC_PHYCFG2_EMODE_COMP_AC131 … #define MAC_PHYCFG2_EMODE_COMP_50610 … #define MAC_PHYCFG2_EMODE_COMP_RT8211 … #define MAC_PHYCFG2_EMODE_COMP_RT8201 … #define MAC_PHYCFG2_FMODE_MASK_MASK … #define MAC_PHYCFG2_FMODE_MASK_AC131 … #define MAC_PHYCFG2_FMODE_MASK_50610 … #define MAC_PHYCFG2_FMODE_MASK_RT8211 … #define MAC_PHYCFG2_FMODE_MASK_RT8201 … #define MAC_PHYCFG2_FMODE_COMP_MASK … #define MAC_PHYCFG2_FMODE_COMP_AC131 … #define MAC_PHYCFG2_FMODE_COMP_50610 … #define MAC_PHYCFG2_FMODE_COMP_RT8211 … #define MAC_PHYCFG2_FMODE_COMP_RT8201 … #define MAC_PHYCFG2_GMODE_MASK_MASK … #define MAC_PHYCFG2_GMODE_MASK_AC131 … #define MAC_PHYCFG2_GMODE_MASK_50610 … #define MAC_PHYCFG2_GMODE_MASK_RT8211 … #define MAC_PHYCFG2_GMODE_MASK_RT8201 … #define MAC_PHYCFG2_GMODE_COMP_MASK … #define MAC_PHYCFG2_GMODE_COMP_AC131 … #define MAC_PHYCFG2_GMODE_COMP_50610 … #define MAC_PHYCFG2_GMODE_COMP_RT8211 … #define MAC_PHYCFG2_GMODE_COMP_RT8201 … #define MAC_PHYCFG2_ACT_MASK_MASK … #define MAC_PHYCFG2_ACT_MASK_AC131 … #define MAC_PHYCFG2_ACT_MASK_50610 … #define MAC_PHYCFG2_ACT_MASK_RT8211 … #define MAC_PHYCFG2_ACT_MASK_RT8201 … #define MAC_PHYCFG2_ACT_COMP_MASK … #define MAC_PHYCFG2_ACT_COMP_AC131 … #define MAC_PHYCFG2_ACT_COMP_50610 … #define MAC_PHYCFG2_ACT_COMP_RT8211 … #define MAC_PHYCFG2_ACT_COMP_RT8201 … #define MAC_PHYCFG2_QUAL_MASK_MASK … #define MAC_PHYCFG2_QUAL_MASK_AC131 … #define MAC_PHYCFG2_QUAL_MASK_50610 … #define MAC_PHYCFG2_QUAL_MASK_RT8211 … #define MAC_PHYCFG2_QUAL_MASK_RT8201 … #define MAC_PHYCFG2_QUAL_COMP_MASK … #define MAC_PHYCFG2_QUAL_COMP_AC131 … #define MAC_PHYCFG2_QUAL_COMP_50610 … #define MAC_PHYCFG2_QUAL_COMP_RT8211 … #define MAC_PHYCFG2_QUAL_COMP_RT8201 … #define MAC_PHYCFG2_50610_LED_MODES … #define MAC_PHYCFG2_AC131_LED_MODES … #define MAC_PHYCFG2_RTL8211C_LED_MODES … #define MAC_PHYCFG2_RTL8201E_LED_MODES … #define MAC_EXT_RGMII_MODE … #define MAC_RGMII_MODE_TX_ENABLE … #define MAC_RGMII_MODE_TX_LOWPWR … #define MAC_RGMII_MODE_TX_RESET … #define MAC_RGMII_MODE_RX_INT_B … #define MAC_RGMII_MODE_RX_QUALITY … #define MAC_RGMII_MODE_RX_ACTIVITY … #define MAC_RGMII_MODE_RX_ENG_DET … /* 0x5ac --> 0x5b0 unused */ #define SERDES_RX_CTRL … #define SERDES_RX_SIG_DETECT … #define SG_DIG_CTRL … #define SG_DIG_USING_HW_AUTONEG … #define SG_DIG_SOFT_RESET … #define SG_DIG_DISABLE_LINKRDY … #define SG_DIG_CRC16_CLEAR_N … #define SG_DIG_EN10B … #define SG_DIG_CLEAR_STATUS … #define SG_DIG_LOCAL_DUPLEX_STATUS … #define SG_DIG_LOCAL_LINK_STATUS … #define SG_DIG_SPEED_STATUS_MASK … #define SG_DIG_SPEED_STATUS_SHIFT … #define SG_DIG_JUMBO_PACKET_DISABLE … #define SG_DIG_RESTART_AUTONEG … #define SG_DIG_FIBER_MODE … #define SG_DIG_REMOTE_FAULT_MASK … #define SG_DIG_PAUSE_MASK … #define SG_DIG_PAUSE_CAP … #define SG_DIG_ASYM_PAUSE … #define SG_DIG_GBIC_ENABLE … #define SG_DIG_CHECK_END_ENABLE … #define SG_DIG_SGMII_AUTONEG_TIMER … #define SG_DIG_CLOCK_PHASE_SELECT … #define SG_DIG_GMII_INPUT_SELECT … #define SG_DIG_MRADV_CRC16_SELECT … #define SG_DIG_COMMA_DETECT_ENABLE … #define SG_DIG_AUTONEG_TIMER_REDUCE … #define SG_DIG_AUTONEG_LOW_ENABLE … #define SG_DIG_REMOTE_LOOPBACK … #define SG_DIG_LOOPBACK … #define SG_DIG_COMMON_SETUP … #define SG_DIG_STATUS … #define SG_DIG_CRC16_BUS_MASK … #define SG_DIG_PARTNER_FAULT_MASK … #define SG_DIG_PARTNER_ASYM_PAUSE … #define SG_DIG_PARTNER_PAUSE_CAPABLE … #define SG_DIG_PARTNER_HALF_DUPLEX … #define SG_DIG_PARTNER_FULL_DUPLEX … #define SG_DIG_PARTNER_NEXT_PAGE … #define SG_DIG_AUTONEG_STATE_MASK … #define SG_DIG_IS_SERDES … #define SG_DIG_COMMA_DETECTOR … #define SG_DIG_MAC_ACK_STATUS … #define SG_DIG_AUTONEG_COMPLETE … #define SG_DIG_AUTONEG_ERROR … #define TG3_TX_TSTAMP_LSB … #define TG3_TX_TSTAMP_MSB … #define TG3_TSTAMP_MASK … /* 0x5c8 --> 0x600 unused */ #define MAC_TX_MAC_STATE_BASE … #define MAC_RX_MAC_STATE_BASE … /* 0x624 --> 0x670 unused */ #define MAC_RSS_INDIR_TBL_0 … #define MAC_RSS_HASH_KEY_0 … #define MAC_RSS_HASH_KEY_1 … #define MAC_RSS_HASH_KEY_2 … #define MAC_RSS_HASH_KEY_3 … #define MAC_RSS_HASH_KEY_4 … #define MAC_RSS_HASH_KEY_5 … #define MAC_RSS_HASH_KEY_6 … #define MAC_RSS_HASH_KEY_7 … #define MAC_RSS_HASH_KEY_8 … #define MAC_RSS_HASH_KEY_9 … /* 0x698 --> 0x6b0 unused */ #define TG3_RX_TSTAMP_LSB … #define TG3_RX_TSTAMP_MSB … /* 0x6b8 --> 0x6c8 unused */ #define TG3_RX_PTP_CTL … #define TG3_RX_PTP_CTL_SYNC_EVNT … #define TG3_RX_PTP_CTL_DELAY_REQ … #define TG3_RX_PTP_CTL_PDLAY_REQ … #define TG3_RX_PTP_CTL_PDLAY_RES … #define TG3_RX_PTP_CTL_ALL_V1_EVENTS … #define TG3_RX_PTP_CTL_ALL_V2_EVENTS … #define TG3_RX_PTP_CTL_FOLLOW_UP … #define TG3_RX_PTP_CTL_DELAY_RES … #define TG3_RX_PTP_CTL_PDRES_FLW_UP … #define TG3_RX_PTP_CTL_ANNOUNCE … #define TG3_RX_PTP_CTL_SIGNALING … #define TG3_RX_PTP_CTL_MANAGEMENT … #define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN … #define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN … #define TG3_RX_PTP_CTL_RX_PTP_V2_EN … #define TG3_RX_PTP_CTL_RX_PTP_V1_EN … #define TG3_RX_PTP_CTL_HWTS_INTERLOCK … /* 0x6cc --> 0x800 unused */ #define MAC_TX_STATS_OCTETS … #define MAC_TX_STATS_RESV1 … #define MAC_TX_STATS_COLLISIONS … #define MAC_TX_STATS_XON_SENT … #define MAC_TX_STATS_XOFF_SENT … #define MAC_TX_STATS_RESV2 … #define MAC_TX_STATS_MAC_ERRORS … #define MAC_TX_STATS_SINGLE_COLLISIONS … #define MAC_TX_STATS_MULT_COLLISIONS … #define MAC_TX_STATS_DEFERRED … #define MAC_TX_STATS_RESV3 … #define MAC_TX_STATS_EXCESSIVE_COL … #define MAC_TX_STATS_LATE_COL … #define MAC_TX_STATS_RESV4_1 … #define MAC_TX_STATS_RESV4_2 … #define MAC_TX_STATS_RESV4_3 … #define MAC_TX_STATS_RESV4_4 … #define MAC_TX_STATS_RESV4_5 … #define MAC_TX_STATS_RESV4_6 … #define MAC_TX_STATS_RESV4_7 … #define MAC_TX_STATS_RESV4_8 … #define MAC_TX_STATS_RESV4_9 … #define MAC_TX_STATS_RESV4_10 … #define MAC_TX_STATS_RESV4_11 … #define MAC_TX_STATS_RESV4_12 … #define MAC_TX_STATS_RESV4_13 … #define MAC_TX_STATS_RESV4_14 … #define MAC_TX_STATS_UCAST … #define MAC_TX_STATS_MCAST … #define MAC_TX_STATS_BCAST … #define MAC_TX_STATS_RESV5_1 … #define MAC_TX_STATS_RESV5_2 … #define MAC_RX_STATS_OCTETS … #define MAC_RX_STATS_RESV1 … #define MAC_RX_STATS_FRAGMENTS … #define MAC_RX_STATS_UCAST … #define MAC_RX_STATS_MCAST … #define MAC_RX_STATS_BCAST … #define MAC_RX_STATS_FCS_ERRORS … #define MAC_RX_STATS_ALIGN_ERRORS … #define MAC_RX_STATS_XON_PAUSE_RECVD … #define MAC_RX_STATS_XOFF_PAUSE_RECVD … #define MAC_RX_STATS_MAC_CTRL_RECVD … #define MAC_RX_STATS_XOFF_ENTERED … #define MAC_RX_STATS_FRAME_TOO_LONG … #define MAC_RX_STATS_JABBERS … #define MAC_RX_STATS_UNDERSIZE … /* 0x8bc --> 0xc00 unused */ /* Send data initiator control registers */ #define SNDDATAI_MODE … #define SNDDATAI_MODE_RESET … #define SNDDATAI_MODE_ENABLE … #define SNDDATAI_MODE_STAT_OFLOW_ENAB … #define SNDDATAI_STATUS … #define SNDDATAI_STATUS_STAT_OFLOW … #define SNDDATAI_STATSCTRL … #define SNDDATAI_SCTRL_ENABLE … #define SNDDATAI_SCTRL_FASTUPD … #define SNDDATAI_SCTRL_CLEAR … #define SNDDATAI_SCTRL_FLUSH … #define SNDDATAI_SCTRL_FORCE_ZERO … #define SNDDATAI_STATSENAB … #define SNDDATAI_STATSINCMASK … #define ISO_PKT_TX … /* 0xc24 --> 0xc80 unused */ #define SNDDATAI_COS_CNT_0 … #define SNDDATAI_COS_CNT_1 … #define SNDDATAI_COS_CNT_2 … #define SNDDATAI_COS_CNT_3 … #define SNDDATAI_COS_CNT_4 … #define SNDDATAI_COS_CNT_5 … #define SNDDATAI_COS_CNT_6 … #define SNDDATAI_COS_CNT_7 … #define SNDDATAI_COS_CNT_8 … #define SNDDATAI_COS_CNT_9 … #define SNDDATAI_COS_CNT_10 … #define SNDDATAI_COS_CNT_11 … #define SNDDATAI_COS_CNT_12 … #define SNDDATAI_COS_CNT_13 … #define SNDDATAI_COS_CNT_14 … #define SNDDATAI_COS_CNT_15 … #define SNDDATAI_DMA_RDQ_FULL_CNT … #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT … #define SNDDATAI_SDCQ_FULL_CNT … #define SNDDATAI_NICRNG_SSND_PIDX_CNT … #define SNDDATAI_STATS_UPDATED_CNT … #define SNDDATAI_INTERRUPTS_CNT … #define SNDDATAI_AVOID_INTERRUPTS_CNT … #define SNDDATAI_SND_THRESH_HIT_CNT … /* 0xce0 --> 0x1000 unused */ /* Send data completion control registers */ #define SNDDATAC_MODE … #define SNDDATAC_MODE_RESET … #define SNDDATAC_MODE_ENABLE … #define SNDDATAC_MODE_CDELAY … /* 0x1004 --> 0x1400 unused */ /* Send BD ring selector */ #define SNDBDS_MODE … #define SNDBDS_MODE_RESET … #define SNDBDS_MODE_ENABLE … #define SNDBDS_MODE_ATTN_ENABLE … #define SNDBDS_STATUS … #define SNDBDS_STATUS_ERROR_ATTN … #define SNDBDS_HWDIAG … /* 0x140c --> 0x1440 */ #define SNDBDS_SEL_CON_IDX_0 … #define SNDBDS_SEL_CON_IDX_1 … #define SNDBDS_SEL_CON_IDX_2 … #define SNDBDS_SEL_CON_IDX_3 … #define SNDBDS_SEL_CON_IDX_4 … #define SNDBDS_SEL_CON_IDX_5 … #define SNDBDS_SEL_CON_IDX_6 … #define SNDBDS_SEL_CON_IDX_7 … #define SNDBDS_SEL_CON_IDX_8 … #define SNDBDS_SEL_CON_IDX_9 … #define SNDBDS_SEL_CON_IDX_10 … #define SNDBDS_SEL_CON_IDX_11 … #define SNDBDS_SEL_CON_IDX_12 … #define SNDBDS_SEL_CON_IDX_13 … #define SNDBDS_SEL_CON_IDX_14 … #define SNDBDS_SEL_CON_IDX_15 … /* 0x1480 --> 0x1800 unused */ /* Send BD initiator control registers */ #define SNDBDI_MODE … #define SNDBDI_MODE_RESET … #define SNDBDI_MODE_ENABLE … #define SNDBDI_MODE_ATTN_ENABLE … #define SNDBDI_MODE_MULTI_TXQ_EN … #define SNDBDI_STATUS … #define SNDBDI_STATUS_ERROR_ATTN … #define SNDBDI_IN_PROD_IDX_0 … #define SNDBDI_IN_PROD_IDX_1 … #define SNDBDI_IN_PROD_IDX_2 … #define SNDBDI_IN_PROD_IDX_3 … #define SNDBDI_IN_PROD_IDX_4 … #define SNDBDI_IN_PROD_IDX_5 … #define SNDBDI_IN_PROD_IDX_6 … #define SNDBDI_IN_PROD_IDX_7 … #define SNDBDI_IN_PROD_IDX_8 … #define SNDBDI_IN_PROD_IDX_9 … #define SNDBDI_IN_PROD_IDX_10 … #define SNDBDI_IN_PROD_IDX_11 … #define SNDBDI_IN_PROD_IDX_12 … #define SNDBDI_IN_PROD_IDX_13 … #define SNDBDI_IN_PROD_IDX_14 … #define SNDBDI_IN_PROD_IDX_15 … /* 0x1848 --> 0x1c00 unused */ /* Send BD completion control registers */ #define SNDBDC_MODE … #define SNDBDC_MODE_RESET … #define SNDBDC_MODE_ENABLE … #define SNDBDC_MODE_ATTN_ENABLE … /* 0x1c04 --> 0x2000 unused */ /* Receive list placement control registers */ #define RCVLPC_MODE … #define RCVLPC_MODE_RESET … #define RCVLPC_MODE_ENABLE … #define RCVLPC_MODE_CLASS0_ATTN_ENAB … #define RCVLPC_MODE_MAPOOR_AATTN_ENAB … #define RCVLPC_MODE_STAT_OFLOW_ENAB … #define RCVLPC_STATUS … #define RCVLPC_STATUS_CLASS0 … #define RCVLPC_STATUS_MAPOOR … #define RCVLPC_STATUS_STAT_OFLOW … #define RCVLPC_LOCK … #define RCVLPC_LOCK_REQ_MASK … #define RCVLPC_LOCK_REQ_SHIFT … #define RCVLPC_LOCK_GRANT_MASK … #define RCVLPC_LOCK_GRANT_SHIFT … #define RCVLPC_NON_EMPTY_BITS … #define RCVLPC_NON_EMPTY_BITS_MASK … #define RCVLPC_CONFIG … #define RCVLPC_STATSCTRL … #define RCVLPC_STATSCTRL_ENABLE … #define RCVLPC_STATSCTRL_FASTUPD … #define RCVLPC_STATS_ENABLE … #define RCVLPC_STATSENAB_ASF_FIX … #define RCVLPC_STATSENAB_DACK_FIX … #define RCVLPC_STATSENAB_LNGBRST_RFIX … #define RCVLPC_STATS_INCMASK … /* 0x2020 --> 0x2100 unused */ #define RCVLPC_SELLST_BASE … #define SELLST_TAIL … #define SELLST_CONT … #define SELLST_UNUSED … #define RCVLPC_COS_CNTL_BASE … #define RCVLPC_DROP_FILTER_CNT … #define RCVLPC_DMA_WQ_FULL_CNT … #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT … #define RCVLPC_NO_RCV_BD_CNT … #define RCVLPC_IN_DISCARDS_CNT … #define RCVLPC_IN_ERRORS_CNT … #define RCVLPC_RCV_THRESH_HIT_CNT … /* 0x225c --> 0x2400 unused */ /* Receive Data and Receive BD Initiator Control */ #define RCVDBDI_MODE … #define RCVDBDI_MODE_RESET … #define RCVDBDI_MODE_ENABLE … #define RCVDBDI_MODE_JUMBOBD_NEEDED … #define RCVDBDI_MODE_FRM_TOO_BIG … #define RCVDBDI_MODE_INV_RING_SZ … #define RCVDBDI_MODE_LRG_RING_SZ … #define RCVDBDI_STATUS … #define RCVDBDI_STATUS_JUMBOBD_NEEDED … #define RCVDBDI_STATUS_FRM_TOO_BIG … #define RCVDBDI_STATUS_INV_RING_SZ … #define RCVDBDI_SPLIT_FRAME_MINSZ … /* 0x240c --> 0x2440 unused */ #define RCVDBDI_JUMBO_BD … #define RCVDBDI_STD_BD … #define RCVDBDI_MINI_BD … #define RCVDBDI_JUMBO_CON_IDX … #define RCVDBDI_STD_CON_IDX … #define RCVDBDI_MINI_CON_IDX … /* 0x247c --> 0x2480 unused */ #define RCVDBDI_BD_PROD_IDX_0 … #define RCVDBDI_BD_PROD_IDX_1 … #define RCVDBDI_BD_PROD_IDX_2 … #define RCVDBDI_BD_PROD_IDX_3 … #define RCVDBDI_BD_PROD_IDX_4 … #define RCVDBDI_BD_PROD_IDX_5 … #define RCVDBDI_BD_PROD_IDX_6 … #define RCVDBDI_BD_PROD_IDX_7 … #define RCVDBDI_BD_PROD_IDX_8 … #define RCVDBDI_BD_PROD_IDX_9 … #define RCVDBDI_BD_PROD_IDX_10 … #define RCVDBDI_BD_PROD_IDX_11 … #define RCVDBDI_BD_PROD_IDX_12 … #define RCVDBDI_BD_PROD_IDX_13 … #define RCVDBDI_BD_PROD_IDX_14 … #define RCVDBDI_BD_PROD_IDX_15 … #define RCVDBDI_HWDIAG … /* 0x24c4 --> 0x2800 unused */ /* Receive Data Completion Control */ #define RCVDCC_MODE … #define RCVDCC_MODE_RESET … #define RCVDCC_MODE_ENABLE … #define RCVDCC_MODE_ATTN_ENABLE … /* 0x2804 --> 0x2c00 unused */ /* Receive BD Initiator Control Registers */ #define RCVBDI_MODE … #define RCVBDI_MODE_RESET … #define RCVBDI_MODE_ENABLE … #define RCVBDI_MODE_RCB_ATTN_ENAB … #define RCVBDI_STATUS … #define RCVBDI_STATUS_RCB_ATTN … #define RCVBDI_JUMBO_PROD_IDX … #define RCVBDI_STD_PROD_IDX … #define RCVBDI_MINI_PROD_IDX … #define RCVBDI_MINI_THRESH … #define RCVBDI_STD_THRESH … #define RCVBDI_JUMBO_THRESH … /* 0x2c20 --> 0x2d00 unused */ #define STD_REPLENISH_LWM … #define JMB_REPLENISH_LWM … /* 0x2d08 --> 0x3000 unused */ /* Receive BD Completion Control Registers */ #define RCVCC_MODE … #define RCVCC_MODE_RESET … #define RCVCC_MODE_ENABLE … #define RCVCC_MODE_ATTN_ENABLE … #define RCVCC_STATUS … #define RCVCC_STATUS_ERROR_ATTN … #define RCVCC_JUMP_PROD_IDX … #define RCVCC_STD_PROD_IDX … #define RCVCC_MINI_PROD_IDX … /* 0x3014 --> 0x3400 unused */ /* Receive list selector control registers */ #define RCVLSC_MODE … #define RCVLSC_MODE_RESET … #define RCVLSC_MODE_ENABLE … #define RCVLSC_MODE_ATTN_ENABLE … #define RCVLSC_STATUS … #define RCVLSC_STATUS_ERROR_ATTN … /* 0x3408 --> 0x3600 unused */ #define TG3_CPMU_DRV_STATUS … /* CPMU registers */ #define TG3_CPMU_CTRL … #define CPMU_CTRL_LINK_IDLE_MODE … #define CPMU_CTRL_LINK_AWARE_MODE … #define CPMU_CTRL_LINK_SPEED_MODE … #define CPMU_CTRL_GPHY_10MB_RXONLY … #define TG3_CPMU_LSPD_10MB_CLK … #define CPMU_LSPD_10MB_MACCLK_MASK … #define CPMU_LSPD_10MB_MACCLK_6_25 … /* 0x3608 --> 0x360c unused */ #define TG3_CPMU_LSPD_1000MB_CLK … #define CPMU_LSPD_1000MB_MACCLK_62_5 … #define CPMU_LSPD_1000MB_MACCLK_12_5 … #define CPMU_LSPD_1000MB_MACCLK_MASK … #define TG3_CPMU_LNK_AWARE_PWRMD … #define CPMU_LNK_AWARE_MACCLK_MASK … #define CPMU_LNK_AWARE_MACCLK_6_25 … /* 0x3614 --> 0x361c unused */ #define TG3_CPMU_HST_ACC … #define CPMU_HST_ACC_MACCLK_MASK … #define CPMU_HST_ACC_MACCLK_6_25 … /* 0x3620 --> 0x3630 unused */ #define TG3_CPMU_CLCK_ORIDE … #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN … #define TG3_CPMU_CLCK_ORIDE_ENABLE … #define TG3_CPMU_MAC_ORIDE_ENABLE … #define TG3_CPMU_STATUS … #define TG3_CPMU_STATUS_FMSK_5717 … #define TG3_CPMU_STATUS_FMSK_5719 … #define TG3_CPMU_STATUS_FSHFT_5719 … #define TG3_CPMU_STATUS_LINK_MASK … #define TG3_CPMU_CLCK_STAT … #define CPMU_CLCK_STAT_MAC_CLCK_MASK … #define CPMU_CLCK_STAT_MAC_CLCK_62_5 … #define CPMU_CLCK_STAT_MAC_CLCK_12_5 … #define CPMU_CLCK_STAT_MAC_CLCK_6_25 … /* 0x3634 --> 0x365c unused */ #define TG3_CPMU_MUTEX_REQ … #define CPMU_MUTEX_REQ_DRIVER … #define TG3_CPMU_MUTEX_GNT … #define CPMU_MUTEX_GNT_DRIVER … #define TG3_CPMU_PHY_STRAP … #define TG3_CPMU_PHY_STRAP_IS_SERDES … #define TG3_CPMU_PADRNG_CTL … #define TG3_CPMU_PADRNG_CTL_RDIV2 … /* 0x3664 --> 0x36b0 unused */ #define TG3_CPMU_EEE_MODE … #define TG3_CPMU_EEEMD_APE_TX_DET_EN … #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET … #define TG3_CPMU_EEEMD_SND_IDX_DET_EN … #define TG3_CPMU_EEEMD_LPI_ENABLE … #define TG3_CPMU_EEEMD_LPI_IN_TX … #define TG3_CPMU_EEEMD_LPI_IN_RX … #define TG3_CPMU_EEEMD_EEE_ENABLE … #define TG3_CPMU_EEE_DBTMR1 … #define TG3_CPMU_DBTMR1_PCIEXIT_2047US … #define TG3_CPMU_DBTMR1_LNKIDLE_2047US … #define TG3_CPMU_DBTMR1_LNKIDLE_MAX … #define TG3_CPMU_EEE_DBTMR2 … #define TG3_CPMU_DBTMR2_APE_TX_2047US … #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US … #define TG3_CPMU_EEE_LNKIDL_CTRL … #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 … #define TG3_CPMU_EEE_LNKIDL_UART_IDL … #define TG3_CPMU_EEE_LNKIDL_APE_TX_MT … /* 0x36c0 --> 0x36d0 unused */ #define TG3_CPMU_EEE_CTRL … #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US … #define TG3_CPMU_EEE_CTRL_EXIT_36_US … #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US … /* 0x36d4 --> 0x3800 unused */ /* Mbuf cluster free registers */ #define MBFREE_MODE … #define MBFREE_MODE_RESET … #define MBFREE_MODE_ENABLE … #define MBFREE_STATUS … /* 0x3808 --> 0x3c00 unused */ /* Host coalescing control registers */ #define HOSTCC_MODE … #define HOSTCC_MODE_RESET … #define HOSTCC_MODE_ENABLE … #define HOSTCC_MODE_ATTN … #define HOSTCC_MODE_NOW … #define HOSTCC_MODE_FULL_STATUS … #define HOSTCC_MODE_64BYTE … #define HOSTCC_MODE_32BYTE … #define HOSTCC_MODE_CLRTICK_RXBD … #define HOSTCC_MODE_CLRTICK_TXBD … #define HOSTCC_MODE_NOINT_ON_NOW … #define HOSTCC_MODE_NOINT_ON_FORCE … #define HOSTCC_MODE_COAL_VEC1_NOW … #define HOSTCC_STATUS … #define HOSTCC_STATUS_ERROR_ATTN … #define HOSTCC_RXCOL_TICKS … #define LOW_RXCOL_TICKS … #define LOW_RXCOL_TICKS_CLRTCKS … #define DEFAULT_RXCOL_TICKS … #define HIGH_RXCOL_TICKS … #define MAX_RXCOL_TICKS … #define HOSTCC_TXCOL_TICKS … #define LOW_TXCOL_TICKS … #define LOW_TXCOL_TICKS_CLRTCKS … #define DEFAULT_TXCOL_TICKS … #define HIGH_TXCOL_TICKS … #define MAX_TXCOL_TICKS … #define HOSTCC_RXMAX_FRAMES … #define LOW_RXMAX_FRAMES … #define DEFAULT_RXMAX_FRAMES … #define HIGH_RXMAX_FRAMES … #define MAX_RXMAX_FRAMES … #define HOSTCC_TXMAX_FRAMES … #define LOW_TXMAX_FRAMES … #define DEFAULT_TXMAX_FRAMES … #define HIGH_TXMAX_FRAMES … #define MAX_TXMAX_FRAMES … #define HOSTCC_RXCOAL_TICK_INT … #define DEFAULT_RXCOAL_TICK_INT … #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS … #define MAX_RXCOAL_TICK_INT … #define HOSTCC_TXCOAL_TICK_INT … #define DEFAULT_TXCOAL_TICK_INT … #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS … #define MAX_TXCOAL_TICK_INT … #define HOSTCC_RXCOAL_MAXF_INT … #define DEFAULT_RXCOAL_MAXF_INT … #define MAX_RXCOAL_MAXF_INT … #define HOSTCC_TXCOAL_MAXF_INT … #define DEFAULT_TXCOAL_MAXF_INT … #define MAX_TXCOAL_MAXF_INT … #define HOSTCC_STAT_COAL_TICKS … #define DEFAULT_STAT_COAL_TICKS … #define MAX_STAT_COAL_TICKS … #define MIN_STAT_COAL_TICKS … /* 0x3c2c --> 0x3c30 unused */ #define HOSTCC_STATS_BLK_HOST_ADDR … #define HOSTCC_STATUS_BLK_HOST_ADDR … #define HOSTCC_STATS_BLK_NIC_ADDR … #define HOSTCC_STATUS_BLK_NIC_ADDR … #define HOSTCC_FLOW_ATTN … #define HOSTCC_FLOW_ATTN_MBUF_LWM … /* 0x3c4c --> 0x3c50 unused */ #define HOSTCC_JUMBO_CON_IDX … #define HOSTCC_STD_CON_IDX … #define HOSTCC_MINI_CON_IDX … /* 0x3c5c --> 0x3c80 unused */ #define HOSTCC_RET_PROD_IDX_0 … #define HOSTCC_RET_PROD_IDX_1 … #define HOSTCC_RET_PROD_IDX_2 … #define HOSTCC_RET_PROD_IDX_3 … #define HOSTCC_RET_PROD_IDX_4 … #define HOSTCC_RET_PROD_IDX_5 … #define HOSTCC_RET_PROD_IDX_6 … #define HOSTCC_RET_PROD_IDX_7 … #define HOSTCC_RET_PROD_IDX_8 … #define HOSTCC_RET_PROD_IDX_9 … #define HOSTCC_RET_PROD_IDX_10 … #define HOSTCC_RET_PROD_IDX_11 … #define HOSTCC_RET_PROD_IDX_12 … #define HOSTCC_RET_PROD_IDX_13 … #define HOSTCC_RET_PROD_IDX_14 … #define HOSTCC_RET_PROD_IDX_15 … #define HOSTCC_SND_CON_IDX_0 … #define HOSTCC_SND_CON_IDX_1 … #define HOSTCC_SND_CON_IDX_2 … #define HOSTCC_SND_CON_IDX_3 … #define HOSTCC_SND_CON_IDX_4 … #define HOSTCC_SND_CON_IDX_5 … #define HOSTCC_SND_CON_IDX_6 … #define HOSTCC_SND_CON_IDX_7 … #define HOSTCC_SND_CON_IDX_8 … #define HOSTCC_SND_CON_IDX_9 … #define HOSTCC_SND_CON_IDX_10 … #define HOSTCC_SND_CON_IDX_11 … #define HOSTCC_SND_CON_IDX_12 … #define HOSTCC_SND_CON_IDX_13 … #define HOSTCC_SND_CON_IDX_14 … #define HOSTCC_SND_CON_IDX_15 … #define HOSTCC_STATBLCK_RING1 … /* 0x3d00 --> 0x3d80 unused */ #define HOSTCC_RXCOL_TICKS_VEC1 … #define HOSTCC_TXCOL_TICKS_VEC1 … #define HOSTCC_RXMAX_FRAMES_VEC1 … #define HOSTCC_TXMAX_FRAMES_VEC1 … #define HOSTCC_RXCOAL_MAXF_INT_VEC1 … #define HOSTCC_TXCOAL_MAXF_INT_VEC1 … /* 0x3d98 --> 0x4000 unused */ /* Memory arbiter control registers */ #define MEMARB_MODE … #define MEMARB_MODE_RESET … #define MEMARB_MODE_ENABLE … #define MEMARB_STATUS … #define MEMARB_TRAP_ADDR_LOW … #define MEMARB_TRAP_ADDR_HIGH … /* 0x4010 --> 0x4400 unused */ /* Buffer manager control registers */ #define BUFMGR_MODE … #define BUFMGR_MODE_RESET … #define BUFMGR_MODE_ENABLE … #define BUFMGR_MODE_ATTN_ENABLE … #define BUFMGR_MODE_BM_TEST … #define BUFMGR_MODE_MBLOW_ATTN_ENAB … #define BUFMGR_MODE_NO_TX_UNDERRUN … #define BUFMGR_STATUS … #define BUFMGR_STATUS_ERROR … #define BUFMGR_STATUS_MBLOW … #define BUFMGR_MB_POOL_ADDR … #define BUFMGR_MB_POOL_SIZE … #define BUFMGR_MB_RDMA_LOW_WATER … #define DEFAULT_MB_RDMA_LOW_WATER … #define DEFAULT_MB_RDMA_LOW_WATER_5705 … #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO … #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 … #define BUFMGR_MB_MACRX_LOW_WATER … #define DEFAULT_MB_MACRX_LOW_WATER … #define DEFAULT_MB_MACRX_LOW_WATER_5705 … #define DEFAULT_MB_MACRX_LOW_WATER_5906 … #define DEFAULT_MB_MACRX_LOW_WATER_57765 … #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO … #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 … #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 … #define BUFMGR_MB_HIGH_WATER … #define DEFAULT_MB_HIGH_WATER … #define DEFAULT_MB_HIGH_WATER_5705 … #define DEFAULT_MB_HIGH_WATER_5906 … #define DEFAULT_MB_HIGH_WATER_57765 … #define DEFAULT_MB_HIGH_WATER_JUMBO … #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 … #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 … #define BUFMGR_RX_MB_ALLOC_REQ … #define BUFMGR_MB_ALLOC_BIT … #define BUFMGR_RX_MB_ALLOC_RESP … #define BUFMGR_TX_MB_ALLOC_REQ … #define BUFMGR_TX_MB_ALLOC_RESP … #define BUFMGR_DMA_DESC_POOL_ADDR … #define BUFMGR_DMA_DESC_POOL_SIZE … #define BUFMGR_DMA_LOW_WATER … #define DEFAULT_DMA_LOW_WATER … #define BUFMGR_DMA_HIGH_WATER … #define DEFAULT_DMA_HIGH_WATER … #define BUFMGR_RX_DMA_ALLOC_REQ … #define BUFMGR_RX_DMA_ALLOC_RESP … #define BUFMGR_TX_DMA_ALLOC_REQ … #define BUFMGR_TX_DMA_ALLOC_RESP … #define BUFMGR_HWDIAG_0 … #define BUFMGR_HWDIAG_1 … #define BUFMGR_HWDIAG_2 … /* 0x4458 --> 0x4800 unused */ /* Read DMA control registers */ #define RDMAC_MODE … #define RDMAC_MODE_RESET … #define RDMAC_MODE_ENABLE … #define RDMAC_MODE_TGTABORT_ENAB … #define RDMAC_MODE_MSTABORT_ENAB … #define RDMAC_MODE_PARITYERR_ENAB … #define RDMAC_MODE_ADDROFLOW_ENAB … #define RDMAC_MODE_FIFOOFLOW_ENAB … #define RDMAC_MODE_FIFOURUN_ENAB … #define RDMAC_MODE_FIFOOREAD_ENAB … #define RDMAC_MODE_LNGREAD_ENAB … #define RDMAC_MODE_SPLIT_ENABLE … #define RDMAC_MODE_BD_SBD_CRPT_ENAB … #define RDMAC_MODE_SPLIT_RESET … #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB … #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB … #define RDMAC_MODE_FIFO_SIZE_128 … #define RDMAC_MODE_FIFO_LONG_BURST … #define RDMAC_MODE_JMB_2K_MMRR … #define RDMAC_MODE_MULT_DMA_RD_DIS … #define RDMAC_MODE_IPV4_LSO_EN … #define RDMAC_MODE_IPV6_LSO_EN … #define RDMAC_MODE_H2BNC_VLAN_DET … #define RDMAC_STATUS … #define RDMAC_STATUS_TGTABORT … #define RDMAC_STATUS_MSTABORT … #define RDMAC_STATUS_PARITYERR … #define RDMAC_STATUS_ADDROFLOW … #define RDMAC_STATUS_FIFOOFLOW … #define RDMAC_STATUS_FIFOURUN … #define RDMAC_STATUS_FIFOOREAD … #define RDMAC_STATUS_LNGREAD … /* 0x4808 --> 0x4890 unused */ #define TG3_RDMA_RSRVCTRL_REG2 … #define TG3_LSO_RD_DMA_CRPTEN_CTRL2 … #define TG3_RDMA_RSRVCTRL_REG … #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX … #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K … #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK … #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K … #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK … #define TG3_RDMA_RSRVCTRL_TXMRGN_320B … #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK … /* 0x4904 --> 0x4910 unused */ #define TG3_LSO_RD_DMA_CRPTEN_CTRL … #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K … #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K … #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719 … #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720 … /* 0x4914 --> 0x4be0 unused */ #define TG3_NUM_RDMA_CHANNELS … #define TG3_RDMA_LENGTH … /* Write DMA control registers */ #define WDMAC_MODE … #define WDMAC_MODE_RESET … #define WDMAC_MODE_ENABLE … #define WDMAC_MODE_TGTABORT_ENAB … #define WDMAC_MODE_MSTABORT_ENAB … #define WDMAC_MODE_PARITYERR_ENAB … #define WDMAC_MODE_ADDROFLOW_ENAB … #define WDMAC_MODE_FIFOOFLOW_ENAB … #define WDMAC_MODE_FIFOURUN_ENAB … #define WDMAC_MODE_FIFOOREAD_ENAB … #define WDMAC_MODE_LNGREAD_ENAB … #define WDMAC_MODE_RX_ACCEL … #define WDMAC_MODE_STATUS_TAG_FIX … #define WDMAC_MODE_BURST_ALL_DATA … #define WDMAC_STATUS … #define WDMAC_STATUS_TGTABORT … #define WDMAC_STATUS_MSTABORT … #define WDMAC_STATUS_PARITYERR … #define WDMAC_STATUS_ADDROFLOW … #define WDMAC_STATUS_FIFOOFLOW … #define WDMAC_STATUS_FIFOURUN … #define WDMAC_STATUS_FIFOOREAD … #define WDMAC_STATUS_LNGREAD … /* 0x4c08 --> 0x5000 unused */ /* Per-cpu register offsets (arm9) */ #define CPU_MODE … #define CPU_MODE_RESET … #define CPU_MODE_HALT … #define CPU_STATE … #define CPU_EVTMASK … /* 0xc --> 0x1c reserved */ #define CPU_PC … #define CPU_INSN … #define CPU_SPAD_UFLOW … #define CPU_WDOG_CLEAR … #define CPU_WDOG_VECTOR … #define CPU_WDOG_PC … #define CPU_HW_BP … /* 0x38 --> 0x44 unused */ #define CPU_WDOG_SAVED_STATE … #define CPU_LAST_BRANCH_ADDR … #define CPU_SPAD_UFLOW_SET … /* 0x50 --> 0x200 unused */ #define CPU_R0 … #define CPU_R1 … #define CPU_R2 … #define CPU_R3 … #define CPU_R4 … #define CPU_R5 … #define CPU_R6 … #define CPU_R7 … #define CPU_R8 … #define CPU_R9 … #define CPU_R10 … #define CPU_R11 … #define CPU_R12 … #define CPU_R13 … #define CPU_R14 … #define CPU_R15 … #define CPU_R16 … #define CPU_R17 … #define CPU_R18 … #define CPU_R19 … #define CPU_R20 … #define CPU_R21 … #define CPU_R22 … #define CPU_R23 … #define CPU_R24 … #define CPU_R25 … #define CPU_R26 … #define CPU_R27 … #define CPU_R28 … #define CPU_R29 … #define CPU_R30 … #define CPU_R31 … /* 0x280 --> 0x400 unused */ #define RX_CPU_BASE … #define RX_CPU_MODE … #define RX_CPU_STATE … #define RX_CPU_PGMCTR … #define RX_CPU_HWBKPT … #define TX_CPU_BASE … #define TX_CPU_MODE … #define TX_CPU_STATE … #define TX_CPU_PGMCTR … #define VCPU_STATUS … #define VCPU_STATUS_INIT_DONE … #define VCPU_STATUS_DRV_RESET … #define VCPU_CFGSHDW … #define VCPU_CFGSHDW_WOL_ENABLE … #define VCPU_CFGSHDW_WOL_MAGPKT … #define VCPU_CFGSHDW_ASPM_DBNC … /* Mailboxes */ #define GRCMBOX_BASE … #define GRCMBOX_INTERRUPT_0 … #define GRCMBOX_INTERRUPT_1 … #define GRCMBOX_INTERRUPT_2 … #define GRCMBOX_INTERRUPT_3 … #define GRCMBOX_GENERAL_0 … #define GRCMBOX_GENERAL_1 … #define GRCMBOX_GENERAL_2 … #define GRCMBOX_GENERAL_3 … #define GRCMBOX_GENERAL_4 … #define GRCMBOX_GENERAL_5 … #define GRCMBOX_GENERAL_6 … #define GRCMBOX_GENERAL_7 … #define GRCMBOX_RELOAD_STAT … #define GRCMBOX_RCVSTD_PROD_IDX … #define GRCMBOX_RCVJUMBO_PROD_IDX … #define GRCMBOX_RCVMINI_PROD_IDX … #define GRCMBOX_RCVRET_CON_IDX_0 … #define GRCMBOX_RCVRET_CON_IDX_1 … #define GRCMBOX_RCVRET_CON_IDX_2 … #define GRCMBOX_RCVRET_CON_IDX_3 … #define GRCMBOX_RCVRET_CON_IDX_4 … #define GRCMBOX_RCVRET_CON_IDX_5 … #define GRCMBOX_RCVRET_CON_IDX_6 … #define GRCMBOX_RCVRET_CON_IDX_7 … #define GRCMBOX_RCVRET_CON_IDX_8 … #define GRCMBOX_RCVRET_CON_IDX_9 … #define GRCMBOX_RCVRET_CON_IDX_10 … #define GRCMBOX_RCVRET_CON_IDX_11 … #define GRCMBOX_RCVRET_CON_IDX_12 … #define GRCMBOX_RCVRET_CON_IDX_13 … #define GRCMBOX_RCVRET_CON_IDX_14 … #define GRCMBOX_RCVRET_CON_IDX_15 … #define GRCMBOX_SNDHOST_PROD_IDX_0 … #define GRCMBOX_SNDHOST_PROD_IDX_1 … #define GRCMBOX_SNDHOST_PROD_IDX_2 … #define GRCMBOX_SNDHOST_PROD_IDX_3 … #define GRCMBOX_SNDHOST_PROD_IDX_4 … #define GRCMBOX_SNDHOST_PROD_IDX_5 … #define GRCMBOX_SNDHOST_PROD_IDX_6 … #define GRCMBOX_SNDHOST_PROD_IDX_7 … #define GRCMBOX_SNDHOST_PROD_IDX_8 … #define GRCMBOX_SNDHOST_PROD_IDX_9 … #define GRCMBOX_SNDHOST_PROD_IDX_10 … #define GRCMBOX_SNDHOST_PROD_IDX_11 … #define GRCMBOX_SNDHOST_PROD_IDX_12 … #define GRCMBOX_SNDHOST_PROD_IDX_13 … #define GRCMBOX_SNDHOST_PROD_IDX_14 … #define GRCMBOX_SNDHOST_PROD_IDX_15 … #define GRCMBOX_SNDNIC_PROD_IDX_0 … #define GRCMBOX_SNDNIC_PROD_IDX_1 … #define GRCMBOX_SNDNIC_PROD_IDX_2 … #define GRCMBOX_SNDNIC_PROD_IDX_3 … #define GRCMBOX_SNDNIC_PROD_IDX_4 … #define GRCMBOX_SNDNIC_PROD_IDX_5 … #define GRCMBOX_SNDNIC_PROD_IDX_6 … #define GRCMBOX_SNDNIC_PROD_IDX_7 … #define GRCMBOX_SNDNIC_PROD_IDX_8 … #define GRCMBOX_SNDNIC_PROD_IDX_9 … #define GRCMBOX_SNDNIC_PROD_IDX_10 … #define GRCMBOX_SNDNIC_PROD_IDX_11 … #define GRCMBOX_SNDNIC_PROD_IDX_12 … #define GRCMBOX_SNDNIC_PROD_IDX_13 … #define GRCMBOX_SNDNIC_PROD_IDX_14 … #define GRCMBOX_SNDNIC_PROD_IDX_15 … #define GRCMBOX_HIGH_PRIO_EV_VECTOR … #define GRCMBOX_HIGH_PRIO_EV_MASK … #define GRCMBOX_LOW_PRIO_EV_VEC … #define GRCMBOX_LOW_PRIO_EV_MASK … /* 0x5a10 --> 0x5c00 */ /* Flow Through queues */ #define FTQ_RESET … /* 0x5c04 --> 0x5c10 unused */ #define FTQ_DMA_NORM_READ_CTL … #define FTQ_DMA_NORM_READ_FULL_CNT … #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ … #define FTQ_DMA_NORM_READ_WRITE_PEEK … #define FTQ_DMA_HIGH_READ_CTL … #define FTQ_DMA_HIGH_READ_FULL_CNT … #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ … #define FTQ_DMA_HIGH_READ_WRITE_PEEK … #define FTQ_DMA_COMP_DISC_CTL … #define FTQ_DMA_COMP_DISC_FULL_CNT … #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ … #define FTQ_DMA_COMP_DISC_WRITE_PEEK … #define FTQ_SEND_BD_COMP_CTL … #define FTQ_SEND_BD_COMP_FULL_CNT … #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ … #define FTQ_SEND_BD_COMP_WRITE_PEEK … #define FTQ_SEND_DATA_INIT_CTL … #define FTQ_SEND_DATA_INIT_FULL_CNT … #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ … #define FTQ_SEND_DATA_INIT_WRITE_PEEK … #define FTQ_DMA_NORM_WRITE_CTL … #define FTQ_DMA_NORM_WRITE_FULL_CNT … #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ … #define FTQ_DMA_NORM_WRITE_WRITE_PEEK … #define FTQ_DMA_HIGH_WRITE_CTL … #define FTQ_DMA_HIGH_WRITE_FULL_CNT … #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ … #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK … #define FTQ_SWTYPE1_CTL … #define FTQ_SWTYPE1_FULL_CNT … #define FTQ_SWTYPE1_FIFO_ENQDEQ … #define FTQ_SWTYPE1_WRITE_PEEK … #define FTQ_SEND_DATA_COMP_CTL … #define FTQ_SEND_DATA_COMP_FULL_CNT … #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ … #define FTQ_SEND_DATA_COMP_WRITE_PEEK … #define FTQ_HOST_COAL_CTL … #define FTQ_HOST_COAL_FULL_CNT … #define FTQ_HOST_COAL_FIFO_ENQDEQ … #define FTQ_HOST_COAL_WRITE_PEEK … #define FTQ_MAC_TX_CTL … #define FTQ_MAC_TX_FULL_CNT … #define FTQ_MAC_TX_FIFO_ENQDEQ … #define FTQ_MAC_TX_WRITE_PEEK … #define FTQ_MB_FREE_CTL … #define FTQ_MB_FREE_FULL_CNT … #define FTQ_MB_FREE_FIFO_ENQDEQ … #define FTQ_MB_FREE_WRITE_PEEK … #define FTQ_RCVBD_COMP_CTL … #define FTQ_RCVBD_COMP_FULL_CNT … #define FTQ_RCVBD_COMP_FIFO_ENQDEQ … #define FTQ_RCVBD_COMP_WRITE_PEEK … #define FTQ_RCVLST_PLMT_CTL … #define FTQ_RCVLST_PLMT_FULL_CNT … #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ … #define FTQ_RCVLST_PLMT_WRITE_PEEK … #define FTQ_RCVDATA_INI_CTL … #define FTQ_RCVDATA_INI_FULL_CNT … #define FTQ_RCVDATA_INI_FIFO_ENQDEQ … #define FTQ_RCVDATA_INI_WRITE_PEEK … #define FTQ_RCVDATA_COMP_CTL … #define FTQ_RCVDATA_COMP_FULL_CNT … #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ … #define FTQ_RCVDATA_COMP_WRITE_PEEK … #define FTQ_SWTYPE2_CTL … #define FTQ_SWTYPE2_FULL_CNT … #define FTQ_SWTYPE2_FIFO_ENQDEQ … #define FTQ_SWTYPE2_WRITE_PEEK … /* 0x5d20 --> 0x6000 unused */ /* Message signaled interrupt registers */ #define MSGINT_MODE … #define MSGINT_MODE_RESET … #define MSGINT_MODE_ENABLE … #define MSGINT_MODE_ONE_SHOT_DISABLE … #define MSGINT_MODE_MULTIVEC_EN … #define MSGINT_STATUS … #define MSGINT_STATUS_MSI_REQ … #define MSGINT_FIFO … /* 0x600c --> 0x6400 unused */ /* DMA completion registers */ #define DMAC_MODE … #define DMAC_MODE_RESET … #define DMAC_MODE_ENABLE … /* 0x6404 --> 0x6800 unused */ /* GRC registers */ #define GRC_MODE … #define GRC_MODE_UPD_ON_COAL … #define GRC_MODE_BSWAP_NONFRM_DATA … #define GRC_MODE_WSWAP_NONFRM_DATA … #define GRC_MODE_BSWAP_DATA … #define GRC_MODE_WSWAP_DATA … #define GRC_MODE_BYTE_SWAP_B2HRX_DATA … #define GRC_MODE_WORD_SWAP_B2HRX_DATA … #define GRC_MODE_SPLITHDR … #define GRC_MODE_NOFRM_CRACKING … #define GRC_MODE_INCL_CRC … #define GRC_MODE_ALLOW_BAD_FRMS … #define GRC_MODE_NOIRQ_ON_SENDS … #define GRC_MODE_NOIRQ_ON_RCV … #define GRC_MODE_FORCE_PCI32BIT … #define GRC_MODE_B2HRX_ENABLE … #define GRC_MODE_HOST_STACKUP … #define GRC_MODE_HOST_SENDBDS … #define GRC_MODE_HTX2B_ENABLE … #define GRC_MODE_TIME_SYNC_ENABLE … #define GRC_MODE_NO_TX_PHDR_CSUM … #define GRC_MODE_NVRAM_WR_ENABLE … #define GRC_MODE_PCIE_TL_SEL … #define GRC_MODE_PCIE_PL_SEL … #define GRC_MODE_NO_RX_PHDR_CSUM … #define GRC_MODE_IRQ_ON_TX_CPU_ATTN … #define GRC_MODE_IRQ_ON_RX_CPU_ATTN … #define GRC_MODE_IRQ_ON_MAC_ATTN … #define GRC_MODE_IRQ_ON_DMA_ATTN … #define GRC_MODE_IRQ_ON_FLOW_ATTN … #define GRC_MODE_4X_NIC_SEND_RINGS … #define GRC_MODE_PCIE_DL_SEL … #define GRC_MODE_MCAST_FRM_ENABLE … #define GRC_MODE_PCIE_HI_1K_EN … #define GRC_MODE_PCIE_PORT_MASK … #define GRC_MISC_CFG … #define GRC_MISC_CFG_CORECLK_RESET … #define GRC_MISC_CFG_PRESCALAR_MASK … #define GRC_MISC_CFG_PRESCALAR_SHIFT … #define GRC_MISC_CFG_BOARD_ID_MASK … #define GRC_MISC_CFG_BOARD_ID_5700 … #define GRC_MISC_CFG_BOARD_ID_5701 … #define GRC_MISC_CFG_BOARD_ID_5702FE … #define GRC_MISC_CFG_BOARD_ID_5703 … #define GRC_MISC_CFG_BOARD_ID_5703S … #define GRC_MISC_CFG_BOARD_ID_5704 … #define GRC_MISC_CFG_BOARD_ID_5704CIOBE … #define GRC_MISC_CFG_BOARD_ID_5704_A2 … #define GRC_MISC_CFG_BOARD_ID_5788 … #define GRC_MISC_CFG_BOARD_ID_5788M … #define GRC_MISC_CFG_BOARD_ID_AC91002A1 … #define GRC_MISC_CFG_EPHY_IDDQ … #define GRC_MISC_CFG_KEEP_GPHY_POWER … #define GRC_LOCAL_CTRL … #define GRC_LCLCTRL_INT_ACTIVE … #define GRC_LCLCTRL_CLEARINT … #define GRC_LCLCTRL_SETINT … #define GRC_LCLCTRL_INT_ON_ATTN … #define GRC_LCLCTRL_GPIO_UART_SEL … #define GRC_LCLCTRL_USE_SIG_DETECT … #define GRC_LCLCTRL_USE_EXT_SIG_DETECT … #define GRC_LCLCTRL_GPIO_INPUT3 … #define GRC_LCLCTRL_GPIO_OE3 … #define GRC_LCLCTRL_GPIO_OUTPUT3 … #define GRC_LCLCTRL_GPIO_INPUT0 … #define GRC_LCLCTRL_GPIO_INPUT1 … #define GRC_LCLCTRL_GPIO_INPUT2 … #define GRC_LCLCTRL_GPIO_OE0 … #define GRC_LCLCTRL_GPIO_OE1 … #define GRC_LCLCTRL_GPIO_OE2 … #define GRC_LCLCTRL_GPIO_OUTPUT0 … #define GRC_LCLCTRL_GPIO_OUTPUT1 … #define GRC_LCLCTRL_GPIO_OUTPUT2 … #define GRC_LCLCTRL_EXTMEM_ENABLE … #define GRC_LCLCTRL_MEMSZ_MASK … #define GRC_LCLCTRL_MEMSZ_256K … #define GRC_LCLCTRL_MEMSZ_512K … #define GRC_LCLCTRL_MEMSZ_1M … #define GRC_LCLCTRL_MEMSZ_2M … #define GRC_LCLCTRL_MEMSZ_4M … #define GRC_LCLCTRL_MEMSZ_8M … #define GRC_LCLCTRL_MEMSZ_16M … #define GRC_LCLCTRL_BANK_SELECT … #define GRC_LCLCTRL_SSRAM_TYPE … #define GRC_LCLCTRL_AUTO_SEEPROM … #define GRC_TIMER … #define GRC_RX_CPU_EVENT … #define GRC_RX_CPU_DRIVER_EVENT … #define GRC_RX_TIMER_REF … #define GRC_RX_CPU_SEM … #define GRC_REMOTE_RX_CPU_ATTN … #define GRC_TX_CPU_EVENT … #define GRC_TX_TIMER_REF … #define GRC_TX_CPU_SEM … #define GRC_REMOTE_TX_CPU_ATTN … #define GRC_MEM_POWER_UP … #define GRC_EEPROM_ADDR … #define EEPROM_ADDR_WRITE … #define EEPROM_ADDR_READ … #define EEPROM_ADDR_COMPLETE … #define EEPROM_ADDR_FSM_RESET … #define EEPROM_ADDR_DEVID_MASK … #define EEPROM_ADDR_DEVID_SHIFT … #define EEPROM_ADDR_START … #define EEPROM_ADDR_CLKPERD_SHIFT … #define EEPROM_ADDR_ADDR_MASK … #define EEPROM_ADDR_ADDR_SHIFT … #define EEPROM_DEFAULT_CLOCK_PERIOD … #define EEPROM_CHIP_SIZE … #define GRC_EEPROM_DATA … #define GRC_EEPROM_CTRL … #define GRC_MDI_CTRL … #define GRC_SEEPROM_DELAY … /* 0x684c --> 0x6890 unused */ #define GRC_VCPU_EXT_CTRL … #define GRC_VCPU_EXT_CTRL_HALT_CPU … #define GRC_VCPU_EXT_CTRL_DISABLE_WOL … #define GRC_FASTBOOT_PC … #define TG3_EAV_REF_CLCK_LSB … #define TG3_EAV_REF_CLCK_MSB … #define TG3_EAV_REF_CLCK_CTL … #define TG3_EAV_REF_CLCK_CTL_STOP … #define TG3_EAV_REF_CLCK_CTL_RESUME … #define TG3_EAV_CTL_TSYNC_GPIO_MASK … #define TG3_EAV_CTL_TSYNC_WDOG0 … #define TG3_EAV_WATCHDOG0_LSB … #define TG3_EAV_WATCHDOG0_MSB … #define TG3_EAV_WATCHDOG0_EN … #define TG3_EAV_WATCHDOG_MSB_MASK … #define TG3_EAV_REF_CLK_CORRECT_CTL … #define TG3_EAV_REF_CLK_CORRECT_EN … #define TG3_EAV_REF_CLK_CORRECT_NEG … #define TG3_EAV_REF_CLK_CORRECT_MASK … /* 0x692c --> 0x7000 unused */ /* NVRAM Control registers */ #define NVRAM_CMD … #define NVRAM_CMD_RESET … #define NVRAM_CMD_DONE … #define NVRAM_CMD_GO … #define NVRAM_CMD_WR … #define NVRAM_CMD_RD … #define NVRAM_CMD_ERASE … #define NVRAM_CMD_FIRST … #define NVRAM_CMD_LAST … #define NVRAM_CMD_WREN … #define NVRAM_CMD_WRDI … #define NVRAM_STAT … #define NVRAM_WRDATA … #define NVRAM_ADDR … #define NVRAM_ADDR_MSK … #define NVRAM_RDDATA … #define NVRAM_CFG1 … #define NVRAM_CFG1_FLASHIF_ENAB … #define NVRAM_CFG1_BUFFERED_MODE … #define NVRAM_CFG1_PASS_THRU … #define NVRAM_CFG1_STATUS_BITS … #define NVRAM_CFG1_BIT_BANG … #define NVRAM_CFG1_FLASH_SIZE … #define NVRAM_CFG1_COMPAT_BYPASS … #define NVRAM_CFG1_VENDOR_MASK … #define FLASH_VENDOR_ATMEL_EEPROM … #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED … #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED … #define FLASH_VENDOR_ST … #define FLASH_VENDOR_SAIFUN … #define FLASH_VENDOR_SST_SMALL … #define FLASH_VENDOR_SST_LARGE … #define NVRAM_CFG1_5752VENDOR_MASK … #define NVRAM_CFG1_5762VENDOR_MASK … #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ … #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ … #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED … #define FLASH_5752VENDOR_ST_M45PE10 … #define FLASH_5752VENDOR_ST_M45PE20 … #define FLASH_5752VENDOR_ST_M45PE40 … #define FLASH_5755VENDOR_ATMEL_FLASH_1 … #define FLASH_5755VENDOR_ATMEL_FLASH_2 … #define FLASH_5755VENDOR_ATMEL_FLASH_3 … #define FLASH_5755VENDOR_ATMEL_FLASH_4 … #define FLASH_5755VENDOR_ATMEL_FLASH_5 … #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ … #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ … #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ … #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ … #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ … #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ … #define FLASH_5761VENDOR_ATMEL_MDB021D … #define FLASH_5761VENDOR_ATMEL_MDB041D … #define FLASH_5761VENDOR_ATMEL_MDB081D … #define FLASH_5761VENDOR_ATMEL_MDB161D … #define FLASH_5761VENDOR_ATMEL_ADB021D … #define FLASH_5761VENDOR_ATMEL_ADB041D … #define FLASH_5761VENDOR_ATMEL_ADB081D … #define FLASH_5761VENDOR_ATMEL_ADB161D … #define FLASH_5761VENDOR_ST_M_M45PE20 … #define FLASH_5761VENDOR_ST_M_M45PE40 … #define FLASH_5761VENDOR_ST_M_M45PE80 … #define FLASH_5761VENDOR_ST_M_M45PE16 … #define FLASH_5761VENDOR_ST_A_M45PE20 … #define FLASH_5761VENDOR_ST_A_M45PE40 … #define FLASH_5761VENDOR_ST_A_M45PE80 … #define FLASH_5761VENDOR_ST_A_M45PE16 … #define FLASH_57780VENDOR_ATMEL_AT45DB011D … #define FLASH_57780VENDOR_ATMEL_AT45DB011B … #define FLASH_57780VENDOR_ATMEL_AT45DB021D … #define FLASH_57780VENDOR_ATMEL_AT45DB021B … #define FLASH_57780VENDOR_ATMEL_AT45DB041D … #define FLASH_57780VENDOR_ATMEL_AT45DB041B … #define FLASH_5717VENDOR_ATMEL_EEPROM … #define FLASH_5717VENDOR_MICRO_EEPROM … #define FLASH_5717VENDOR_ATMEL_MDB011D … #define FLASH_5717VENDOR_ATMEL_MDB021D … #define FLASH_5717VENDOR_ST_M_M25PE10 … #define FLASH_5717VENDOR_ST_M_M25PE20 … #define FLASH_5717VENDOR_ST_M_M45PE10 … #define FLASH_5717VENDOR_ST_M_M45PE20 … #define FLASH_5717VENDOR_ATMEL_ADB011B … #define FLASH_5717VENDOR_ATMEL_ADB021B … #define FLASH_5717VENDOR_ATMEL_ADB011D … #define FLASH_5717VENDOR_ATMEL_ADB021D … #define FLASH_5717VENDOR_ST_A_M25PE10 … #define FLASH_5717VENDOR_ST_A_M25PE20 … #define FLASH_5717VENDOR_ST_A_M45PE10 … #define FLASH_5717VENDOR_ST_A_M45PE20 … #define FLASH_5717VENDOR_ATMEL_45USPT … #define FLASH_5717VENDOR_ST_25USPT … #define FLASH_5717VENDOR_ST_45USPT … #define FLASH_5720_EEPROM_HD … #define FLASH_5720_EEPROM_LD … #define FLASH_5762_EEPROM_HD … #define FLASH_5762_EEPROM_LD … #define FLASH_5762_MX25L_100 … #define FLASH_5762_MX25L_200 … #define FLASH_5762_MX25L_400 … #define FLASH_5762_MX25L_800 … #define FLASH_5762_MX25L_160_320 … #define FLASH_5720VENDOR_M_ATMEL_DB011D … #define FLASH_5720VENDOR_M_ATMEL_DB021D … #define FLASH_5720VENDOR_M_ATMEL_DB041D … #define FLASH_5720VENDOR_M_ATMEL_DB081D … #define FLASH_5720VENDOR_M_ST_M25PE10 … #define FLASH_5720VENDOR_M_ST_M25PE20 … #define FLASH_5720VENDOR_M_ST_M25PE40 … #define FLASH_5720VENDOR_M_ST_M25PE80 … #define FLASH_5720VENDOR_M_ST_M45PE10 … #define FLASH_5720VENDOR_M_ST_M45PE20 … #define FLASH_5720VENDOR_M_ST_M45PE40 … #define FLASH_5720VENDOR_M_ST_M45PE80 … #define FLASH_5720VENDOR_A_ATMEL_DB011B … #define FLASH_5720VENDOR_A_ATMEL_DB021B … #define FLASH_5720VENDOR_A_ATMEL_DB041B … #define FLASH_5720VENDOR_A_ATMEL_DB011D … #define FLASH_5720VENDOR_A_ATMEL_DB021D … #define FLASH_5720VENDOR_A_ATMEL_DB041D … #define FLASH_5720VENDOR_A_ATMEL_DB081D … #define FLASH_5720VENDOR_A_ST_M25PE10 … #define FLASH_5720VENDOR_A_ST_M25PE20 … #define FLASH_5720VENDOR_A_ST_M25PE40 … #define FLASH_5720VENDOR_A_ST_M25PE80 … #define FLASH_5720VENDOR_A_ST_M45PE10 … #define FLASH_5720VENDOR_A_ST_M45PE20 … #define FLASH_5720VENDOR_A_ST_M45PE40 … #define FLASH_5720VENDOR_A_ST_M45PE80 … #define FLASH_5720VENDOR_ATMEL_45USPT … #define FLASH_5720VENDOR_ST_25USPT … #define FLASH_5720VENDOR_ST_45USPT … #define NVRAM_CFG1_5752PAGE_SIZE_MASK … #define FLASH_5752PAGE_SIZE_256 … #define FLASH_5752PAGE_SIZE_512 … #define FLASH_5752PAGE_SIZE_1K … #define FLASH_5752PAGE_SIZE_2K … #define FLASH_5752PAGE_SIZE_4K … #define FLASH_5752PAGE_SIZE_264 … #define FLASH_5752PAGE_SIZE_528 … #define NVRAM_CFG2 … #define NVRAM_CFG3 … #define NVRAM_SWARB … #define SWARB_REQ_SET0 … #define SWARB_REQ_SET1 … #define SWARB_REQ_SET2 … #define SWARB_REQ_SET3 … #define SWARB_REQ_CLR0 … #define SWARB_REQ_CLR1 … #define SWARB_REQ_CLR2 … #define SWARB_REQ_CLR3 … #define SWARB_GNT0 … #define SWARB_GNT1 … #define SWARB_GNT2 … #define SWARB_GNT3 … #define SWARB_REQ0 … #define SWARB_REQ1 … #define SWARB_REQ2 … #define SWARB_REQ3 … #define NVRAM_ACCESS … #define ACCESS_ENABLE … #define ACCESS_WR_ENABLE … #define NVRAM_WRITE1 … /* 0x702c unused */ #define NVRAM_ADDR_LOCKOUT … #define NVRAM_AUTOSENSE_STATUS … #define AUTOSENSE_DEVID … #define AUTOSENSE_DEVID_MASK … #define AUTOSENSE_SIZE_IN_MB … /* 0x703c --> 0x7500 unused */ #define OTP_MODE … #define OTP_MODE_OTP_THRU_GRC … #define OTP_CTRL … #define OTP_CTRL_OTP_PROG_ENABLE … #define OTP_CTRL_OTP_CMD_READ … #define OTP_CTRL_OTP_CMD_INIT … #define OTP_CTRL_OTP_CMD_START … #define OTP_STATUS … #define OTP_STATUS_CMD_DONE … #define OTP_ADDRESS … #define OTP_ADDRESS_MAGIC1 … #define OTP_ADDRESS_MAGIC2 … /* 0x7510 unused */ #define OTP_READ_DATA … /* 0x7518 --> 0x7c04 unused */ #define PCIE_TRANSACTION_CFG … #define PCIE_TRANS_CFG_1SHOT_MSI … #define PCIE_TRANS_CFG_LOM … /* 0x7c08 --> 0x7d28 unused */ #define PCIE_PWR_MGMT_THRESH … #define PCIE_PWR_MGMT_L1_THRESH_MSK … #define PCIE_PWR_MGMT_L1_THRESH_4MS … #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN … /* 0x7d2c --> 0x7d54 unused */ #define TG3_PCIE_LNKCTL … #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN … #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS … /* 0x7d58 --> 0x7e70 unused */ #define TG3_PCIE_PHY_TSTCTL … #define TG3_PCIE_PHY_TSTCTL_PCIE10 … #define TG3_PCIE_PHY_TSTCTL_PSCRAM … #define TG3_PCIE_EIDLE_DELAY … #define TG3_PCIE_EIDLE_DELAY_MASK … #define TG3_PCIE_EIDLE_DELAY_13_CLKS … /* 0x7e74 --> 0x8000 unused */ /* Alternate PCIE definitions */ #define TG3_PCIE_TLDLPL_PORT … #define TG3_PCIE_DL_LO_FTSMAX … #define TG3_PCIE_DL_LO_FTSMAX_MSK … #define TG3_PCIE_DL_LO_FTSMAX_VAL … #define TG3_PCIE_PL_LO_PHYCTL1 … #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN … #define TG3_PCIE_PL_LO_PHYCTL5 … #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ … #define TG3_REG_BLK_SIZE … /* OTP bit definitions */ #define TG3_OTP_AGCTGT_MASK … #define TG3_OTP_AGCTGT_SHIFT … #define TG3_OTP_HPFFLTR_MASK … #define TG3_OTP_HPFFLTR_SHIFT … #define TG3_OTP_HPFOVER_MASK … #define TG3_OTP_HPFOVER_SHIFT … #define TG3_OTP_LPFDIS_MASK … #define TG3_OTP_LPFDIS_SHIFT … #define TG3_OTP_VDAC_MASK … #define TG3_OTP_VDAC_SHIFT … #define TG3_OTP_10BTAMP_MASK … #define TG3_OTP_10BTAMP_SHIFT … #define TG3_OTP_ROFF_MASK … #define TG3_OTP_ROFF_SHIFT … #define TG3_OTP_RCOFF_MASK … #define TG3_OTP_RCOFF_SHIFT … #define TG3_OTP_DEFAULT … /* Hardware Legacy NVRAM layout */ #define TG3_NVM_VPD_OFF … #define TG3_NVM_VPD_LEN … /* Hardware Selfboot NVRAM layout */ #define TG3_NVM_HWSB_CFG1 … #define TG3_NVM_HWSB_CFG1_MAJMSK … #define TG3_NVM_HWSB_CFG1_MAJSFT … #define TG3_NVM_HWSB_CFG1_MINMSK … #define TG3_NVM_HWSB_CFG1_MINSFT … #define TG3_EEPROM_MAGIC … #define TG3_EEPROM_MAGIC_FW … #define TG3_EEPROM_MAGIC_FW_MSK … #define TG3_EEPROM_SB_FORMAT_MASK … #define TG3_EEPROM_SB_FORMAT_1 … #define TG3_EEPROM_SB_REVISION_MASK … #define TG3_EEPROM_SB_REVISION_0 … #define TG3_EEPROM_SB_REVISION_2 … #define TG3_EEPROM_SB_REVISION_3 … #define TG3_EEPROM_SB_REVISION_4 … #define TG3_EEPROM_SB_REVISION_5 … #define TG3_EEPROM_SB_REVISION_6 … #define TG3_EEPROM_MAGIC_HW … #define TG3_EEPROM_MAGIC_HW_MSK … #define TG3_NVM_DIR_START … #define TG3_NVM_DIR_END … #define TG3_NVM_DIRENT_SIZE … #define TG3_NVM_DIRTYPE_SHIFT … #define TG3_NVM_DIRTYPE_LENMSK … #define TG3_NVM_DIRTYPE_ASFINI … #define TG3_NVM_DIRTYPE_EXTVPD … #define TG3_NVM_PTREV_BCVER … #define TG3_NVM_BCVER_MAJMSK … #define TG3_NVM_BCVER_MAJSFT … #define TG3_NVM_BCVER_MINMSK … #define TG3_EEPROM_SB_F1R0_EDH_OFF … #define TG3_EEPROM_SB_F1R2_EDH_OFF … #define TG3_EEPROM_SB_F1R2_MBA_OFF … #define TG3_EEPROM_SB_F1R3_EDH_OFF … #define TG3_EEPROM_SB_F1R4_EDH_OFF … #define TG3_EEPROM_SB_F1R5_EDH_OFF … #define TG3_EEPROM_SB_F1R6_EDH_OFF … #define TG3_EEPROM_SB_EDH_MAJ_MASK … #define TG3_EEPROM_SB_EDH_MAJ_SHFT … #define TG3_EEPROM_SB_EDH_MIN_MASK … #define TG3_EEPROM_SB_EDH_BLD_MASK … #define TG3_EEPROM_SB_EDH_BLD_SHFT … /* 32K Window into NIC internal memory */ #define NIC_SRAM_WIN_BASE … /* Offsets into first 32k of NIC internal memory. */ #define NIC_SRAM_PAGE_ZERO … #define NIC_SRAM_SEND_RCB … #define NIC_SRAM_RCV_RET_RCB … #define NIC_SRAM_STATS_BLK … #define NIC_SRAM_STATUS_BLK … #define NIC_SRAM_FIRMWARE_MBOX … #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 … #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 … #define NIC_SRAM_DATA_SIG … #define NIC_SRAM_DATA_SIG_MAGIC … #define NIC_SRAM_DATA_CFG … #define NIC_SRAM_DATA_CFG_LED_MODE_MASK … #define NIC_SRAM_DATA_CFG_LED_MODE_MAC … #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 … #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 … #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK … #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN … #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER … #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER … #define NIC_SRAM_DATA_CFG_WOL_ENABLE … #define NIC_SRAM_DATA_CFG_ASF_ENABLE … #define NIC_SRAM_DATA_CFG_EEPROM_WP … #define NIC_SRAM_DATA_CFG_MINI_PCI … #define NIC_SRAM_DATA_CFG_FIBER_WOL … #define NIC_SRAM_DATA_CFG_NO_GPIO2 … #define NIC_SRAM_DATA_CFG_APE_ENABLE … #define NIC_SRAM_DATA_VER … #define NIC_SRAM_DATA_VER_SHIFT … #define NIC_SRAM_DATA_PHY_ID … #define NIC_SRAM_DATA_PHY_ID1_MASK … #define NIC_SRAM_DATA_PHY_ID2_MASK … #define NIC_SRAM_FW_CMD_MBOX … #define FWCMD_NICDRV_ALIVE … #define FWCMD_NICDRV_PAUSE_FW … #define FWCMD_NICDRV_IPV4ADDR_CHG … #define FWCMD_NICDRV_IPV6ADDR_CHG … #define FWCMD_NICDRV_FIX_DMAR … #define FWCMD_NICDRV_FIX_DMAW … #define FWCMD_NICDRV_LINK_UPDATE … #define FWCMD_NICDRV_ALIVE2 … #define FWCMD_NICDRV_ALIVE3 … #define NIC_SRAM_FW_CMD_LEN_MBOX … #define NIC_SRAM_FW_CMD_DATA_MBOX … #define NIC_SRAM_FW_ASF_STATUS_MBOX … #define NIC_SRAM_FW_DRV_STATE_MBOX … #define DRV_STATE_START … #define DRV_STATE_START_DONE … #define DRV_STATE_UNLOAD … #define DRV_STATE_UNLOAD_DONE … #define DRV_STATE_WOL … #define DRV_STATE_SUSPEND … #define NIC_SRAM_FW_RESET_TYPE_MBOX … #define NIC_SRAM_MAC_ADDR_HIGH_MBOX … #define NIC_SRAM_MAC_ADDR_LOW_MBOX … #define NIC_SRAM_WOL_MBOX … #define WOL_SIGNATURE … #define WOL_DRV_STATE_SHUTDOWN … #define WOL_DRV_WOL … #define WOL_SET_MAGIC_PKT … #define NIC_SRAM_DATA_CFG_2 … #define NIC_SRAM_DATA_CFG_2_APD_EN … #define SHASTA_EXT_LED_MODE_MASK … #define SHASTA_EXT_LED_LEGACY … #define SHASTA_EXT_LED_SHARED … #define SHASTA_EXT_LED_MAC … #define SHASTA_EXT_LED_COMBO … #define NIC_SRAM_DATA_CFG_3 … #define NIC_SRAM_ASPM_DEBOUNCE … #define NIC_SRAM_LNK_FLAP_AVOID … #define NIC_SRAM_1G_ON_VAUX_OK … #define NIC_SRAM_DATA_CFG_4 … #define NIC_SRAM_GMII_MODE … #define NIC_SRAM_RGMII_INBAND_DISABLE … #define NIC_SRAM_RGMII_EXT_IBND_RX_EN … #define NIC_SRAM_RGMII_EXT_IBND_TX_EN … #define NIC_SRAM_CPMU_STATUS … #define NIC_SRAM_CPMUSTAT_SIG … #define NIC_SRAM_CPMUSTAT_SIG_MSK … #define NIC_SRAM_DATA_CFG_5 … #define NIC_SRAM_DISABLE_1G_HALF_ADV … #define NIC_SRAM_RX_MINI_BUFFER_DESC … #define NIC_SRAM_DMA_DESC_POOL_BASE … #define NIC_SRAM_DMA_DESC_POOL_SIZE … #define NIC_SRAM_TX_BUFFER_DESC … #define NIC_SRAM_RX_BUFFER_DESC … #define NIC_SRAM_RX_JUMBO_BUFFER_DESC … #define NIC_SRAM_MBUF_POOL_BASE … #define NIC_SRAM_MBUF_POOL_SIZE96 … #define NIC_SRAM_MBUF_POOL_SIZE64 … #define NIC_SRAM_MBUF_POOL_BASE5705 … #define NIC_SRAM_MBUF_POOL_SIZE5705 … #define TG3_SRAM_RXCPU_SCRATCH_BASE_57766 … #define TG3_SRAM_RXCPU_SCRATCH_SIZE_57766 … #define TG3_57766_FW_BASE_ADDR … #define TG3_57766_FW_HANDSHAKE … #define TG3_SBROM_IN_SERVICE_LOOP … #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 … #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 … #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 … #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 … #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 … /* Currently this is fixed. */ #define TG3_PHY_MII_ADDR … /*** Tigon3 specific PHY MII registers. ***/ #define MII_TG3_MMD_CTRL … #define MII_TG3_MMD_CTRL_DATA_NOINC … #define MII_TG3_MMD_ADDRESS … #define MII_TG3_EXT_CTRL … #define MII_TG3_EXT_CTRL_FIFO_ELASTIC … #define MII_TG3_EXT_CTRL_LNK3_LED_MODE … #define MII_TG3_EXT_CTRL_FORCE_LED_OFF … #define MII_TG3_EXT_CTRL_TBI … #define MII_TG3_EXT_STAT … #define MII_TG3_EXT_STAT_MDIX … #define MII_TG3_EXT_STAT_LPASS … #define MII_TG3_RXR_COUNTERS … #define MII_TG3_DSP_RW_PORT … #define MII_TG3_DSP_CONTROL … #define MII_TG3_DSP_ADDRESS … #define MII_TG3_DSP_TAP1 … #define MII_TG3_DSP_TAP1_AGCTGT_DFLT … #define MII_TG3_DSP_TAP26 … #define MII_TG3_DSP_TAP26_ALNOKO … #define MII_TG3_DSP_TAP26_RMRXSTO … #define MII_TG3_DSP_TAP26_OPCSINPT … #define MII_TG3_DSP_AADJ1CH0 … #define MII_TG3_DSP_CH34TP2 … #define MII_TG3_DSP_CH34TP2_HIBW01 … #define MII_TG3_DSP_AADJ1CH3 … #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ … #define MII_TG3_DSP_EXP1_INT_STAT … #define MII_TG3_DSP_EXP8 … #define MII_TG3_DSP_EXP8_REJ2MHz … #define MII_TG3_DSP_EXP8_AEDW … #define MII_TG3_DSP_EXP75 … #define MII_TG3_DSP_EXP96 … #define MII_TG3_DSP_EXP97 … #define MII_TG3_AUX_CTRL … #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL … #define MII_TG3_AUXCTL_ACTL_TX_6DB … #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA … #define MII_TG3_AUXCTL_ACTL_EXTPKTLEN … #define MII_TG3_AUXCTL_ACTL_EXTLOOPBK … #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL … #define MII_TG3_AUXCTL_PCTL_WOL_EN … #define MII_TG3_AUXCTL_PCTL_100TX_LPWR … #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE … #define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC … #define MII_TG3_AUXCTL_PCTL_VREG_11V … #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST … #define MII_TG3_AUXCTL_SHDWSEL_MISC … #define MII_TG3_AUXCTL_MISC_WIRESPD_EN … #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX … #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT … #define MII_TG3_AUXCTL_MISC_WREN … #define MII_TG3_AUX_STAT … #define MII_TG3_AUX_STAT_LPASS … #define MII_TG3_AUX_STAT_SPDMASK … #define MII_TG3_AUX_STAT_10HALF … #define MII_TG3_AUX_STAT_10FULL … #define MII_TG3_AUX_STAT_100HALF … #define MII_TG3_AUX_STAT_100_4 … #define MII_TG3_AUX_STAT_100FULL … #define MII_TG3_AUX_STAT_1000HALF … #define MII_TG3_AUX_STAT_1000FULL … #define MII_TG3_AUX_STAT_100 … #define MII_TG3_AUX_STAT_FULL … #define MII_TG3_ISTAT … #define MII_TG3_IMASK … /* ISTAT/IMASK event bits */ #define MII_TG3_INT_LINKCHG … #define MII_TG3_INT_SPEEDCHG … #define MII_TG3_INT_DUPLEXCHG … #define MII_TG3_INT_ANEG_PAGE_RX … #define MII_TG3_MISC_SHDW … #define MII_TG3_MISC_SHDW_WREN … #define MII_TG3_MISC_SHDW_APD_WKTM_84MS … #define MII_TG3_MISC_SHDW_APD_ENABLE … #define MII_TG3_MISC_SHDW_APD_SEL … #define MII_TG3_MISC_SHDW_SCR5_C125OE … #define MII_TG3_MISC_SHDW_SCR5_DLLAPD … #define MII_TG3_MISC_SHDW_SCR5_SDTL … #define MII_TG3_MISC_SHDW_SCR5_DLPTLM … #define MII_TG3_MISC_SHDW_SCR5_LPED … #define MII_TG3_MISC_SHDW_SCR5_SEL … #define MII_TG3_TEST1 … #define MII_TG3_TEST1_TRIM_EN … #define MII_TG3_TEST1_CRC_EN … /* Clause 45 expansion registers */ #define TG3_CL45_D7_EEERES_STAT … #define TG3_CL45_D7_EEERES_STAT_LP_100TX … #define TG3_CL45_D7_EEERES_STAT_LP_1000T … /* Fast Ethernet Tranceiver definitions */ #define MII_TG3_FET_PTEST … #define MII_TG3_FET_PTEST_TRIM_SEL … #define MII_TG3_FET_PTEST_TRIM_2 … #define MII_TG3_FET_PTEST_FRC_TX_LINK … #define MII_TG3_FET_PTEST_FRC_TX_LOCK … #define MII_TG3_FET_GEN_STAT … #define MII_TG3_FET_GEN_STAT_MDIXSTAT … #define MII_TG3_FET_TEST … #define MII_TG3_FET_SHADOW_EN … #define MII_TG3_FET_SHDW_MISCCTRL … #define MII_TG3_FET_SHDW_MISCCTRL_MDIX … #define MII_TG3_FET_SHDW_AUXMODE4 … #define MII_TG3_FET_SHDW_AUXMODE4_SBPD … #define MII_TG3_FET_SHDW_AUXSTAT2 … #define MII_TG3_FET_SHDW_AUXSTAT2_APD … /* Serdes PHY Register Definitions */ #define SERDES_TG3_1000X_STATUS … #define SERDES_TG3_SGMII_MODE … #define SERDES_TG3_LINK_UP … #define SERDES_TG3_FULL_DUPLEX … #define SERDES_TG3_SPEED_100 … #define SERDES_TG3_SPEED_1000 … /* APE registers. Accessible through BAR1 */ #define TG3_APE_GPIO_MSG … #define TG3_APE_GPIO_MSG_SHIFT … #define TG3_APE_EVENT … #define APE_EVENT_1 … #define TG3_APE_LOCK_REQ … #define APE_LOCK_REQ_DRIVER … #define TG3_APE_LOCK_GRANT … #define APE_LOCK_GRANT_DRIVER … #define TG3_APE_OTP_CTRL … #define APE_OTP_CTRL_PROG_EN … #define APE_OTP_CTRL_CMD_RD … #define APE_OTP_CTRL_START … #define TG3_APE_OTP_STATUS … #define APE_OTP_STATUS_CMD_DONE … #define TG3_APE_OTP_ADDR … #define APE_OTP_ADDR_CPU_ENABLE … #define TG3_APE_OTP_RD_DATA … #define OTP_ADDRESS_MAGIC0 … #define TG3_OTP_MAGIC0_VALID(val) … /* APE shared memory. Accessible through BAR1 */ #define TG3_APE_SHMEM_BASE … #define TG3_APE_SEG_SIG … #define APE_SEG_SIG_MAGIC … #define TG3_APE_FW_STATUS … #define APE_FW_STATUS_READY … #define TG3_APE_FW_FEATURES … #define TG3_APE_FW_FEATURE_NCSI … #define TG3_APE_FW_VERSION … #define APE_FW_VERSION_MAJMSK … #define APE_FW_VERSION_MAJSFT … #define APE_FW_VERSION_MINMSK … #define APE_FW_VERSION_MINSFT … #define APE_FW_VERSION_REVMSK … #define APE_FW_VERSION_REVSFT … #define APE_FW_VERSION_BLDMSK … #define TG3_APE_SEG_MSG_BUF_OFF … #define TG3_APE_SEG_MSG_BUF_LEN … #define TG3_APE_HOST_SEG_SIG … #define APE_HOST_SEG_SIG_MAGIC … #define TG3_APE_HOST_SEG_LEN … #define APE_HOST_SEG_LEN_MAGIC … #define TG3_APE_HOST_INIT_COUNT … #define TG3_APE_HOST_DRIVER_ID … #define APE_HOST_DRIVER_ID_LINUX … #define APE_HOST_DRIVER_ID_MAGIC(maj, min) … #define TG3_APE_HOST_BEHAVIOR … #define APE_HOST_BEHAV_NO_PHYLOCK … #define TG3_APE_HOST_HEARTBEAT_INT_MS … #define APE_HOST_HEARTBEAT_INT_DISABLE … #define APE_HOST_HEARTBEAT_INT_5SEC … #define TG3_APE_HOST_HEARTBEAT_COUNT … #define TG3_APE_HOST_DRVR_STATE … #define TG3_APE_HOST_DRVR_STATE_START … #define TG3_APE_HOST_DRVR_STATE_UNLOAD … #define TG3_APE_HOST_DRVR_STATE_WOL … #define TG3_APE_HOST_WOL_SPEED … #define TG3_APE_HOST_WOL_SPEED_AUTO … #define TG3_APE_EVENT_STATUS … #define APE_EVENT_STATUS_DRIVER_EVNT … #define APE_EVENT_STATUS_STATE_CHNGE … #define APE_EVENT_STATUS_SCRTCHPD_READ … #define APE_EVENT_STATUS_SCRTCHPD_WRITE … #define APE_EVENT_STATUS_STATE_START … #define APE_EVENT_STATUS_STATE_UNLOAD … #define APE_EVENT_STATUS_STATE_WOL … #define APE_EVENT_STATUS_STATE_SUSPEND … #define APE_EVENT_STATUS_EVENT_PENDING … #define TG3_APE_PER_LOCK_REQ … #define APE_LOCK_PER_REQ_DRIVER … #define TG3_APE_PER_LOCK_GRANT … #define APE_PER_LOCK_GRANT_DRIVER … /* APE convenience enumerations. */ #define TG3_APE_LOCK_PHY0 … #define TG3_APE_LOCK_GRC … #define TG3_APE_LOCK_PHY1 … #define TG3_APE_LOCK_PHY2 … #define TG3_APE_LOCK_MEM … #define TG3_APE_LOCK_PHY3 … #define TG3_APE_LOCK_GPIO … #define TG3_APE_HB_INTERVAL … #define TG3_EEPROM_SB_F1R2_MBA_OFF … /* There are two ways to manage the TX descriptors on the tigon3. * Either the descriptors are in host DMA'able memory, or they * exist only in the cards on-chip SRAM. All 16 send bds are under * the same mode, they may not be configured individually. * * This driver always uses host memory TX descriptors. * * To use host memory TX descriptors: * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. * 2) Allocate DMA'able memory. * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory * obtained in step 2 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number * of TX descriptors. Leave flags field clear. * 4) Access TX descriptors via host memory. The chip * will refetch into local SRAM as needed when producer * index mailboxes are updated. * * To use on-chip TX descriptors: * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. * Make sure GRC_MODE_HOST_SENDBDS is clear. * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: * a) Set TG3_BDINFO_HOST_ADDR to zero. * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. * 3) Access TX descriptors directly in on-chip SRAM * using normal {read,write}l(). (and not using * pointer dereferencing of ioremap()'d memory like * the broken Broadcom driver does) * * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. */ struct tg3_tx_buffer_desc { … }; #define TXD_ADDR … #define TXD_LEN_FLAGS … #define TXD_VLAN_TAG … #define TXD_SIZE … struct tg3_rx_buffer_desc { … }; struct tg3_ext_rx_buffer_desc { … }; /* We only use this when testing out the DMA engine * at probe time. This is the internal format of buffer * descriptors used by the chip at NIC_SRAM_DMA_DESCS. */ struct tg3_internal_buffer_desc { … }; #define TG3_HW_STATUS_SIZE … struct tg3_hw_status { … }; tg3_stat64_t; struct tg3_hw_stats { … }; #define TG3_SD_NUM_RECS … #define TG3_OCIR_LEN … #define TG3_OCIR_SIG_MAGIC … #define TG3_OCIR_FLAG_ACTIVE … #define TG3_TEMP_CAUTION_OFFSET … #define TG3_TEMP_MAX_OFFSET … #define TG3_TEMP_SENSOR_OFFSET … struct tg3_ocir { … }; /* 'mapping' is superfluous as the chip does not write into * the tx/rx post rings so we could just fetch it from there. * But the cache behavior is better how we are doing it now. * * This driver uses new build_skb() API : * RX ring buffer contains pointer to kmalloc() data only, * skb are built only after Hardware filled the frame. */ struct ring_info { … }; struct tg3_tx_ring_info { … }; struct tg3_link_config { … }; struct tg3_bufmgr_config { … }; struct tg3_ethtool_stats { … }; struct tg3_rx_prodring_set { … }; #define TG3_RSS_MAX_NUM_QS … #define TG3_IRQ_MAX_VECS_RSS … #define TG3_IRQ_MAX_VECS … struct tg3_napi { … }; enum TG3_FLAGS { … }; struct tg3_firmware_hdr { … }; #define TG3_FW_HDR_LEN … struct tg3 { … }; /* Accessor macros for chip and asic attributes * * nb: Using static inlines equivalent to the accessor macros generates * larger object code with gcc 4.7. * Using statement expression macros to check tp with * typecheck(struct tg3 *, tp) also creates larger objects. */ #define tg3_chip_rev_id(tp) … #define tg3_asic_rev(tp) … #define tg3_chip_rev(tp) … #endif /* !(_T3_H) */
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