/* bnx2.h: QLogic bnx2 network driver. * * Copyright (c) 2004-2014 Broadcom Corporation * Copyright (c) 2014-2015 QLogic Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. * * Written by: Michael Chan ([email protected]) */ #ifndef BNX2_H #define BNX2_H /* Hardware data structures and register definitions automatically * generated from RTL code. Do not modify. */ /* * tx_bd definition */ struct bnx2_tx_bd { … }; /* * rx_bd definition */ struct bnx2_rx_bd { … }; #define BNX2_RX_ALIGN … /* * status_block definition */ struct status_block { … }; /* * status_block definition */ struct status_block_msix { … }; #define BNX2_SBLK_MSIX_ALIGN_SIZE … /* * statistics_block definition */ struct statistics_block { … }; /* * l2_fhdr definition */ struct l2_fhdr { … }; #define BNX2_RX_OFFSET … /* * l2_context definition */ #define BNX2_L2CTX_TYPE … #define BNX2_L2CTX_TYPE_SIZE_L2 … #define BNX2_L2CTX_TYPE_TYPE … #define BNX2_L2CTX_TYPE_TYPE_EMPTY … #define BNX2_L2CTX_TYPE_TYPE_L2 … #define BNX2_L2CTX_TX_HOST_BIDX … #define BNX2_L2CTX_EST_NBD … #define BNX2_L2CTX_CMD_TYPE … #define BNX2_L2CTX_CMD_TYPE_TYPE … #define BNX2_L2CTX_CMD_TYPE_TYPE_L2 … #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP … #define BNX2_L2CTX_TX_HOST_BSEQ … #define BNX2_L2CTX_TSCH_BSEQ … #define BNX2_L2CTX_TBDR_BSEQ … #define BNX2_L2CTX_TBDR_BOFF … #define BNX2_L2CTX_TBDR_BIDX … #define BNX2_L2CTX_TBDR_BHADDR_HI … #define BNX2_L2CTX_TBDR_BHADDR_LO … #define BNX2_L2CTX_TXP_BOFF … #define BNX2_L2CTX_TXP_BIDX … #define BNX2_L2CTX_TXP_BSEQ … #define BNX2_L2CTX_TYPE_XI … #define BNX2_L2CTX_CMD_TYPE_XI … #define BNX2_L2CTX_TBDR_BHADDR_HI_XI … #define BNX2_L2CTX_TBDR_BHADDR_LO_XI … /* * l2_bd_chain_context definition */ #define BNX2_L2CTX_BD_PRE_READ … #define BNX2_L2CTX_CTX_SIZE … #define BNX2_L2CTX_CTX_TYPE … #define BNX2_L2CTX_FLOW_CTRL_ENABLE … #define BNX2_L2CTX_CTX_TYPE_SIZE_L2 … #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE … #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED … #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE … #define BNX2_L2CTX_HOST_BDIDX … #define BNX2_L2CTX_L5_STATUSB_NUM_SHIFT … #define BNX2_L2CTX_L2_STATUSB_NUM_SHIFT … #define BNX2_L2CTX_L5_STATUSB_NUM(sb_id) … #define BNX2_L2CTX_L2_STATUSB_NUM(sb_id) … #define BNX2_L2CTX_HOST_BSEQ … #define BNX2_L2CTX_NX_BSEQ … #define BNX2_L2CTX_NX_BDHADDR_HI … #define BNX2_L2CTX_NX_BDHADDR_LO … #define BNX2_L2CTX_NX_BDIDX … #define BNX2_L2CTX_HOST_PG_BDIDX … #define BNX2_L2CTX_PG_BUF_SIZE … #define BNX2_L2CTX_RBDC_KEY … #define BNX2_L2CTX_RBDC_JUMBO_KEY … #define BNX2_L2CTX_NX_PG_BDHADDR_HI … #define BNX2_L2CTX_NX_PG_BDHADDR_LO … /* * pci_config_l definition * offset: 0000 */ #define BNX2_PCICFG_MSI_CONTROL … #define BNX2_PCICFG_MSI_CONTROL_ENABLE … #define BNX2_PCICFG_MISC_CONFIG … #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP … #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP … #define BNX2_PCICFG_MISC_CONFIG_RESERVED1 … #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA … #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP … #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA … #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ … #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY … #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN … #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN … #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN … #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV … #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV … #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID … #define BNX2_PCICFG_MISC_STATUS … #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE … #define BNX2_PCICFG_MISC_STATUS_32BIT_DET … #define BNX2_PCICFG_MISC_STATUS_M66EN … #define BNX2_PCICFG_MISC_STATUS_PCIX_DET … #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED … #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 … #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 … #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 … #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE … #define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19 … #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED … #define BNX2_PCICFG_REG_WINDOW_ADDRESS … #define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL … #define BNX2_PCICFG_REG_WINDOW … #define BNX2_PCICFG_INT_ACK_CMD … #define BNX2_PCICFG_INT_ACK_CMD_INDEX … #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID … #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM … #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT … #define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM … #define BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT … #define BNX2_PCICFG_STATUS_BIT_SET_CMD … #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD … #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR … #define BNX2_PCICFG_MAILBOX_QUEUE_DATA … #define BNX2_PCICFG_DEVICE_CONTROL … #define BNX2_PCICFG_DEVICE_STATUS_NO_PEND … /* * pci_reg definition * offset: 0x400 */ #define BNX2_PCI_GRC_WINDOW_ADDR … #define BNX2_PCI_GRC_WINDOW_ADDR_VALUE … #define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN … #define BNX2_PCI_GRC_WINDOW2_BASE … #define BNX2_PCI_GRC_WINDOW3_BASE … #define BNX2_PCI_CONFIG_1 … #define BNX2_PCI_CONFIG_1_RESERVED0 … #define BNX2_PCI_CONFIG_1_READ_BOUNDARY … #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF … #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 … #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 … #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 … #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 … #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 … #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 … #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 … #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY … #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF … #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 … #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 … #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 … #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 … #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 … #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 … #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 … #define BNX2_PCI_CONFIG_1_RESERVED1 … #define BNX2_PCI_CONFIG_2 … #define BNX2_PCI_CONFIG_2_BAR1_SIZE … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M … #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G … #define BNX2_PCI_CONFIG_2_BAR1_64ENA … #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY … #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY … #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M … #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M … #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT … #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT … #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 … #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K … #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K … #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K … #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR … #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT … #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT … #define BNX2_PCI_CONFIG_2_RESERVED0 … #define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI … #define BNX2_PCI_CONFIG_2_RESERVED0_XI … #define BNX2_PCI_CONFIG_3 … #define BNX2_PCI_CONFIG_3_STICKY_BYTE … #define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE … #define BNX2_PCI_CONFIG_3_FORCE_PME … #define BNX2_PCI_CONFIG_3_PME_STATUS … #define BNX2_PCI_CONFIG_3_PME_ENABLE … #define BNX2_PCI_CONFIG_3_PM_STATE … #define BNX2_PCI_CONFIG_3_VAUX_PRESET … #define BNX2_PCI_CONFIG_3_PCI_POWER … #define BNX2_PCI_PM_DATA_A … #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG … #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG … #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG … #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG … #define BNX2_PCI_PM_DATA_B … #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG … #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG … #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG … #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG … #define BNX2_PCI_SWAP_DIAG0 … #define BNX2_PCI_SWAP_DIAG1 … #define BNX2_PCI_EXP_ROM_ADDR … #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS … #define BNX2_PCI_EXP_ROM_ADDR_REQ … #define BNX2_PCI_EXP_ROM_DATA … #define BNX2_PCI_VPD_INTF … #define BNX2_PCI_VPD_INTF_INTF_REQ … #define BNX2_PCI_VPD_ADDR_FLAG … #define BNX2_PCI_VPD_ADDR_FLAG_MSK … #define BNX2_PCI_VPD_ADDR_FLAG_SL … #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS … #define BNX2_PCI_VPD_ADDR_FLAG_WR … #define BNX2_PCI_VPD_DATA … #define BNX2_PCI_ID_VAL1 … #define BNX2_PCI_ID_VAL1_DEVICE_ID … #define BNX2_PCI_ID_VAL1_VENDOR_ID … #define BNX2_PCI_ID_VAL2 … #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID … #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID … #define BNX2_PCI_ID_VAL3 … #define BNX2_PCI_ID_VAL3_CLASS_CODE … #define BNX2_PCI_ID_VAL3_REVISION_ID … #define BNX2_PCI_ID_VAL4 … #define BNX2_PCI_ID_VAL4_CAP_ENA … #define BNX2_PCI_ID_VAL4_CAP_ENA_0 … #define BNX2_PCI_ID_VAL4_CAP_ENA_1 … #define BNX2_PCI_ID_VAL4_CAP_ENA_2 … #define BNX2_PCI_ID_VAL4_CAP_ENA_3 … #define BNX2_PCI_ID_VAL4_CAP_ENA_4 … #define BNX2_PCI_ID_VAL4_CAP_ENA_5 … #define BNX2_PCI_ID_VAL4_CAP_ENA_6 … #define BNX2_PCI_ID_VAL4_CAP_ENA_7 … #define BNX2_PCI_ID_VAL4_CAP_ENA_8 … #define BNX2_PCI_ID_VAL4_CAP_ENA_9 … #define BNX2_PCI_ID_VAL4_CAP_ENA_10 … #define BNX2_PCI_ID_VAL4_CAP_ENA_11 … #define BNX2_PCI_ID_VAL4_CAP_ENA_12 … #define BNX2_PCI_ID_VAL4_CAP_ENA_13 … #define BNX2_PCI_ID_VAL4_CAP_ENA_14 … #define BNX2_PCI_ID_VAL4_CAP_ENA_15 … #define BNX2_PCI_ID_VAL4_RESERVED0 … #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG … #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 … #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 … #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 … #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 … #define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP … #define BNX2_PCI_ID_VAL4_MSI_LIMIT … #define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP … #define BNX2_PCI_ID_VAL4_MSI_ENABLE … #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE … #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE … #define BNX2_PCI_ID_VAL4_RESERVED2 … #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21 … #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21 … #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0 … #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10 … #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0 … #define BNX2_PCI_ID_VAL4_RESERVED3 … #define BNX2_PCI_ID_VAL4_RESERVED3_XI … #define BNX2_PCI_ID_VAL5 … #define BNX2_PCI_ID_VAL5_D1_SUPPORT … #define BNX2_PCI_ID_VAL5_D2_SUPPORT … #define BNX2_PCI_ID_VAL5_PME_IN_D0 … #define BNX2_PCI_ID_VAL5_PME_IN_D1 … #define BNX2_PCI_ID_VAL5_PME_IN_D2 … #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT … #define BNX2_PCI_ID_VAL5_RESERVED0_TE … #define BNX2_PCI_ID_VAL5_PM_VERSION_XI … #define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI … #define BNX2_PCI_ID_VAL5_RESERVED0_XI … #define BNX2_PCI_PCIX_EXTENDED_STATUS … #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP … #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST … #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS … #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX … #define BNX2_PCI_ID_VAL6 … #define BNX2_PCI_ID_VAL6_MAX_LAT … #define BNX2_PCI_ID_VAL6_MIN_GNT … #define BNX2_PCI_ID_VAL6_BIST … #define BNX2_PCI_ID_VAL6_RESERVED0 … #define BNX2_PCI_MSI_DATA … #define BNX2_PCI_MSI_DATA_MSI_DATA … #define BNX2_PCI_MSI_ADDR_H … #define BNX2_PCI_MSI_ADDR_L … #define BNX2_PCI_MSI_ADDR_L_VAL … #define BNX2_PCI_CFG_ACCESS_CMD … #define BNX2_PCI_CFG_ACCESS_CMD_ADR … #define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ … #define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ … #define BNX2_PCI_CFG_ACCESS_DATA … #define BNX2_PCI_MSI_MASK … #define BNX2_PCI_MSI_MASK_MSI_MASK … #define BNX2_PCI_MSI_PEND … #define BNX2_PCI_MSI_PEND_MSI_PEND … #define BNX2_PCI_PM_DATA_C … #define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG … #define BNX2_PCI_PM_DATA_C_RESERVED0 … #define BNX2_PCI_MSIX_CONTROL … #define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ … #define BNX2_PCI_MSIX_CONTROL_RESERVED0 … #define BNX2_PCI_MSIX_TBL_OFF_BIR … #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR … #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF … #define BNX2_PCI_MSIX_PBA_OFF_BIT … #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR … #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF … #define BNX2_PCI_PCIE_CAPABILITY … #define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM … #define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1 … #define BNX2_PCI_DEVICE_CAPABILITY … #define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED … #define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT … #define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY … #define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY … #define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT … #define BNX2_PCI_LINK_CAPABILITY … #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED … #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001 … #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010 … #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH … #define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT … #define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT … #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT … #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101 … #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110 … #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT … #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001 … #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010 … #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT … #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101 … #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110 … #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT … #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001 … #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010 … #define BNX2_PCI_LINK_CAPABILITY_PORT_NUM … #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2 … #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP … #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP … #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED … #define BNX2_PCI_PCIE_LINK_CAPABILITY_2 … #define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED … #define BNX2_PCI_GRC_WINDOW1_ADDR … #define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE … #define BNX2_PCI_GRC_WINDOW2_ADDR … #define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE … #define BNX2_PCI_GRC_WINDOW3_ADDR … #define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE … #define BNX2_MSIX_TABLE_ADDR … #define BNX2_MSIX_PBA_ADDR … /* * misc_reg definition * offset: 0x800 */ #define BNX2_MISC_COMMAND … #define BNX2_MISC_COMMAND_ENABLE_ALL … #define BNX2_MISC_COMMAND_DISABLE_ALL … #define BNX2_MISC_COMMAND_SW_RESET … #define BNX2_MISC_COMMAND_POR_RESET … #define BNX2_MISC_COMMAND_HD_RESET … #define BNX2_MISC_COMMAND_CMN_SW_RESET … #define BNX2_MISC_COMMAND_PAR_ERROR … #define BNX2_MISC_COMMAND_CS16_ERR … #define BNX2_MISC_COMMAND_CS16_ERR_LOC … #define BNX2_MISC_COMMAND_PAR_ERR_RAM … #define BNX2_MISC_COMMAND_POWERDOWN_EVENT … #define BNX2_MISC_COMMAND_SW_SHUTDOWN … #define BNX2_MISC_COMMAND_SHUTDOWN_EN … #define BNX2_MISC_COMMAND_DINTEG_ATTN_EN … #define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23 … #define BNX2_MISC_COMMAND_PCIE_DIS … #define BNX2_MISC_CFG … #define BNX2_MISC_CFG_GRC_TMOUT … #define BNX2_MISC_CFG_NVM_WR_EN … #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT … #define BNX2_MISC_CFG_NVM_WR_EN_PCI … #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW … #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 … #define BNX2_MISC_CFG_BIST_EN … #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC … #define BNX2_MISC_CFG_RESERVED5_TE … #define BNX2_MISC_CFG_RESERVED6_TE … #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE … #define BNX2_MISC_CFG_LEDMODE … #define BNX2_MISC_CFG_LEDMODE_MAC … #define BNX2_MISC_CFG_LEDMODE_PHY1_TE … #define BNX2_MISC_CFG_LEDMODE_PHY2_TE … #define BNX2_MISC_CFG_LEDMODE_PHY3_TE … #define BNX2_MISC_CFG_LEDMODE_PHY4_TE … #define BNX2_MISC_CFG_LEDMODE_PHY5_TE … #define BNX2_MISC_CFG_LEDMODE_PHY6_TE … #define BNX2_MISC_CFG_LEDMODE_PHY7_TE … #define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE … #define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE … #define BNX2_MISC_CFG_LEDMODE_XI … #define BNX2_MISC_CFG_LEDMODE_MAC_XI … #define BNX2_MISC_CFG_LEDMODE_PHY1_XI … #define BNX2_MISC_CFG_LEDMODE_PHY2_XI … #define BNX2_MISC_CFG_LEDMODE_PHY3_XI … #define BNX2_MISC_CFG_LEDMODE_MAC2_XI … #define BNX2_MISC_CFG_LEDMODE_PHY4_XI … #define BNX2_MISC_CFG_LEDMODE_PHY5_XI … #define BNX2_MISC_CFG_LEDMODE_PHY6_XI … #define BNX2_MISC_CFG_LEDMODE_MAC3_XI … #define BNX2_MISC_CFG_LEDMODE_PHY7_XI … #define BNX2_MISC_CFG_LEDMODE_PHY8_XI … #define BNX2_MISC_CFG_LEDMODE_PHY9_XI … #define BNX2_MISC_CFG_LEDMODE_MAC4_XI … #define BNX2_MISC_CFG_LEDMODE_PHY10_XI … #define BNX2_MISC_CFG_LEDMODE_PHY11_XI … #define BNX2_MISC_CFG_LEDMODE_UNUSED_XI … #define BNX2_MISC_CFG_PORT_SELECT_XI … #define BNX2_MISC_CFG_PARITY_MODE_XI … #define BNX2_MISC_ID … #define BNX2_MISC_ID_BOND_ID … #define BNX2_MISC_ID_BOND_ID_X … #define BNX2_MISC_ID_BOND_ID_C … #define BNX2_MISC_ID_BOND_ID_S … #define BNX2_MISC_ID_CHIP_METAL … #define BNX2_MISC_ID_CHIP_REV … #define BNX2_MISC_ID_CHIP_NUM … #define BNX2_MISC_ENABLE_STATUS_BITS … #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE … #define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS … #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE … #define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS … #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE … #define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE … #define BNX2_MISC_CLOCK_CONTROL_BITS … #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET … #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ … #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ … #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ … #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ … #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ … #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ … #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ … #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ … #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 … #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI … #define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 … #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP … #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE … #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE … #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE … #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI … #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI … #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI … #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI … #define BNX2_MISC_SPIO … #define BNX2_MISC_SPIO_VALUE … #define BNX2_MISC_SPIO_SET … #define BNX2_MISC_SPIO_CLR … #define BNX2_MISC_SPIO_FLOAT … #define BNX2_MISC_SPIO_INT … #define BNX2_MISC_SPIO_INT_INT_STATE_TE … #define BNX2_MISC_SPIO_INT_OLD_VALUE_TE … #define BNX2_MISC_SPIO_INT_OLD_SET_TE … #define BNX2_MISC_SPIO_INT_OLD_CLR_TE … #define BNX2_MISC_SPIO_INT_INT_STATE_XI … #define BNX2_MISC_SPIO_INT_OLD_VALUE_XI … #define BNX2_MISC_SPIO_INT_OLD_SET_XI … #define BNX2_MISC_SPIO_INT_OLD_CLR_XI … #define BNX2_MISC_CONFIG_LFSR … #define BNX2_MISC_CONFIG_LFSR_DIV … #define BNX2_MISC_LFSR_MASK_BITS … #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE … #define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE … #define BNX2_MISC_ARB_REQ0 … #define BNX2_MISC_ARB_REQ1 … #define BNX2_MISC_ARB_REQ2 … #define BNX2_MISC_ARB_REQ3 … #define BNX2_MISC_ARB_REQ4 … #define BNX2_MISC_ARB_FREE0 … #define BNX2_MISC_ARB_FREE1 … #define BNX2_MISC_ARB_FREE2 … #define BNX2_MISC_ARB_FREE3 … #define BNX2_MISC_ARB_FREE4 … #define BNX2_MISC_ARB_REQ_STATUS0 … #define BNX2_MISC_ARB_REQ_STATUS1 … #define BNX2_MISC_ARB_REQ_STATUS2 … #define BNX2_MISC_ARB_REQ_STATUS3 … #define BNX2_MISC_ARB_REQ_STATUS4 … #define BNX2_MISC_ARB_GNT0 … #define BNX2_MISC_ARB_GNT0_0 … #define BNX2_MISC_ARB_GNT0_1 … #define BNX2_MISC_ARB_GNT0_2 … #define BNX2_MISC_ARB_GNT0_3 … #define BNX2_MISC_ARB_GNT0_4 … #define BNX2_MISC_ARB_GNT0_5 … #define BNX2_MISC_ARB_GNT0_6 … #define BNX2_MISC_ARB_GNT0_7 … #define BNX2_MISC_ARB_GNT1 … #define BNX2_MISC_ARB_GNT1_8 … #define BNX2_MISC_ARB_GNT1_9 … #define BNX2_MISC_ARB_GNT1_10 … #define BNX2_MISC_ARB_GNT1_11 … #define BNX2_MISC_ARB_GNT1_12 … #define BNX2_MISC_ARB_GNT1_13 … #define BNX2_MISC_ARB_GNT1_14 … #define BNX2_MISC_ARB_GNT1_15 … #define BNX2_MISC_ARB_GNT2 … #define BNX2_MISC_ARB_GNT2_16 … #define BNX2_MISC_ARB_GNT2_17 … #define BNX2_MISC_ARB_GNT2_18 … #define BNX2_MISC_ARB_GNT2_19 … #define BNX2_MISC_ARB_GNT2_20 … #define BNX2_MISC_ARB_GNT2_21 … #define BNX2_MISC_ARB_GNT2_22 … #define BNX2_MISC_ARB_GNT2_23 … #define BNX2_MISC_ARB_GNT3 … #define BNX2_MISC_ARB_GNT3_24 … #define BNX2_MISC_ARB_GNT3_25 … #define BNX2_MISC_ARB_GNT3_26 … #define BNX2_MISC_ARB_GNT3_27 … #define BNX2_MISC_ARB_GNT3_28 … #define BNX2_MISC_ARB_GNT3_29 … #define BNX2_MISC_ARB_GNT3_30 … #define BNX2_MISC_ARB_GNT3_31 … #define BNX2_MISC_RESERVED1 … #define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE … #define BNX2_MISC_RESERVED2 … #define BNX2_MISC_RESERVED2_PCIE_DIS … #define BNX2_MISC_RESERVED2_LINK_IN_L23 … #define BNX2_MISC_SM_ASF_CONTROL … #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST … #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN … #define BNX2_MISC_SM_ASF_CONTROL_WG_TO … #define BNX2_MISC_SM_ASF_CONTROL_HB_TO … #define BNX2_MISC_SM_ASF_CONTROL_PA_TO … #define BNX2_MISC_SM_ASF_CONTROL_PL_TO … #define BNX2_MISC_SM_ASF_CONTROL_RT_TO … #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT … #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN … #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE … #define BNX2_MISC_SM_ASF_CONTROL_RES … #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN … #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN … #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT … #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD … #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 … #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 … #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 … #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN … #define BNX2_MISC_SMB_IN … #define BNX2_MISC_SMB_IN_DAT_IN … #define BNX2_MISC_SMB_IN_RDY … #define BNX2_MISC_SMB_IN_DONE … #define BNX2_MISC_SMB_IN_FIRSTBYTE … #define BNX2_MISC_SMB_IN_STATUS … #define BNX2_MISC_SMB_IN_STATUS_OK … #define BNX2_MISC_SMB_IN_STATUS_PEC … #define BNX2_MISC_SMB_IN_STATUS_OFLOW … #define BNX2_MISC_SMB_IN_STATUS_STOP … #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT … #define BNX2_MISC_SMB_OUT … #define BNX2_MISC_SMB_OUT_DAT_OUT … #define BNX2_MISC_SMB_OUT_RDY … #define BNX2_MISC_SMB_OUT_START … #define BNX2_MISC_SMB_OUT_LAST … #define BNX2_MISC_SMB_OUT_ACC_TYPE … #define BNX2_MISC_SMB_OUT_ENB_PEC … #define BNX2_MISC_SMB_OUT_GET_RX_LEN … #define BNX2_MISC_SMB_OUT_SMB_READ_LEN … #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS … #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK … #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK … #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW … #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP … #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT … #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST … #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK … #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK … #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST … #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE … #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN … #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN … #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN … #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN … #define BNX2_MISC_SMB_WATCHDOG … #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG … #define BNX2_MISC_SMB_HEARTBEAT … #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT … #define BNX2_MISC_SMB_POLL_ASF … #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF … #define BNX2_MISC_SMB_POLL_LEGACY … #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY … #define BNX2_MISC_SMB_RETRAN … #define BNX2_MISC_SMB_RETRAN_RETRAN … #define BNX2_MISC_SMB_TIMESTAMP … #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP … #define BNX2_MISC_PERR_ENA0 … #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC … #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF … #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD … #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC … #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF … #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD … #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM … #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 … #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 … #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 … #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 … #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 … #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 … #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL … #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 … #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 … #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 … #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 … #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 … #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 … #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 … #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 … #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA … #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF … #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD … #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX … #define BNX2_MISC_PERR_ENA0_RBDC_MISC … #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB … #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR … #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC … #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM … #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS … #define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI … #define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1 … #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS … #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM … #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM … #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC … #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF … #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD … #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC … #define BNX2_MISC_PERR_ENA1_TBDC_MISC … #define BNX2_MISC_PERR_ENA1_TDMA_MISC … #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 … #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 … #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF … #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD … #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB … #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR … #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC … #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF … #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD … #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX … #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX … #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX … #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX … #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC … #define BNX2_MISC_PERR_ENA1_CSQ_MISC … #define BNX2_MISC_PERR_ENA1_CPQ_MISC … #define BNX2_MISC_PERR_ENA1_MCPQ_MISC … #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC … #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC … #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC … #define BNX2_MISC_PERR_ENA1_RXPQ_MISC … #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC … #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC … #define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI … #define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI … #define BNX2_MISC_PERR_ENA2 … #define BNX2_MISC_PERR_ENA2_COMQ_MISC … #define BNX2_MISC_PERR_ENA2_COMXQ_MISC … #define BNX2_MISC_PERR_ENA2_COMTQ_MISC … #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC … #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC … #define BNX2_MISC_PERR_ENA2_TXPQ_MISC … #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC … #define BNX2_MISC_PERR_ENA2_TPATQ_MISC … #define BNX2_MISC_PERR_ENA2_TASQ_MISC … #define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI … #define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI … #define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI … #define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI … #define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI … #define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI … #define BNX2_MISC_DEBUG_VECTOR_SEL … #define BNX2_MISC_DEBUG_VECTOR_SEL_0 … #define BNX2_MISC_DEBUG_VECTOR_SEL_1 … #define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI … #define BNX2_MISC_VREG_CONTROL … #define BNX2_MISC_VREG_CONTROL_1_2 … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI … #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI … #define BNX2_MISC_VREG_CONTROL_2_5 … #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14 … #define BNX2_MISC_VREG_CONTROL_2_5_PLUS12 … #define BNX2_MISC_VREG_CONTROL_2_5_PLUS10 … #define BNX2_MISC_VREG_CONTROL_2_5_PLUS8 … #define BNX2_MISC_VREG_CONTROL_2_5_PLUS6 … #define BNX2_MISC_VREG_CONTROL_2_5_PLUS4 … #define BNX2_MISC_VREG_CONTROL_2_5_PLUS2 … #define BNX2_MISC_VREG_CONTROL_2_5_NOM … #define BNX2_MISC_VREG_CONTROL_2_5_MINUS2 … #define BNX2_MISC_VREG_CONTROL_2_5_MINUS4 … #define BNX2_MISC_VREG_CONTROL_2_5_MINUS6 … #define BNX2_MISC_VREG_CONTROL_2_5_MINUS8 … #define BNX2_MISC_VREG_CONTROL_2_5_MINUS10 … #define BNX2_MISC_VREG_CONTROL_2_5_MINUS12 … #define BNX2_MISC_VREG_CONTROL_2_5_MINUS14 … #define BNX2_MISC_VREG_CONTROL_2_5_MINUS16 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 … #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 … #define BNX2_MISC_FINAL_CLK_CTL_VAL … #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL … #define BNX2_MISC_GP_HW_CTL0 … #define BNX2_MISC_GP_HW_CTL0_TX_DRIVE … #define BNX2_MISC_GP_HW_CTL0_RMII_MODE … #define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL … #define BNX2_MISC_GP_HW_CTL0_RVMII_MODE … #define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE … #define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE … #define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE … #define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI … #define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY … #define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE … #define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE … #define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE … #define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI … #define BNX2_MISC_GP_HW_CTL0_UP1_DEF0 … #define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF … #define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF … #define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF … #define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 … #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 … #define BNX2_MISC_GP_HW_CTL1 … #define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE … #define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE … #define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE … #define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE … #define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI … #define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI … #define BNX2_MISC_NEW_HW_CTL … #define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS … #define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE … #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0 … #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1 … #define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED … #define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT … #define BNX2_MISC_NEW_CORE_CTL … #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS … #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ … #define BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE … #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN … #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC … #define BNX2_MISC_ECO_HW_CTL … #define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN … #define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT … #define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD … #define BNX2_MISC_ECO_CORE_CTL … #define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT … #define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD … #define BNX2_MISC_PPIO … #define BNX2_MISC_PPIO_VALUE … #define BNX2_MISC_PPIO_SET … #define BNX2_MISC_PPIO_CLR … #define BNX2_MISC_PPIO_FLOAT … #define BNX2_MISC_PPIO_INT … #define BNX2_MISC_PPIO_INT_INT_STATE … #define BNX2_MISC_PPIO_INT_OLD_VALUE … #define BNX2_MISC_PPIO_INT_OLD_SET … #define BNX2_MISC_PPIO_INT_OLD_CLR … #define BNX2_MISC_RESET_NUMS … #define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS … #define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS … #define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS … #define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS … #define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS … #define BNX2_MISC_CS16_ERR … #define BNX2_MISC_CS16_ERR_ENA_PCI … #define BNX2_MISC_CS16_ERR_ENA_RDMA … #define BNX2_MISC_CS16_ERR_ENA_TDMA … #define BNX2_MISC_CS16_ERR_ENA_EMAC … #define BNX2_MISC_CS16_ERR_ENA_CTX … #define BNX2_MISC_CS16_ERR_ENA_TBDR … #define BNX2_MISC_CS16_ERR_ENA_RBDC … #define BNX2_MISC_CS16_ERR_ENA_COM … #define BNX2_MISC_CS16_ERR_ENA_CP … #define BNX2_MISC_CS16_ERR_STA_PCI … #define BNX2_MISC_CS16_ERR_STA_RDMA … #define BNX2_MISC_CS16_ERR_STA_TDMA … #define BNX2_MISC_CS16_ERR_STA_EMAC … #define BNX2_MISC_CS16_ERR_STA_CTX … #define BNX2_MISC_CS16_ERR_STA_TBDR … #define BNX2_MISC_CS16_ERR_STA_RBDC … #define BNX2_MISC_CS16_ERR_STA_COM … #define BNX2_MISC_CS16_ERR_STA_CP … #define BNX2_MISC_SPIO_EVENT … #define BNX2_MISC_SPIO_EVENT_ENABLE … #define BNX2_MISC_PPIO_EVENT … #define BNX2_MISC_PPIO_EVENT_ENABLE … #define BNX2_MISC_DUAL_MEDIA_CTRL … #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID … #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X … #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C … #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP … #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN … #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET … #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET … #define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST … #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST … #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL … #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP … #define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ … #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ … #define BNX2_MISC_OTP_CMD1 … #define BNX2_MISC_OTP_CMD1_FMODE … #define BNX2_MISC_OTP_CMD1_FMODE_IDLE … #define BNX2_MISC_OTP_CMD1_FMODE_WRITE … #define BNX2_MISC_OTP_CMD1_FMODE_INIT … #define BNX2_MISC_OTP_CMD1_FMODE_SET … #define BNX2_MISC_OTP_CMD1_FMODE_RST … #define BNX2_MISC_OTP_CMD1_FMODE_VERIFY … #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0 … #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1 … #define BNX2_MISC_OTP_CMD1_USEPINS … #define BNX2_MISC_OTP_CMD1_PROGSEL … #define BNX2_MISC_OTP_CMD1_PROGSTART … #define BNX2_MISC_OTP_CMD1_PCOUNT … #define BNX2_MISC_OTP_CMD1_PBYP … #define BNX2_MISC_OTP_CMD1_VSEL … #define BNX2_MISC_OTP_CMD1_TM … #define BNX2_MISC_OTP_CMD1_SADBYP … #define BNX2_MISC_OTP_CMD1_DEBUG … #define BNX2_MISC_OTP_CMD2 … #define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR … #define BNX2_MISC_OTP_CMD2_DOSEL … #define BNX2_MISC_OTP_CMD2_DOSEL_0 … #define BNX2_MISC_OTP_CMD2_DOSEL_1 … #define BNX2_MISC_OTP_CMD2_DOSEL_127 … #define BNX2_MISC_OTP_STATUS … #define BNX2_MISC_OTP_STATUS_DATA … #define BNX2_MISC_OTP_STATUS_VALID … #define BNX2_MISC_OTP_STATUS_BUSY … #define BNX2_MISC_OTP_STATUS_BUSYSM … #define BNX2_MISC_OTP_STATUS_DONE … #define BNX2_MISC_OTP_SHIFT1_CMD … #define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N … #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE … #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START … #define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA … #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT … #define BNX2_MISC_OTP_SHIFT1_DATA … #define BNX2_MISC_OTP_SHIFT2_CMD … #define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N … #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE … #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START … #define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA … #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT … #define BNX2_MISC_OTP_SHIFT2_DATA … #define BNX2_MISC_BIST_CS0 … #define BNX2_MISC_BIST_CS0_MBIST_EN … #define BNX2_MISC_BIST_CS0_BIST_SETUP … #define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET … #define BNX2_MISC_BIST_CS0_MBIST_DONE … #define BNX2_MISC_BIST_CS0_MBIST_GO … #define BNX2_MISC_BIST_CS0_BIST_OVERRIDE … #define BNX2_MISC_BIST_MEMSTATUS0 … #define BNX2_MISC_BIST_CS1 … #define BNX2_MISC_BIST_CS1_MBIST_EN … #define BNX2_MISC_BIST_CS1_BIST_SETUP … #define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET … #define BNX2_MISC_BIST_CS1_MBIST_DONE … #define BNX2_MISC_BIST_CS1_MBIST_GO … #define BNX2_MISC_BIST_MEMSTATUS1 … #define BNX2_MISC_BIST_CS2 … #define BNX2_MISC_BIST_CS2_MBIST_EN … #define BNX2_MISC_BIST_CS2_BIST_SETUP … #define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET … #define BNX2_MISC_BIST_CS2_MBIST_DONE … #define BNX2_MISC_BIST_CS2_MBIST_GO … #define BNX2_MISC_BIST_MEMSTATUS2 … #define BNX2_MISC_BIST_CS3 … #define BNX2_MISC_BIST_CS3_MBIST_EN … #define BNX2_MISC_BIST_CS3_BIST_SETUP … #define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET … #define BNX2_MISC_BIST_CS3_MBIST_DONE … #define BNX2_MISC_BIST_CS3_MBIST_GO … #define BNX2_MISC_BIST_MEMSTATUS3 … #define BNX2_MISC_BIST_CS4 … #define BNX2_MISC_BIST_CS4_MBIST_EN … #define BNX2_MISC_BIST_CS4_BIST_SETUP … #define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET … #define BNX2_MISC_BIST_CS4_MBIST_DONE … #define BNX2_MISC_BIST_CS4_MBIST_GO … #define BNX2_MISC_BIST_MEMSTATUS4 … #define BNX2_MISC_BIST_CS5 … #define BNX2_MISC_BIST_CS5_MBIST_EN … #define BNX2_MISC_BIST_CS5_BIST_SETUP … #define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET … #define BNX2_MISC_BIST_CS5_MBIST_DONE … #define BNX2_MISC_BIST_CS5_MBIST_GO … #define BNX2_MISC_BIST_MEMSTATUS5 … #define BNX2_MISC_MEM_TM0 … #define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM … #define BNX2_MISC_MEM_TM0_MCP_SCPAD … #define BNX2_MISC_MEM_TM0_UMP_TM … #define BNX2_MISC_MEM_TM0_HB_MEM_TM … #define BNX2_MISC_USPLL_CTRL … #define BNX2_MISC_USPLL_CTRL_PH_DET_DIS … #define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS … #define BNX2_MISC_USPLL_CTRL_LCPX … #define BNX2_MISC_USPLL_CTRL_RX … #define BNX2_MISC_USPLL_CTRL_VC_EN … #define BNX2_MISC_USPLL_CTRL_VCO_MG … #define BNX2_MISC_USPLL_CTRL_KVCO_XF … #define BNX2_MISC_USPLL_CTRL_KVCO_XS … #define BNX2_MISC_USPLL_CTRL_TESTD_EN … #define BNX2_MISC_USPLL_CTRL_TESTD_SEL … #define BNX2_MISC_USPLL_CTRL_TESTA_EN … #define BNX2_MISC_USPLL_CTRL_TESTA_SEL … #define BNX2_MISC_USPLL_CTRL_ATTEN_FREF … #define BNX2_MISC_USPLL_CTRL_DIGITAL_RST … #define BNX2_MISC_USPLL_CTRL_ANALOG_RST … #define BNX2_MISC_USPLL_CTRL_LOCK … #define BNX2_MISC_PERR_STATUS0 … #define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR … #define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR … #define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR … #define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR … #define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR … #define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR … #define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR … #define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR … #define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR … #define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR … #define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR … #define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR … #define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR … #define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR … #define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR … #define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR … #define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR … #define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR … #define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR … #define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR … #define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR … #define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR … #define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR … #define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR … #define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR … #define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR … #define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR … #define BNX2_MISC_PERR_STATUS0_TPBUF_PERR … #define BNX2_MISC_PERR_STATUS0_THBUF_PERR … #define BNX2_MISC_PERR_STATUS0_TDMA_PERR … #define BNX2_MISC_PERR_STATUS0_TBDC_PERR … #define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR … #define BNX2_MISC_PERR_STATUS1 … #define BNX2_MISC_PERR_STATUS1_RBDC_PERR … #define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR … #define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR … #define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR … #define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR … #define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR … #define BNX2_MISC_PERR_STATUS1_TPATQ_PERR … #define BNX2_MISC_PERR_STATUS1_MCPQ_PERR … #define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR … #define BNX2_MISC_PERR_STATUS1_TXPQ_PERR … #define BNX2_MISC_PERR_STATUS1_COMTQ_PERR … #define BNX2_MISC_PERR_STATUS1_COMQ_PERR … #define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR … #define BNX2_MISC_PERR_STATUS1_RXPQ_PERR … #define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR … #define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR … #define BNX2_MISC_PERR_STATUS1_TASQ_PERR … #define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR … #define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR … #define BNX2_MISC_PERR_STATUS1_COMXQ_PERR … #define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR … #define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR … #define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR … #define BNX2_MISC_PERR_STATUS1_CPQ_PERR … #define BNX2_MISC_PERR_STATUS1_CSQ_PERR … #define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR … #define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR … #define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR … #define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR … #define BNX2_MISC_PERR_STATUS2 … #define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR … #define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR … #define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR … #define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR … #define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR … #define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR … #define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR … #define BNX2_MISC_LCPLL_CTRL0 … #define BNX2_MISC_LCPLL_CTRL0_OAC … #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY … #define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO … #define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY … #define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY … #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL … #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360 … #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480 … #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600 … #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720 … #define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL … #define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE … #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL … #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0 … #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1 … #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2 … #define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART … #define BNX2_MISC_LCPLL_CTRL0_RESERVED … #define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN … #define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN … #define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN … #define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN … #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN … #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE … #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS … #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN … #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE … #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN … #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS … #define BNX2_MISC_LCPLL_CTRL0_CAPRESTART … #define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN … #define BNX2_MISC_LCPLL_CTRL1 … #define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM … #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN … #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN … #define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR … #define BNX2_MISC_LCPLL_STATUS … #define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM … #define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM … #define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE … #define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS … #define BNX2_MISC_LCPLL_STATUS_PLLSTATE … #define BNX2_MISC_LCPLL_STATUS_CAPSTATE … #define BNX2_MISC_LCPLL_STATUS_CAPSELECT … #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR … #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 … #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 … #define BNX2_MISC_OSCFUNDS_CTRL … #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON … #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF … #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON … #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM … #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 … #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 … #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 … #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 … #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ … #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 … #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 … #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 … #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 … #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ … #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 … #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 … #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 … #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 … /* * nvm_reg definition * offset: 0x6400 */ #define BNX2_NVM_COMMAND … #define BNX2_NVM_COMMAND_RST … #define BNX2_NVM_COMMAND_DONE … #define BNX2_NVM_COMMAND_DOIT … #define BNX2_NVM_COMMAND_WR … #define BNX2_NVM_COMMAND_ERASE … #define BNX2_NVM_COMMAND_FIRST … #define BNX2_NVM_COMMAND_LAST … #define BNX2_NVM_COMMAND_WREN … #define BNX2_NVM_COMMAND_WRDI … #define BNX2_NVM_COMMAND_EWSR … #define BNX2_NVM_COMMAND_WRSR … #define BNX2_NVM_COMMAND_RD_ID … #define BNX2_NVM_COMMAND_RD_STATUS … #define BNX2_NVM_COMMAND_MODE_256 … #define BNX2_NVM_STATUS … #define BNX2_NVM_STATUS_PI_FSM_STATE … #define BNX2_NVM_STATUS_EE_FSM_STATE … #define BNX2_NVM_STATUS_EQ_FSM_STATE … #define BNX2_NVM_STATUS_SPI_FSM_STATE_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI … #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI … #define BNX2_NVM_WRITE … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI … #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI … #define BNX2_NVM_ADDR … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI … #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI … #define BNX2_NVM_READ … #define BNX2_NVM_READ_NVM_READ_VALUE … #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG … #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK … #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA … #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK … #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B … #define BNX2_NVM_READ_NVM_READ_VALUE_SO … #define BNX2_NVM_READ_NVM_READ_VALUE_SI … #define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI … #define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI … #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI … #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI … #define BNX2_NVM_CFG1 … #define BNX2_NVM_CFG1_FLASH_MODE … #define BNX2_NVM_CFG1_BUFFER_MODE … #define BNX2_NVM_CFG1_PASS_MODE … #define BNX2_NVM_CFG1_BITBANG_MODE … #define BNX2_NVM_CFG1_STATUS_BIT … #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY … #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY … #define BNX2_NVM_CFG1_SPI_CLK_DIV … #define BNX2_NVM_CFG1_SEE_CLK_DIV … #define BNX2_NVM_CFG1_STRAP_CONTROL_0 … #define BNX2_NVM_CFG1_PROTECT_MODE … #define BNX2_NVM_CFG1_FLASH_SIZE … #define BNX2_NVM_CFG1_FW_USTRAP_1 … #define BNX2_NVM_CFG1_FW_USTRAP_0 … #define BNX2_NVM_CFG1_FW_USTRAP_2 … #define BNX2_NVM_CFG1_FW_USTRAP_3 … #define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN … #define BNX2_NVM_CFG1_COMPAT_BYPASSS … #define BNX2_NVM_CFG2 … #define BNX2_NVM_CFG2_ERASE_CMD … #define BNX2_NVM_CFG2_DUMMY … #define BNX2_NVM_CFG2_STATUS_CMD … #define BNX2_NVM_CFG2_READ_ID … #define BNX2_NVM_CFG3 … #define BNX2_NVM_CFG3_BUFFER_RD_CMD … #define BNX2_NVM_CFG3_WRITE_CMD … #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD … #define BNX2_NVM_CFG3_READ_CMD … #define BNX2_NVM_SW_ARB … #define BNX2_NVM_SW_ARB_ARB_REQ_SET0 … #define BNX2_NVM_SW_ARB_ARB_REQ_SET1 … #define BNX2_NVM_SW_ARB_ARB_REQ_SET2 … #define BNX2_NVM_SW_ARB_ARB_REQ_SET3 … #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 … #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 … #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 … #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 … #define BNX2_NVM_SW_ARB_ARB_ARB0 … #define BNX2_NVM_SW_ARB_ARB_ARB1 … #define BNX2_NVM_SW_ARB_ARB_ARB2 … #define BNX2_NVM_SW_ARB_ARB_ARB3 … #define BNX2_NVM_SW_ARB_REQ0 … #define BNX2_NVM_SW_ARB_REQ1 … #define BNX2_NVM_SW_ARB_REQ2 … #define BNX2_NVM_SW_ARB_REQ3 … #define BNX2_NVM_ACCESS_ENABLE … #define BNX2_NVM_ACCESS_ENABLE_EN … #define BNX2_NVM_ACCESS_ENABLE_WR_EN … #define BNX2_NVM_WRITE1 … #define BNX2_NVM_WRITE1_WREN_CMD … #define BNX2_NVM_WRITE1_WRDI_CMD … #define BNX2_NVM_WRITE1_SR_DATA … #define BNX2_NVM_CFG4 … #define BNX2_NVM_CFG4_FLASH_SIZE … #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT … #define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT … #define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT … #define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT … #define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT … #define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT … #define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT … #define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT … #define BNX2_NVM_CFG4_FLASH_VENDOR … #define BNX2_NVM_CFG4_FLASH_VENDOR_ST … #define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL … #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC … #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 … #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 … #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 … #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 … #define BNX2_NVM_CFG4_STATUS_BIT_POLARITY … #define BNX2_NVM_CFG4_RESERVED … #define BNX2_NVM_RECONFIG … #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE … #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST … #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL … #define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE … #define BNX2_NVM_RECONFIG_RESERVED … #define BNX2_NVM_RECONFIG_RECONFIG_DONE … /* * dma_reg definition * offset: 0xc00 */ #define BNX2_DMA_COMMAND … #define BNX2_DMA_COMMAND_ENABLE … #define BNX2_DMA_STATUS … #define BNX2_DMA_STATUS_PAR_ERROR_STATE … #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT … #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT … #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT … #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT … #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT … #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT … #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT … #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT … #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT … #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT … #define BNX2_DMA_STATUS_GLOBAL_ERR_XI … #define BNX2_DMA_STATUS_BME_XI … #define BNX2_DMA_CONFIG … #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP … #define BNX2_DMA_CONFIG_DATA_WORD_SWAP … #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP … #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP … #define BNX2_DMA_CONFIG_ONE_DMA … #define BNX2_DMA_CONFIG_CNTL_TWO_DMA … #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE … #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA … #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY … #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE … #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE … #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS … #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP … #define BNX2_DMA_CONFIG_BIG_SIZE … #define BNX2_DMA_CONFIG_BIG_SIZE_NONE … #define BNX2_DMA_CONFIG_BIG_SIZE_64 … #define BNX2_DMA_CONFIG_BIG_SIZE_128 … #define BNX2_DMA_CONFIG_BIG_SIZE_256 … #define BNX2_DMA_CONFIG_BIG_SIZE_512 … #define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI … #define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI … #define BNX2_DMA_CONFIG_MAX_PL_XI … #define BNX2_DMA_CONFIG_MAX_PL_128B_XI … #define BNX2_DMA_CONFIG_MAX_PL_256B_XI … #define BNX2_DMA_CONFIG_MAX_PL_512B_XI … #define BNX2_DMA_CONFIG_MAX_PL_EN_XI … #define BNX2_DMA_CONFIG_MAX_RRS_XI … #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI … #define BNX2_DMA_CONFIG_MAX_RRS_256B_XI … #define BNX2_DMA_CONFIG_MAX_RRS_512B_XI … #define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI … #define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI … #define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI … #define BNX2_DMA_CONFIG_MAX_RRS_EN_XI … #define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI … #define BNX2_DMA_BLACKOUT … #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT … #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT … #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT … #define BNX2_DMA_READ_MASTER_SETTING_0 … #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP … #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER … #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY … #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS … #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN … #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP … #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER … #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY … #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS … #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN … #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP … #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER … #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY … #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS … #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN … #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP … #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER … #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY … #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS … #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN … #define BNX2_DMA_READ_MASTER_SETTING_1 … #define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP … #define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER … #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY … #define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS … #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN … #define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP … #define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER … #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY … #define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS … #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN … #define BNX2_DMA_WRITE_MASTER_SETTING_0 … #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP … #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER … #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY … #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD … #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS … #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN … #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP … #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER … #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY … #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD … #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS … #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN … #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP … #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER … #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY … #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD … #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS … #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN … #define BNX2_DMA_WRITE_MASTER_SETTING_1 … #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP … #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER … #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY … #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD … #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS … #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN … #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP … #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER … #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY … #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD … #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS … #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN … #define BNX2_DMA_ARBITER … #define BNX2_DMA_ARBITER_NUM_READS … #define BNX2_DMA_ARBITER_WR_ARB_MODE … #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT … #define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN … #define BNX2_DMA_ARBITER_RD_ARB_MODE … #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT … #define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN … #define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN … #define BNX2_DMA_ARBITER_ALT_MODE_EN … #define BNX2_DMA_ARBITER_RR_MODE … #define BNX2_DMA_ARBITER_TIMER_MODE … #define BNX2_DMA_ARBITER_OUSTD_READ_REQ … #define BNX2_DMA_ARB_TIMERS … #define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME … #define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT … #define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT … #define BNX2_DMA_DEBUG_VECT_PEEK … #define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE … #define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN … #define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL … #define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE … #define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN … #define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL … #define BNX2_DMA_TAG_RAM_00 … #define BNX2_DMA_TAG_RAM_00_CHANNEL … #define BNX2_DMA_TAG_RAM_00_MASTER … #define BNX2_DMA_TAG_RAM_00_MASTER_CTX … #define BNX2_DMA_TAG_RAM_00_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_00_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_00_MASTER_COM … #define BNX2_DMA_TAG_RAM_00_MASTER_CP … #define BNX2_DMA_TAG_RAM_00_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_00_SWAP … #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_00_SWAP_DATA … #define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_00_FUNCTION … #define BNX2_DMA_TAG_RAM_00_VALID … #define BNX2_DMA_TAG_RAM_01 … #define BNX2_DMA_TAG_RAM_01_CHANNEL … #define BNX2_DMA_TAG_RAM_01_MASTER … #define BNX2_DMA_TAG_RAM_01_MASTER_CTX … #define BNX2_DMA_TAG_RAM_01_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_01_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_01_MASTER_COM … #define BNX2_DMA_TAG_RAM_01_MASTER_CP … #define BNX2_DMA_TAG_RAM_01_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_01_SWAP … #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_01_SWAP_DATA … #define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_01_FUNCTION … #define BNX2_DMA_TAG_RAM_01_VALID … #define BNX2_DMA_TAG_RAM_02 … #define BNX2_DMA_TAG_RAM_02_CHANNEL … #define BNX2_DMA_TAG_RAM_02_MASTER … #define BNX2_DMA_TAG_RAM_02_MASTER_CTX … #define BNX2_DMA_TAG_RAM_02_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_02_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_02_MASTER_COM … #define BNX2_DMA_TAG_RAM_02_MASTER_CP … #define BNX2_DMA_TAG_RAM_02_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_02_SWAP … #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_02_SWAP_DATA … #define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_02_FUNCTION … #define BNX2_DMA_TAG_RAM_02_VALID … #define BNX2_DMA_TAG_RAM_03 … #define BNX2_DMA_TAG_RAM_03_CHANNEL … #define BNX2_DMA_TAG_RAM_03_MASTER … #define BNX2_DMA_TAG_RAM_03_MASTER_CTX … #define BNX2_DMA_TAG_RAM_03_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_03_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_03_MASTER_COM … #define BNX2_DMA_TAG_RAM_03_MASTER_CP … #define BNX2_DMA_TAG_RAM_03_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_03_SWAP … #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_03_SWAP_DATA … #define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_03_FUNCTION … #define BNX2_DMA_TAG_RAM_03_VALID … #define BNX2_DMA_TAG_RAM_04 … #define BNX2_DMA_TAG_RAM_04_CHANNEL … #define BNX2_DMA_TAG_RAM_04_MASTER … #define BNX2_DMA_TAG_RAM_04_MASTER_CTX … #define BNX2_DMA_TAG_RAM_04_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_04_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_04_MASTER_COM … #define BNX2_DMA_TAG_RAM_04_MASTER_CP … #define BNX2_DMA_TAG_RAM_04_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_04_SWAP … #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_04_SWAP_DATA … #define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_04_FUNCTION … #define BNX2_DMA_TAG_RAM_04_VALID … #define BNX2_DMA_TAG_RAM_05 … #define BNX2_DMA_TAG_RAM_05_CHANNEL … #define BNX2_DMA_TAG_RAM_05_MASTER … #define BNX2_DMA_TAG_RAM_05_MASTER_CTX … #define BNX2_DMA_TAG_RAM_05_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_05_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_05_MASTER_COM … #define BNX2_DMA_TAG_RAM_05_MASTER_CP … #define BNX2_DMA_TAG_RAM_05_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_05_SWAP … #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_05_SWAP_DATA … #define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_05_FUNCTION … #define BNX2_DMA_TAG_RAM_05_VALID … #define BNX2_DMA_TAG_RAM_06 … #define BNX2_DMA_TAG_RAM_06_CHANNEL … #define BNX2_DMA_TAG_RAM_06_MASTER … #define BNX2_DMA_TAG_RAM_06_MASTER_CTX … #define BNX2_DMA_TAG_RAM_06_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_06_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_06_MASTER_COM … #define BNX2_DMA_TAG_RAM_06_MASTER_CP … #define BNX2_DMA_TAG_RAM_06_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_06_SWAP … #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_06_SWAP_DATA … #define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_06_FUNCTION … #define BNX2_DMA_TAG_RAM_06_VALID … #define BNX2_DMA_TAG_RAM_07 … #define BNX2_DMA_TAG_RAM_07_CHANNEL … #define BNX2_DMA_TAG_RAM_07_MASTER … #define BNX2_DMA_TAG_RAM_07_MASTER_CTX … #define BNX2_DMA_TAG_RAM_07_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_07_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_07_MASTER_COM … #define BNX2_DMA_TAG_RAM_07_MASTER_CP … #define BNX2_DMA_TAG_RAM_07_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_07_SWAP … #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_07_SWAP_DATA … #define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_07_FUNCTION … #define BNX2_DMA_TAG_RAM_07_VALID … #define BNX2_DMA_TAG_RAM_08 … #define BNX2_DMA_TAG_RAM_08_CHANNEL … #define BNX2_DMA_TAG_RAM_08_MASTER … #define BNX2_DMA_TAG_RAM_08_MASTER_CTX … #define BNX2_DMA_TAG_RAM_08_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_08_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_08_MASTER_COM … #define BNX2_DMA_TAG_RAM_08_MASTER_CP … #define BNX2_DMA_TAG_RAM_08_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_08_SWAP … #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_08_SWAP_DATA … #define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_08_FUNCTION … #define BNX2_DMA_TAG_RAM_08_VALID … #define BNX2_DMA_TAG_RAM_09 … #define BNX2_DMA_TAG_RAM_09_CHANNEL … #define BNX2_DMA_TAG_RAM_09_MASTER … #define BNX2_DMA_TAG_RAM_09_MASTER_CTX … #define BNX2_DMA_TAG_RAM_09_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_09_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_09_MASTER_COM … #define BNX2_DMA_TAG_RAM_09_MASTER_CP … #define BNX2_DMA_TAG_RAM_09_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_09_SWAP … #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_09_SWAP_DATA … #define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_09_FUNCTION … #define BNX2_DMA_TAG_RAM_09_VALID … #define BNX2_DMA_TAG_RAM_10 … #define BNX2_DMA_TAG_RAM_10_CHANNEL … #define BNX2_DMA_TAG_RAM_10_MASTER … #define BNX2_DMA_TAG_RAM_10_MASTER_CTX … #define BNX2_DMA_TAG_RAM_10_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_10_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_10_MASTER_COM … #define BNX2_DMA_TAG_RAM_10_MASTER_CP … #define BNX2_DMA_TAG_RAM_10_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_10_SWAP … #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_10_SWAP_DATA … #define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_10_FUNCTION … #define BNX2_DMA_TAG_RAM_10_VALID … #define BNX2_DMA_TAG_RAM_11 … #define BNX2_DMA_TAG_RAM_11_CHANNEL … #define BNX2_DMA_TAG_RAM_11_MASTER … #define BNX2_DMA_TAG_RAM_11_MASTER_CTX … #define BNX2_DMA_TAG_RAM_11_MASTER_RBDC … #define BNX2_DMA_TAG_RAM_11_MASTER_TBDC … #define BNX2_DMA_TAG_RAM_11_MASTER_COM … #define BNX2_DMA_TAG_RAM_11_MASTER_CP … #define BNX2_DMA_TAG_RAM_11_MASTER_TDMA … #define BNX2_DMA_TAG_RAM_11_SWAP … #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG … #define BNX2_DMA_TAG_RAM_11_SWAP_DATA … #define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL … #define BNX2_DMA_TAG_RAM_11_FUNCTION … #define BNX2_DMA_TAG_RAM_11_VALID … #define BNX2_DMA_RCHAN_STAT_22 … #define BNX2_DMA_RCHAN_STAT_30 … #define BNX2_DMA_RCHAN_STAT_31 … #define BNX2_DMA_RCHAN_STAT_32 … #define BNX2_DMA_RCHAN_STAT_40 … #define BNX2_DMA_RCHAN_STAT_41 … #define BNX2_DMA_RCHAN_STAT_42 … #define BNX2_DMA_RCHAN_STAT_50 … #define BNX2_DMA_RCHAN_STAT_51 … #define BNX2_DMA_RCHAN_STAT_52 … #define BNX2_DMA_RCHAN_STAT_60 … #define BNX2_DMA_RCHAN_STAT_61 … #define BNX2_DMA_RCHAN_STAT_62 … #define BNX2_DMA_RCHAN_STAT_70 … #define BNX2_DMA_RCHAN_STAT_71 … #define BNX2_DMA_RCHAN_STAT_72 … #define BNX2_DMA_WCHAN_STAT_00 … #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW … #define BNX2_DMA_WCHAN_STAT_01 … #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH … #define BNX2_DMA_WCHAN_STAT_02 … #define BNX2_DMA_WCHAN_STAT_02_LENGTH … #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP … #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP … #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL … #define BNX2_DMA_WCHAN_STAT_10 … #define BNX2_DMA_WCHAN_STAT_11 … #define BNX2_DMA_WCHAN_STAT_12 … #define BNX2_DMA_WCHAN_STAT_20 … #define BNX2_DMA_WCHAN_STAT_21 … #define BNX2_DMA_WCHAN_STAT_22 … #define BNX2_DMA_WCHAN_STAT_30 … #define BNX2_DMA_WCHAN_STAT_31 … #define BNX2_DMA_WCHAN_STAT_32 … #define BNX2_DMA_WCHAN_STAT_40 … #define BNX2_DMA_WCHAN_STAT_41 … #define BNX2_DMA_WCHAN_STAT_42 … #define BNX2_DMA_WCHAN_STAT_50 … #define BNX2_DMA_WCHAN_STAT_51 … #define BNX2_DMA_WCHAN_STAT_52 … #define BNX2_DMA_WCHAN_STAT_60 … #define BNX2_DMA_WCHAN_STAT_61 … #define BNX2_DMA_WCHAN_STAT_62 … #define BNX2_DMA_WCHAN_STAT_70 … #define BNX2_DMA_WCHAN_STAT_71 … #define BNX2_DMA_WCHAN_STAT_72 … #define BNX2_DMA_ARB_STAT_00 … #define BNX2_DMA_ARB_STAT_00_MASTER … #define BNX2_DMA_ARB_STAT_00_MASTER_ENC … #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR … #define BNX2_DMA_ARB_STAT_01 … #define BNX2_DMA_ARB_STAT_01_LPR_RPTR … #define BNX2_DMA_ARB_STAT_01_LPR_WPTR … #define BNX2_DMA_ARB_STAT_01_LPB_RPTR … #define BNX2_DMA_ARB_STAT_01_LPB_WPTR … #define BNX2_DMA_ARB_STAT_01_HPR_RPTR … #define BNX2_DMA_ARB_STAT_01_HPR_WPTR … #define BNX2_DMA_ARB_STAT_01_HPB_RPTR … #define BNX2_DMA_ARB_STAT_01_HPB_WPTR … #define BNX2_DMA_FUSE_CTRL0_CMD … #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE … #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE … #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT … #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD … #define BNX2_DMA_FUSE_CTRL0_CMD_SEL … #define BNX2_DMA_FUSE_CTRL0_DATA … #define BNX2_DMA_FUSE_CTRL1_CMD … #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE … #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE … #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT … #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD … #define BNX2_DMA_FUSE_CTRL1_CMD_SEL … #define BNX2_DMA_FUSE_CTRL1_DATA … #define BNX2_DMA_FUSE_CTRL2_CMD … #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE … #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE … #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT … #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD … #define BNX2_DMA_FUSE_CTRL2_CMD_SEL … #define BNX2_DMA_FUSE_CTRL2_DATA … /* * context_reg definition * offset: 0x1000 */ #define BNX2_CTX_COMMAND … #define BNX2_CTX_COMMAND_ENABLED … #define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT … #define BNX2_CTX_COMMAND_DISABLE_PLRU … #define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ … #define BNX2_CTX_COMMAND_FLUSH_AHEAD … #define BNX2_CTX_COMMAND_MEM_INIT … #define BNX2_CTX_COMMAND_PAGE_SIZE … #define BNX2_CTX_COMMAND_PAGE_SIZE_256 … #define BNX2_CTX_COMMAND_PAGE_SIZE_512 … #define BNX2_CTX_COMMAND_PAGE_SIZE_1K … #define BNX2_CTX_COMMAND_PAGE_SIZE_2K … #define BNX2_CTX_COMMAND_PAGE_SIZE_4K … #define BNX2_CTX_COMMAND_PAGE_SIZE_8K … #define BNX2_CTX_COMMAND_PAGE_SIZE_16K … #define BNX2_CTX_COMMAND_PAGE_SIZE_32K … #define BNX2_CTX_COMMAND_PAGE_SIZE_64K … #define BNX2_CTX_COMMAND_PAGE_SIZE_128K … #define BNX2_CTX_COMMAND_PAGE_SIZE_256K … #define BNX2_CTX_COMMAND_PAGE_SIZE_512K … #define BNX2_CTX_COMMAND_PAGE_SIZE_1M … #define BNX2_CTX_STATUS … #define BNX2_CTX_STATUS_LOCK_WAIT … #define BNX2_CTX_STATUS_READ_STAT … #define BNX2_CTX_STATUS_WRITE_STAT … #define BNX2_CTX_STATUS_ACC_STALL_STAT … #define BNX2_CTX_STATUS_LOCK_STALL_STAT … #define BNX2_CTX_STATUS_EXT_READ_STAT … #define BNX2_CTX_STATUS_EXT_WRITE_STAT … #define BNX2_CTX_STATUS_MISS_STAT … #define BNX2_CTX_STATUS_HIT_STAT … #define BNX2_CTX_STATUS_DEAD_LOCK … #define BNX2_CTX_STATUS_USAGE_CNT_ERR … #define BNX2_CTX_STATUS_INVALID_PAGE … #define BNX2_CTX_VIRT_ADDR … #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR … #define BNX2_CTX_PAGE_TBL … #define BNX2_CTX_PAGE_TBL_PAGE_TBL … #define BNX2_CTX_DATA_ADR … #define BNX2_CTX_DATA_ADR_DATA_ADR … #define BNX2_CTX_DATA … #define BNX2_CTX_LOCK … #define BNX2_CTX_LOCK_TYPE … #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID … #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL … #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX … #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER … #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE … #define BNX2_CTX_LOCK_TYPE_VOID_XI … #define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI … #define BNX2_CTX_LOCK_TYPE_TX_XI … #define BNX2_CTX_LOCK_TYPE_TIMER_XI … #define BNX2_CTX_LOCK_TYPE_COMPLETE_XI … #define BNX2_CTX_LOCK_CID_VALUE … #define BNX2_CTX_LOCK_GRANTED … #define BNX2_CTX_LOCK_MODE … #define BNX2_CTX_LOCK_MODE_UNLOCK … #define BNX2_CTX_LOCK_MODE_IMMEDIATE … #define BNX2_CTX_LOCK_MODE_SURE … #define BNX2_CTX_LOCK_STATUS … #define BNX2_CTX_LOCK_REQ … #define BNX2_CTX_CTX_CTRL … #define BNX2_CTX_CTX_CTRL_CTX_ADDR … #define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT … #define BNX2_CTX_CTX_CTRL_NO_RAM_ACC … #define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE … #define BNX2_CTX_CTX_CTRL_ATTR … #define BNX2_CTX_CTX_CTRL_WRITE_REQ … #define BNX2_CTX_CTX_CTRL_READ_REQ … #define BNX2_CTX_CTX_DATA … #define BNX2_CTX_ACCESS_STATUS … #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED … #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM … #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM … #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM … #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST … #define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI … #define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI … #define BNX2_CTX_ACCESS_STATUS_REQUEST_XI … #define BNX2_CTX_DBG_LOCK_STATUS … #define BNX2_CTX_DBG_LOCK_STATUS_SM … #define BNX2_CTX_DBG_LOCK_STATUS_MATCH … #define BNX2_CTX_CACHE_CTRL_STATUS … #define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW … #define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP … #define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START … #define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT … #define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE … #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE … #define BNX2_CTX_CACHE_CTRL_SM_STATUS … #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC … #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC … #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC … #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC … #define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR … #define BNX2_CTX_CACHE_STATUS … #define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES … #define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES … #define BNX2_CTX_DMA_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS … #define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS … #define BNX2_CTX_REP_STATUS … #define BNX2_CTX_REP_STATUS_ERROR_ENTRY … #define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID … #define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR … #define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR … #define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR … #define BNX2_CTX_CKSUM_ERROR_STATUS … #define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED … #define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED … #define BNX2_CTX_CHNL_LOCK_STATUS_0 … #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID … #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE … #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE … #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI … #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI … #define BNX2_CTX_CHNL_LOCK_STATUS_1 … #define BNX2_CTX_CHNL_LOCK_STATUS_2 … #define BNX2_CTX_CHNL_LOCK_STATUS_3 … #define BNX2_CTX_CHNL_LOCK_STATUS_4 … #define BNX2_CTX_CHNL_LOCK_STATUS_5 … #define BNX2_CTX_CHNL_LOCK_STATUS_6 … #define BNX2_CTX_CHNL_LOCK_STATUS_7 … #define BNX2_CTX_CHNL_LOCK_STATUS_8 … #define BNX2_CTX_CHNL_LOCK_STATUS_9 … #define BNX2_CTX_CACHE_DATA … #define BNX2_CTX_HOST_PAGE_TBL_CTRL … #define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR … #define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ … #define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ … #define BNX2_CTX_HOST_PAGE_TBL_DATA0 … #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID … #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE … #define BNX2_CTX_HOST_PAGE_TBL_DATA1 … #define BNX2_CTX_CAM_CTRL … #define BNX2_CTX_CAM_CTRL_CAM_ADDR … #define BNX2_CTX_CAM_CTRL_RESET … #define BNX2_CTX_CAM_CTRL_INVALIDATE … #define BNX2_CTX_CAM_CTRL_SEARCH … #define BNX2_CTX_CAM_CTRL_WRITE_REQ … #define BNX2_CTX_CAM_CTRL_READ_REQ … /* * emac_reg definition * offset: 0x1400 */ #define BNX2_EMAC_MODE … #define BNX2_EMAC_MODE_RESET … #define BNX2_EMAC_MODE_HALF_DUPLEX … #define BNX2_EMAC_MODE_PORT … #define BNX2_EMAC_MODE_PORT_NONE … #define BNX2_EMAC_MODE_PORT_MII … #define BNX2_EMAC_MODE_PORT_GMII … #define BNX2_EMAC_MODE_PORT_MII_10M … #define BNX2_EMAC_MODE_MAC_LOOP … #define BNX2_EMAC_MODE_25G_MODE … #define BNX2_EMAC_MODE_TAGGED_MAC_CTL … #define BNX2_EMAC_MODE_TX_BURST … #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA … #define BNX2_EMAC_MODE_EXT_LINK_POL … #define BNX2_EMAC_MODE_FORCE_LINK … #define BNX2_EMAC_MODE_SERDES_MODE … #define BNX2_EMAC_MODE_BOND_OVRD … #define BNX2_EMAC_MODE_MPKT … #define BNX2_EMAC_MODE_MPKT_RCVD … #define BNX2_EMAC_MODE_ACPI_RCVD … #define BNX2_EMAC_STATUS … #define BNX2_EMAC_STATUS_LINK … #define BNX2_EMAC_STATUS_LINK_CHANGE … #define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE … #define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE … #define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE … #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0 … #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE … #define BNX2_EMAC_STATUS_MI_COMPLETE … #define BNX2_EMAC_STATUS_MI_INT … #define BNX2_EMAC_STATUS_AP_ERROR … #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE … #define BNX2_EMAC_ATTENTION_ENA … #define BNX2_EMAC_ATTENTION_ENA_LINK … #define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE … #define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE … #define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE … #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE … #define BNX2_EMAC_ATTENTION_ENA_MI_INT … #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR … #define BNX2_EMAC_LED … #define BNX2_EMAC_LED_OVERRIDE … #define BNX2_EMAC_LED_1000MB_OVERRIDE … #define BNX2_EMAC_LED_100MB_OVERRIDE … #define BNX2_EMAC_LED_10MB_OVERRIDE … #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE … #define BNX2_EMAC_LED_BLNK_TRAFFIC … #define BNX2_EMAC_LED_TRAFFIC … #define BNX2_EMAC_LED_1000MB … #define BNX2_EMAC_LED_100MB … #define BNX2_EMAC_LED_10MB … #define BNX2_EMAC_LED_TRAFFIC_STAT … #define BNX2_EMAC_LED_2500MB … #define BNX2_EMAC_LED_2500MB_OVERRIDE … #define BNX2_EMAC_LED_ACTIVITY_SEL … #define BNX2_EMAC_LED_ACTIVITY_SEL_0 … #define BNX2_EMAC_LED_ACTIVITY_SEL_1 … #define BNX2_EMAC_LED_ACTIVITY_SEL_2 … #define BNX2_EMAC_LED_ACTIVITY_SEL_3 … #define BNX2_EMAC_LED_BLNK_RATE … #define BNX2_EMAC_LED_BLNK_RATE_ENA … #define BNX2_EMAC_MAC_MATCH0 … #define BNX2_EMAC_MAC_MATCH1 … #define BNX2_EMAC_MAC_MATCH2 … #define BNX2_EMAC_MAC_MATCH3 … #define BNX2_EMAC_MAC_MATCH4 … #define BNX2_EMAC_MAC_MATCH5 … #define BNX2_EMAC_MAC_MATCH6 … #define BNX2_EMAC_MAC_MATCH7 … #define BNX2_EMAC_MAC_MATCH8 … #define BNX2_EMAC_MAC_MATCH9 … #define BNX2_EMAC_MAC_MATCH10 … #define BNX2_EMAC_MAC_MATCH11 … #define BNX2_EMAC_MAC_MATCH12 … #define BNX2_EMAC_MAC_MATCH13 … #define BNX2_EMAC_MAC_MATCH14 … #define BNX2_EMAC_MAC_MATCH15 … #define BNX2_EMAC_MAC_MATCH16 … #define BNX2_EMAC_MAC_MATCH17 … #define BNX2_EMAC_MAC_MATCH18 … #define BNX2_EMAC_MAC_MATCH19 … #define BNX2_EMAC_MAC_MATCH20 … #define BNX2_EMAC_MAC_MATCH21 … #define BNX2_EMAC_MAC_MATCH22 … #define BNX2_EMAC_MAC_MATCH23 … #define BNX2_EMAC_MAC_MATCH24 … #define BNX2_EMAC_MAC_MATCH25 … #define BNX2_EMAC_MAC_MATCH26 … #define BNX2_EMAC_MAC_MATCH27 … #define BNX2_EMAC_MAC_MATCH28 … #define BNX2_EMAC_MAC_MATCH29 … #define BNX2_EMAC_MAC_MATCH30 … #define BNX2_EMAC_MAC_MATCH31 … #define BNX2_EMAC_BACKOFF_SEED … #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED … #define BNX2_EMAC_RX_MTU_SIZE … #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE … #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA … #define BNX2_EMAC_SERDES_CNTL … #define BNX2_EMAC_SERDES_CNTL_RXR … #define BNX2_EMAC_SERDES_CNTL_RXG … #define BNX2_EMAC_SERDES_CNTL_RXCKSEL … #define BNX2_EMAC_SERDES_CNTL_TXBIAS … #define BNX2_EMAC_SERDES_CNTL_BGMAX … #define BNX2_EMAC_SERDES_CNTL_BGMIN … #define BNX2_EMAC_SERDES_CNTL_TXMODE … #define BNX2_EMAC_SERDES_CNTL_TXEDGE … #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE … #define BNX2_EMAC_SERDES_CNTL_PLLTEST … #define BNX2_EMAC_SERDES_CNTL_CDET_EN … #define BNX2_EMAC_SERDES_CNTL_TBI_LBK … #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK … #define BNX2_EMAC_SERDES_CNTL_REV_PHASE … #define BNX2_EMAC_SERDES_CNTL_REGCTL12 … #define BNX2_EMAC_SERDES_CNTL_REGCTL25 … #define BNX2_EMAC_SERDES_STATUS … #define BNX2_EMAC_SERDES_STATUS_RX_STAT … #define BNX2_EMAC_SERDES_STATUS_COMMA_DET … #define BNX2_EMAC_MDIO_COMM … #define BNX2_EMAC_MDIO_COMM_DATA … #define BNX2_EMAC_MDIO_COMM_REG_ADDR … #define BNX2_EMAC_MDIO_COMM_PHY_ADDR … #define BNX2_EMAC_MDIO_COMM_COMMAND … #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 … #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS … #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE … #define BNX2_EMAC_MDIO_COMM_COMMAND_READ … #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI … #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI … #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI … #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI … #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 … #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45 … #define BNX2_EMAC_MDIO_COMM_FAIL … #define BNX2_EMAC_MDIO_COMM_START_BUSY … #define BNX2_EMAC_MDIO_COMM_DISEXT … #define BNX2_EMAC_MDIO_STATUS … #define BNX2_EMAC_MDIO_STATUS_LINK … #define BNX2_EMAC_MDIO_STATUS_10MB … #define BNX2_EMAC_MDIO_MODE … #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE … #define BNX2_EMAC_MDIO_MODE_AUTO_POLL … #define BNX2_EMAC_MDIO_MODE_BIT_BANG … #define BNX2_EMAC_MDIO_MODE_MDIO … #define BNX2_EMAC_MDIO_MODE_MDIO_OE … #define BNX2_EMAC_MDIO_MODE_MDC … #define BNX2_EMAC_MDIO_MODE_MDINT … #define BNX2_EMAC_MDIO_MODE_EXT_MDINT … #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT … #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI … #define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI … #define BNX2_EMAC_MDIO_AUTO_STATUS … #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR … #define BNX2_EMAC_TX_MODE … #define BNX2_EMAC_TX_MODE_RESET … #define BNX2_EMAC_TX_MODE_CS16_TEST … #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN … #define BNX2_EMAC_TX_MODE_FLOW_EN … #define BNX2_EMAC_TX_MODE_BIG_BACKOFF … #define BNX2_EMAC_TX_MODE_LONG_PAUSE … #define BNX2_EMAC_TX_MODE_LINK_AWARE … #define BNX2_EMAC_TX_STATUS … #define BNX2_EMAC_TX_STATUS_XOFFED … #define BNX2_EMAC_TX_STATUS_XOFF_SENT … #define BNX2_EMAC_TX_STATUS_XON_SENT … #define BNX2_EMAC_TX_STATUS_LINK_UP … #define BNX2_EMAC_TX_STATUS_UNDERRUN … #define BNX2_EMAC_TX_STATUS_CS16_ERROR … #define BNX2_EMAC_TX_LENGTHS … #define BNX2_EMAC_TX_LENGTHS_SLOT … #define BNX2_EMAC_TX_LENGTHS_IPG … #define BNX2_EMAC_TX_LENGTHS_IPG_CRS … #define BNX2_EMAC_RX_MODE … #define BNX2_EMAC_RX_MODE_RESET … #define BNX2_EMAC_RX_MODE_FLOW_EN … #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL … #define BNX2_EMAC_RX_MODE_KEEP_PAUSE … #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE … #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS … #define BNX2_EMAC_RX_MODE_LLC_CHK … #define BNX2_EMAC_RX_MODE_PROMISCUOUS … #define BNX2_EMAC_RX_MODE_NO_CRC_CHK … #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG … #define BNX2_EMAC_RX_MODE_FILT_BROADCAST … #define BNX2_EMAC_RX_MODE_SORT_MODE … #define BNX2_EMAC_RX_STATUS … #define BNX2_EMAC_RX_STATUS_FFED … #define BNX2_EMAC_RX_STATUS_FF_RECEIVED … #define BNX2_EMAC_RX_STATUS_N_RECEIVED … #define BNX2_EMAC_MULTICAST_HASH0 … #define BNX2_EMAC_MULTICAST_HASH1 … #define BNX2_EMAC_MULTICAST_HASH2 … #define BNX2_EMAC_MULTICAST_HASH3 … #define BNX2_EMAC_MULTICAST_HASH4 … #define BNX2_EMAC_MULTICAST_HASH5 … #define BNX2_EMAC_MULTICAST_HASH6 … #define BNX2_EMAC_MULTICAST_HASH7 … #define BNX2_EMAC_CKSUM_ERROR_STATUS … #define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED … #define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED … #define BNX2_EMAC_RX_STAT_IFHCINOCTETS … #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS … #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS … #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS … #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS … #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS … #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS … #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS … #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS … #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED … #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED … #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED … #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED … #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG … #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS … #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS … #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS … #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS … #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS … #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS … #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS … #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS … #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS … #define BNX2_EMAC_RXMAC_DEBUG0 … #define BNX2_EMAC_RXMAC_DEBUG1 … #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT … #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE … #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC … #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR … #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR … #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA … #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START … #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT … #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME … #define BNX2_EMAC_RXMAC_DEBUG2 … #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE … #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE … #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD … #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA … #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP … #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT … #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP … #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP … #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC … #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE … #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE … #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 … #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 … #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 … #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 … #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT … #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT … #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS … #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST … #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN … #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC … #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED … #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE … #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE … #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED … #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER … #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA … #define BNX2_EMAC_RXMAC_DEBUG3 … #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR … #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR … #define BNX2_EMAC_RXMAC_DEBUG4 … #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE … #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP … #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT … #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED … #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER … #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA … #define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND … #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE … #define BNX2_EMAC_RXMAC_DEBUG4_START … #define BNX2_EMAC_RXMAC_DEBUG5 … #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM … #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE … #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF … #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT … #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC … #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE … #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL … #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT … #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 … #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW … #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT … #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF … #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF … #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF … #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF … #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF … #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED … #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 … #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL … #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE … #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA … #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT … #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT … #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE … #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT … #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN … #define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS … #define BNX2_EMAC_RX_STAT_AC0 … #define BNX2_EMAC_RX_STAT_AC1 … #define BNX2_EMAC_RX_STAT_AC2 … #define BNX2_EMAC_RX_STAT_AC3 … #define BNX2_EMAC_RX_STAT_AC4 … #define BNX2_EMAC_RX_STAT_AC5 … #define BNX2_EMAC_RX_STAT_AC6 … #define BNX2_EMAC_RX_STAT_AC7 … #define BNX2_EMAC_RX_STAT_AC8 … #define BNX2_EMAC_RX_STAT_AC9 … #define BNX2_EMAC_RX_STAT_AC10 … #define BNX2_EMAC_RX_STAT_AC11 … #define BNX2_EMAC_RX_STAT_AC12 … #define BNX2_EMAC_RX_STAT_AC13 … #define BNX2_EMAC_RX_STAT_AC14 … #define BNX2_EMAC_RX_STAT_AC15 … #define BNX2_EMAC_RX_STAT_AC16 … #define BNX2_EMAC_RX_STAT_AC17 … #define BNX2_EMAC_RX_STAT_AC18 … #define BNX2_EMAC_RX_STAT_AC19 … #define BNX2_EMAC_RX_STAT_AC20 … #define BNX2_EMAC_RX_STAT_AC21 … #define BNX2_EMAC_RX_STAT_AC22 … #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC … #define BNX2_EMAC_RX_STAT_AC_28 … #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS … #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS … #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS … #define BNX2_EMAC_TX_STAT_OUTXONSENT … #define BNX2_EMAC_TX_STAT_OUTXOFFSENT … #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE … #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES … #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES … #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS … #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS … #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS … #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS … #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS … #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS … #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS … #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS … #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS … #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS … #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS … #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS … #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS … #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS … #define BNX2_EMAC_TXMAC_DEBUG0 … #define BNX2_EMAC_TXMAC_DEBUG1 … #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE … #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE … #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 … #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 … #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 … #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 … #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 … #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 … #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 … #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE … #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC … #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER … #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE … #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION … #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER … #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED … #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE … #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME … #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME … #define BNX2_EMAC_TXMAC_DEBUG2 … #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF … #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT … #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT … #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT … #define BNX2_EMAC_TXMAC_DEBUG3 … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT … #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF … #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE … #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE … #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT … #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI … #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC … #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 … #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 … #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC … #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE … #define BNX2_EMAC_TXMAC_DEBUG3_XOFF … #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER … #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER … #define BNX2_EMAC_TXMAC_DEBUG4 … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT … #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD … #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID … #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC … #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED … #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER … #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND … #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING … #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC … #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING … #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN … #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING … #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE … #define BNX2_EMAC_TXMAC_DEBUG4_GO … #define BNX2_EMAC_TX_STAT_AC0 … #define BNX2_EMAC_TX_STAT_AC1 … #define BNX2_EMAC_TX_STAT_AC2 … #define BNX2_EMAC_TX_STAT_AC3 … #define BNX2_EMAC_TX_STAT_AC4 … #define BNX2_EMAC_TX_STAT_AC5 … #define BNX2_EMAC_TX_STAT_AC6 … #define BNX2_EMAC_TX_STAT_AC7 … #define BNX2_EMAC_TX_STAT_AC8 … #define BNX2_EMAC_TX_STAT_AC9 … #define BNX2_EMAC_TX_STAT_AC10 … #define BNX2_EMAC_TX_STAT_AC11 … #define BNX2_EMAC_TX_STAT_AC12 … #define BNX2_EMAC_TX_STAT_AC13 … #define BNX2_EMAC_TX_STAT_AC14 … #define BNX2_EMAC_TX_STAT_AC15 … #define BNX2_EMAC_TX_STAT_AC16 … #define BNX2_EMAC_TX_STAT_AC17 … #define BNX2_EMAC_TX_STAT_AC18 … #define BNX2_EMAC_TX_STAT_AC19 … #define BNX2_EMAC_TX_STAT_AC20 … #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC … #define BNX2_EMAC_TX_RATE_LIMIT_CTRL … #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC … #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM … #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN … /* * rpm_reg definition * offset: 0x1800 */ #define BNX2_RPM_COMMAND … #define BNX2_RPM_COMMAND_ENABLED … #define BNX2_RPM_COMMAND_OVERRUN_ABORT … #define BNX2_RPM_STATUS … #define BNX2_RPM_STATUS_MBUF_WAIT … #define BNX2_RPM_STATUS_FREE_WAIT … #define BNX2_RPM_CONFIG … #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM … #define BNX2_RPM_CONFIG_ACPI_ENA … #define BNX2_RPM_CONFIG_ACPI_KEEP … #define BNX2_RPM_CONFIG_MP_KEEP … #define BNX2_RPM_CONFIG_SORT_VECT_VAL … #define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT … #define BNX2_RPM_CONFIG_IGNORE_VLAN … #define BNX2_RPM_MGMT_PKT_CTRL … #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT … #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE … #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN … #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN … #define BNX2_RPM_VLAN_MATCH0 … #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE … #define BNX2_RPM_VLAN_MATCH1 … #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE … #define BNX2_RPM_VLAN_MATCH2 … #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE … #define BNX2_RPM_VLAN_MATCH3 … #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE … #define BNX2_RPM_SORT_USER0 … #define BNX2_RPM_SORT_USER0_PM_EN … #define BNX2_RPM_SORT_USER0_BC_EN … #define BNX2_RPM_SORT_USER0_MC_EN … #define BNX2_RPM_SORT_USER0_MC_HSH_EN … #define BNX2_RPM_SORT_USER0_PROM_EN … #define BNX2_RPM_SORT_USER0_VLAN_EN … #define BNX2_RPM_SORT_USER0_PROM_VLAN … #define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH … #define BNX2_RPM_SORT_USER0_ENA … #define BNX2_RPM_SORT_USER1 … #define BNX2_RPM_SORT_USER1_PM_EN … #define BNX2_RPM_SORT_USER1_BC_EN … #define BNX2_RPM_SORT_USER1_MC_EN … #define BNX2_RPM_SORT_USER1_MC_HSH_EN … #define BNX2_RPM_SORT_USER1_PROM_EN … #define BNX2_RPM_SORT_USER1_VLAN_EN … #define BNX2_RPM_SORT_USER1_PROM_VLAN … #define BNX2_RPM_SORT_USER1_ENA … #define BNX2_RPM_SORT_USER2 … #define BNX2_RPM_SORT_USER2_PM_EN … #define BNX2_RPM_SORT_USER2_BC_EN … #define BNX2_RPM_SORT_USER2_MC_EN … #define BNX2_RPM_SORT_USER2_MC_HSH_EN … #define BNX2_RPM_SORT_USER2_PROM_EN … #define BNX2_RPM_SORT_USER2_VLAN_EN … #define BNX2_RPM_SORT_USER2_PROM_VLAN … #define BNX2_RPM_SORT_USER2_ENA … #define BNX2_RPM_SORT_USER3 … #define BNX2_RPM_SORT_USER3_PM_EN … #define BNX2_RPM_SORT_USER3_BC_EN … #define BNX2_RPM_SORT_USER3_MC_EN … #define BNX2_RPM_SORT_USER3_MC_HSH_EN … #define BNX2_RPM_SORT_USER3_PROM_EN … #define BNX2_RPM_SORT_USER3_VLAN_EN … #define BNX2_RPM_SORT_USER3_PROM_VLAN … #define BNX2_RPM_SORT_USER3_ENA … #define BNX2_RPM_STAT_L2_FILTER_DISCARDS … #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS … #define BNX2_RPM_STAT_IFINFTQDISCARDS … #define BNX2_RPM_STAT_IFINMBUFDISCARD … #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0 … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1 … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2 … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3 … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4 … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5 … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6 … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7 … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE … #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN … #define BNX2_RPM_STAT_AC0 … #define BNX2_RPM_STAT_AC1 … #define BNX2_RPM_STAT_AC2 … #define BNX2_RPM_STAT_AC3 … #define BNX2_RPM_STAT_AC4 … #define BNX2_RPM_RC_CNTL_16 … #define BNX2_RPM_RC_CNTL_16_OFFSET … #define BNX2_RPM_RC_CNTL_16_CLASS … #define BNX2_RPM_RC_CNTL_16_PRIORITY … #define BNX2_RPM_RC_CNTL_16_P4 … #define BNX2_RPM_RC_CNTL_16_HDR_TYPE … #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START … #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP … #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP … #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP … #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA … #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP … #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6 … #define BNX2_RPM_RC_CNTL_16_COMP … #define BNX2_RPM_RC_CNTL_16_COMP_EQUAL … #define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL … #define BNX2_RPM_RC_CNTL_16_COMP_GREATER … #define BNX2_RPM_RC_CNTL_16_COMP_LESS … #define BNX2_RPM_RC_CNTL_16_MAP … #define BNX2_RPM_RC_CNTL_16_SBIT … #define BNX2_RPM_RC_CNTL_16_CMDSEL … #define BNX2_RPM_RC_CNTL_16_DISCARD … #define BNX2_RPM_RC_CNTL_16_MASK … #define BNX2_RPM_RC_CNTL_16_P1 … #define BNX2_RPM_RC_CNTL_16_P2 … #define BNX2_RPM_RC_CNTL_16_P3 … #define BNX2_RPM_RC_CNTL_16_NBIT … #define BNX2_RPM_RC_VALUE_MASK_16 … #define BNX2_RPM_RC_VALUE_MASK_16_VALUE … #define BNX2_RPM_RC_VALUE_MASK_16_MASK … #define BNX2_RPM_RC_CNTL_17 … #define BNX2_RPM_RC_CNTL_17_OFFSET … #define BNX2_RPM_RC_CNTL_17_CLASS … #define BNX2_RPM_RC_CNTL_17_PRIORITY … #define BNX2_RPM_RC_CNTL_17_P4 … #define BNX2_RPM_RC_CNTL_17_HDR_TYPE … #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START … #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP … #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP … #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP … #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA … #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP … #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6 … #define BNX2_RPM_RC_CNTL_17_COMP … #define BNX2_RPM_RC_CNTL_17_COMP_EQUAL … #define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL … #define BNX2_RPM_RC_CNTL_17_COMP_GREATER … #define BNX2_RPM_RC_CNTL_17_COMP_LESS … #define BNX2_RPM_RC_CNTL_17_MAP … #define BNX2_RPM_RC_CNTL_17_SBIT … #define BNX2_RPM_RC_CNTL_17_CMDSEL … #define BNX2_RPM_RC_CNTL_17_DISCARD … #define BNX2_RPM_RC_CNTL_17_MASK … #define BNX2_RPM_RC_CNTL_17_P1 … #define BNX2_RPM_RC_CNTL_17_P2 … #define BNX2_RPM_RC_CNTL_17_P3 … #define BNX2_RPM_RC_CNTL_17_NBIT … #define BNX2_RPM_RC_VALUE_MASK_17 … #define BNX2_RPM_RC_VALUE_MASK_17_VALUE … #define BNX2_RPM_RC_VALUE_MASK_17_MASK … #define BNX2_RPM_RC_CNTL_18 … #define BNX2_RPM_RC_CNTL_18_OFFSET … #define BNX2_RPM_RC_CNTL_18_CLASS … #define BNX2_RPM_RC_CNTL_18_PRIORITY … #define BNX2_RPM_RC_CNTL_18_P4 … #define BNX2_RPM_RC_CNTL_18_HDR_TYPE … #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START … #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP … #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP … #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP … #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA … #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP … #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6 … #define BNX2_RPM_RC_CNTL_18_COMP … #define BNX2_RPM_RC_CNTL_18_COMP_EQUAL … #define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL … #define BNX2_RPM_RC_CNTL_18_COMP_GREATER … #define BNX2_RPM_RC_CNTL_18_COMP_LESS … #define BNX2_RPM_RC_CNTL_18_MAP … #define BNX2_RPM_RC_CNTL_18_SBIT … #define BNX2_RPM_RC_CNTL_18_CMDSEL … #define BNX2_RPM_RC_CNTL_18_DISCARD … #define BNX2_RPM_RC_CNTL_18_MASK … #define BNX2_RPM_RC_CNTL_18_P1 … #define BNX2_RPM_RC_CNTL_18_P2 … #define BNX2_RPM_RC_CNTL_18_P3 … #define BNX2_RPM_RC_CNTL_18_NBIT … #define BNX2_RPM_RC_VALUE_MASK_18 … #define BNX2_RPM_RC_VALUE_MASK_18_VALUE … #define BNX2_RPM_RC_VALUE_MASK_18_MASK … #define BNX2_RPM_RC_CNTL_19 … #define BNX2_RPM_RC_CNTL_19_OFFSET … #define BNX2_RPM_RC_CNTL_19_CLASS … #define BNX2_RPM_RC_CNTL_19_PRIORITY … #define BNX2_RPM_RC_CNTL_19_P4 … #define BNX2_RPM_RC_CNTL_19_HDR_TYPE … #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START … #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP … #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP … #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP … #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA … #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP … #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6 … #define BNX2_RPM_RC_CNTL_19_COMP … #define BNX2_RPM_RC_CNTL_19_COMP_EQUAL … #define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL … #define BNX2_RPM_RC_CNTL_19_COMP_GREATER … #define BNX2_RPM_RC_CNTL_19_COMP_LESS … #define BNX2_RPM_RC_CNTL_19_MAP … #define BNX2_RPM_RC_CNTL_19_SBIT … #define BNX2_RPM_RC_CNTL_19_CMDSEL … #define BNX2_RPM_RC_CNTL_19_DISCARD … #define BNX2_RPM_RC_CNTL_19_MASK … #define BNX2_RPM_RC_CNTL_19_P1 … #define BNX2_RPM_RC_CNTL_19_P2 … #define BNX2_RPM_RC_CNTL_19_P3 … #define BNX2_RPM_RC_CNTL_19_NBIT … #define BNX2_RPM_RC_VALUE_MASK_19 … #define BNX2_RPM_RC_VALUE_MASK_19_VALUE … #define BNX2_RPM_RC_VALUE_MASK_19_MASK … #define BNX2_RPM_RC_CNTL_0 … #define BNX2_RPM_RC_CNTL_0_OFFSET … #define BNX2_RPM_RC_CNTL_0_CLASS … #define BNX2_RPM_RC_CNTL_0_PRIORITY … #define BNX2_RPM_RC_CNTL_0_P4 … #define BNX2_RPM_RC_CNTL_0_HDR_TYPE … #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START … #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP … #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP … #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP … #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA … #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP … #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6 … #define BNX2_RPM_RC_CNTL_0_COMP … #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL … #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL … #define BNX2_RPM_RC_CNTL_0_COMP_GREATER … #define BNX2_RPM_RC_CNTL_0_COMP_LESS … #define BNX2_RPM_RC_CNTL_0_MAP_XI … #define BNX2_RPM_RC_CNTL_0_SBIT … #define BNX2_RPM_RC_CNTL_0_CMDSEL … #define BNX2_RPM_RC_CNTL_0_MAP … #define BNX2_RPM_RC_CNTL_0_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_0_DISCARD … #define BNX2_RPM_RC_CNTL_0_MASK … #define BNX2_RPM_RC_CNTL_0_P1 … #define BNX2_RPM_RC_CNTL_0_P2 … #define BNX2_RPM_RC_CNTL_0_P3 … #define BNX2_RPM_RC_CNTL_0_NBIT … #define BNX2_RPM_RC_VALUE_MASK_0 … #define BNX2_RPM_RC_VALUE_MASK_0_VALUE … #define BNX2_RPM_RC_VALUE_MASK_0_MASK … #define BNX2_RPM_RC_CNTL_1 … #define BNX2_RPM_RC_CNTL_1_A … #define BNX2_RPM_RC_CNTL_1_B … #define BNX2_RPM_RC_CNTL_1_OFFSET_XI … #define BNX2_RPM_RC_CNTL_1_CLASS_XI … #define BNX2_RPM_RC_CNTL_1_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_1_P4_XI … #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_1_COMP_XI … #define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_1_MAP_XI … #define BNX2_RPM_RC_CNTL_1_SBIT_XI … #define BNX2_RPM_RC_CNTL_1_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_1_DISCARD_XI … #define BNX2_RPM_RC_CNTL_1_MASK_XI … #define BNX2_RPM_RC_CNTL_1_P1_XI … #define BNX2_RPM_RC_CNTL_1_P2_XI … #define BNX2_RPM_RC_CNTL_1_P3_XI … #define BNX2_RPM_RC_CNTL_1_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_1 … #define BNX2_RPM_RC_VALUE_MASK_1_VALUE … #define BNX2_RPM_RC_VALUE_MASK_1_MASK … #define BNX2_RPM_RC_CNTL_2 … #define BNX2_RPM_RC_CNTL_2_A … #define BNX2_RPM_RC_CNTL_2_B … #define BNX2_RPM_RC_CNTL_2_OFFSET_XI … #define BNX2_RPM_RC_CNTL_2_CLASS_XI … #define BNX2_RPM_RC_CNTL_2_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_2_P4_XI … #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_2_COMP_XI … #define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_2_MAP_XI … #define BNX2_RPM_RC_CNTL_2_SBIT_XI … #define BNX2_RPM_RC_CNTL_2_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_2_DISCARD_XI … #define BNX2_RPM_RC_CNTL_2_MASK_XI … #define BNX2_RPM_RC_CNTL_2_P1_XI … #define BNX2_RPM_RC_CNTL_2_P2_XI … #define BNX2_RPM_RC_CNTL_2_P3_XI … #define BNX2_RPM_RC_CNTL_2_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_2 … #define BNX2_RPM_RC_VALUE_MASK_2_VALUE … #define BNX2_RPM_RC_VALUE_MASK_2_MASK … #define BNX2_RPM_RC_CNTL_3 … #define BNX2_RPM_RC_CNTL_3_A … #define BNX2_RPM_RC_CNTL_3_B … #define BNX2_RPM_RC_CNTL_3_OFFSET_XI … #define BNX2_RPM_RC_CNTL_3_CLASS_XI … #define BNX2_RPM_RC_CNTL_3_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_3_P4_XI … #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_3_COMP_XI … #define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_3_MAP_XI … #define BNX2_RPM_RC_CNTL_3_SBIT_XI … #define BNX2_RPM_RC_CNTL_3_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_3_DISCARD_XI … #define BNX2_RPM_RC_CNTL_3_MASK_XI … #define BNX2_RPM_RC_CNTL_3_P1_XI … #define BNX2_RPM_RC_CNTL_3_P2_XI … #define BNX2_RPM_RC_CNTL_3_P3_XI … #define BNX2_RPM_RC_CNTL_3_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_3 … #define BNX2_RPM_RC_VALUE_MASK_3_VALUE … #define BNX2_RPM_RC_VALUE_MASK_3_MASK … #define BNX2_RPM_RC_CNTL_4 … #define BNX2_RPM_RC_CNTL_4_A … #define BNX2_RPM_RC_CNTL_4_B … #define BNX2_RPM_RC_CNTL_4_OFFSET_XI … #define BNX2_RPM_RC_CNTL_4_CLASS_XI … #define BNX2_RPM_RC_CNTL_4_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_4_P4_XI … #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_4_COMP_XI … #define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_4_MAP_XI … #define BNX2_RPM_RC_CNTL_4_SBIT_XI … #define BNX2_RPM_RC_CNTL_4_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_4_DISCARD_XI … #define BNX2_RPM_RC_CNTL_4_MASK_XI … #define BNX2_RPM_RC_CNTL_4_P1_XI … #define BNX2_RPM_RC_CNTL_4_P2_XI … #define BNX2_RPM_RC_CNTL_4_P3_XI … #define BNX2_RPM_RC_CNTL_4_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_4 … #define BNX2_RPM_RC_VALUE_MASK_4_VALUE … #define BNX2_RPM_RC_VALUE_MASK_4_MASK … #define BNX2_RPM_RC_CNTL_5 … #define BNX2_RPM_RC_CNTL_5_A … #define BNX2_RPM_RC_CNTL_5_B … #define BNX2_RPM_RC_CNTL_5_OFFSET_XI … #define BNX2_RPM_RC_CNTL_5_CLASS_XI … #define BNX2_RPM_RC_CNTL_5_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_5_P4_XI … #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_5_COMP_XI … #define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_5_MAP_XI … #define BNX2_RPM_RC_CNTL_5_SBIT_XI … #define BNX2_RPM_RC_CNTL_5_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_5_DISCARD_XI … #define BNX2_RPM_RC_CNTL_5_MASK_XI … #define BNX2_RPM_RC_CNTL_5_P1_XI … #define BNX2_RPM_RC_CNTL_5_P2_XI … #define BNX2_RPM_RC_CNTL_5_P3_XI … #define BNX2_RPM_RC_CNTL_5_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_5 … #define BNX2_RPM_RC_VALUE_MASK_5_VALUE … #define BNX2_RPM_RC_VALUE_MASK_5_MASK … #define BNX2_RPM_RC_CNTL_6 … #define BNX2_RPM_RC_CNTL_6_A … #define BNX2_RPM_RC_CNTL_6_B … #define BNX2_RPM_RC_CNTL_6_OFFSET_XI … #define BNX2_RPM_RC_CNTL_6_CLASS_XI … #define BNX2_RPM_RC_CNTL_6_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_6_P4_XI … #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_6_COMP_XI … #define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_6_MAP_XI … #define BNX2_RPM_RC_CNTL_6_SBIT_XI … #define BNX2_RPM_RC_CNTL_6_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_6_DISCARD_XI … #define BNX2_RPM_RC_CNTL_6_MASK_XI … #define BNX2_RPM_RC_CNTL_6_P1_XI … #define BNX2_RPM_RC_CNTL_6_P2_XI … #define BNX2_RPM_RC_CNTL_6_P3_XI … #define BNX2_RPM_RC_CNTL_6_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_6 … #define BNX2_RPM_RC_VALUE_MASK_6_VALUE … #define BNX2_RPM_RC_VALUE_MASK_6_MASK … #define BNX2_RPM_RC_CNTL_7 … #define BNX2_RPM_RC_CNTL_7_A … #define BNX2_RPM_RC_CNTL_7_B … #define BNX2_RPM_RC_CNTL_7_OFFSET_XI … #define BNX2_RPM_RC_CNTL_7_CLASS_XI … #define BNX2_RPM_RC_CNTL_7_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_7_P4_XI … #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_7_COMP_XI … #define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_7_MAP_XI … #define BNX2_RPM_RC_CNTL_7_SBIT_XI … #define BNX2_RPM_RC_CNTL_7_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_7_DISCARD_XI … #define BNX2_RPM_RC_CNTL_7_MASK_XI … #define BNX2_RPM_RC_CNTL_7_P1_XI … #define BNX2_RPM_RC_CNTL_7_P2_XI … #define BNX2_RPM_RC_CNTL_7_P3_XI … #define BNX2_RPM_RC_CNTL_7_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_7 … #define BNX2_RPM_RC_VALUE_MASK_7_VALUE … #define BNX2_RPM_RC_VALUE_MASK_7_MASK … #define BNX2_RPM_RC_CNTL_8 … #define BNX2_RPM_RC_CNTL_8_A … #define BNX2_RPM_RC_CNTL_8_B … #define BNX2_RPM_RC_CNTL_8_OFFSET_XI … #define BNX2_RPM_RC_CNTL_8_CLASS_XI … #define BNX2_RPM_RC_CNTL_8_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_8_P4_XI … #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_8_COMP_XI … #define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_8_MAP_XI … #define BNX2_RPM_RC_CNTL_8_SBIT_XI … #define BNX2_RPM_RC_CNTL_8_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_8_DISCARD_XI … #define BNX2_RPM_RC_CNTL_8_MASK_XI … #define BNX2_RPM_RC_CNTL_8_P1_XI … #define BNX2_RPM_RC_CNTL_8_P2_XI … #define BNX2_RPM_RC_CNTL_8_P3_XI … #define BNX2_RPM_RC_CNTL_8_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_8 … #define BNX2_RPM_RC_VALUE_MASK_8_VALUE … #define BNX2_RPM_RC_VALUE_MASK_8_MASK … #define BNX2_RPM_RC_CNTL_9 … #define BNX2_RPM_RC_CNTL_9_A … #define BNX2_RPM_RC_CNTL_9_B … #define BNX2_RPM_RC_CNTL_9_OFFSET_XI … #define BNX2_RPM_RC_CNTL_9_CLASS_XI … #define BNX2_RPM_RC_CNTL_9_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_9_P4_XI … #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_9_COMP_XI … #define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_9_MAP_XI … #define BNX2_RPM_RC_CNTL_9_SBIT_XI … #define BNX2_RPM_RC_CNTL_9_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_9_DISCARD_XI … #define BNX2_RPM_RC_CNTL_9_MASK_XI … #define BNX2_RPM_RC_CNTL_9_P1_XI … #define BNX2_RPM_RC_CNTL_9_P2_XI … #define BNX2_RPM_RC_CNTL_9_P3_XI … #define BNX2_RPM_RC_CNTL_9_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_9 … #define BNX2_RPM_RC_VALUE_MASK_9_VALUE … #define BNX2_RPM_RC_VALUE_MASK_9_MASK … #define BNX2_RPM_RC_CNTL_10 … #define BNX2_RPM_RC_CNTL_10_A … #define BNX2_RPM_RC_CNTL_10_B … #define BNX2_RPM_RC_CNTL_10_OFFSET_XI … #define BNX2_RPM_RC_CNTL_10_CLASS_XI … #define BNX2_RPM_RC_CNTL_10_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_10_P4_XI … #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_10_COMP_XI … #define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_10_MAP_XI … #define BNX2_RPM_RC_CNTL_10_SBIT_XI … #define BNX2_RPM_RC_CNTL_10_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_10_DISCARD_XI … #define BNX2_RPM_RC_CNTL_10_MASK_XI … #define BNX2_RPM_RC_CNTL_10_P1_XI … #define BNX2_RPM_RC_CNTL_10_P2_XI … #define BNX2_RPM_RC_CNTL_10_P3_XI … #define BNX2_RPM_RC_CNTL_10_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_10 … #define BNX2_RPM_RC_VALUE_MASK_10_VALUE … #define BNX2_RPM_RC_VALUE_MASK_10_MASK … #define BNX2_RPM_RC_CNTL_11 … #define BNX2_RPM_RC_CNTL_11_A … #define BNX2_RPM_RC_CNTL_11_B … #define BNX2_RPM_RC_CNTL_11_OFFSET_XI … #define BNX2_RPM_RC_CNTL_11_CLASS_XI … #define BNX2_RPM_RC_CNTL_11_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_11_P4_XI … #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_11_COMP_XI … #define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_11_MAP_XI … #define BNX2_RPM_RC_CNTL_11_SBIT_XI … #define BNX2_RPM_RC_CNTL_11_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_11_DISCARD_XI … #define BNX2_RPM_RC_CNTL_11_MASK_XI … #define BNX2_RPM_RC_CNTL_11_P1_XI … #define BNX2_RPM_RC_CNTL_11_P2_XI … #define BNX2_RPM_RC_CNTL_11_P3_XI … #define BNX2_RPM_RC_CNTL_11_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_11 … #define BNX2_RPM_RC_VALUE_MASK_11_VALUE … #define BNX2_RPM_RC_VALUE_MASK_11_MASK … #define BNX2_RPM_RC_CNTL_12 … #define BNX2_RPM_RC_CNTL_12_A … #define BNX2_RPM_RC_CNTL_12_B … #define BNX2_RPM_RC_CNTL_12_OFFSET_XI … #define BNX2_RPM_RC_CNTL_12_CLASS_XI … #define BNX2_RPM_RC_CNTL_12_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_12_P4_XI … #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_12_COMP_XI … #define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_12_MAP_XI … #define BNX2_RPM_RC_CNTL_12_SBIT_XI … #define BNX2_RPM_RC_CNTL_12_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_12_DISCARD_XI … #define BNX2_RPM_RC_CNTL_12_MASK_XI … #define BNX2_RPM_RC_CNTL_12_P1_XI … #define BNX2_RPM_RC_CNTL_12_P2_XI … #define BNX2_RPM_RC_CNTL_12_P3_XI … #define BNX2_RPM_RC_CNTL_12_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_12 … #define BNX2_RPM_RC_VALUE_MASK_12_VALUE … #define BNX2_RPM_RC_VALUE_MASK_12_MASK … #define BNX2_RPM_RC_CNTL_13 … #define BNX2_RPM_RC_CNTL_13_A … #define BNX2_RPM_RC_CNTL_13_B … #define BNX2_RPM_RC_CNTL_13_OFFSET_XI … #define BNX2_RPM_RC_CNTL_13_CLASS_XI … #define BNX2_RPM_RC_CNTL_13_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_13_P4_XI … #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_13_COMP_XI … #define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_13_MAP_XI … #define BNX2_RPM_RC_CNTL_13_SBIT_XI … #define BNX2_RPM_RC_CNTL_13_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_13_DISCARD_XI … #define BNX2_RPM_RC_CNTL_13_MASK_XI … #define BNX2_RPM_RC_CNTL_13_P1_XI … #define BNX2_RPM_RC_CNTL_13_P2_XI … #define BNX2_RPM_RC_CNTL_13_P3_XI … #define BNX2_RPM_RC_CNTL_13_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_13 … #define BNX2_RPM_RC_VALUE_MASK_13_VALUE … #define BNX2_RPM_RC_VALUE_MASK_13_MASK … #define BNX2_RPM_RC_CNTL_14 … #define BNX2_RPM_RC_CNTL_14_A … #define BNX2_RPM_RC_CNTL_14_B … #define BNX2_RPM_RC_CNTL_14_OFFSET_XI … #define BNX2_RPM_RC_CNTL_14_CLASS_XI … #define BNX2_RPM_RC_CNTL_14_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_14_P4_XI … #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_14_COMP_XI … #define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_14_MAP_XI … #define BNX2_RPM_RC_CNTL_14_SBIT_XI … #define BNX2_RPM_RC_CNTL_14_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_14_DISCARD_XI … #define BNX2_RPM_RC_CNTL_14_MASK_XI … #define BNX2_RPM_RC_CNTL_14_P1_XI … #define BNX2_RPM_RC_CNTL_14_P2_XI … #define BNX2_RPM_RC_CNTL_14_P3_XI … #define BNX2_RPM_RC_CNTL_14_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_14 … #define BNX2_RPM_RC_VALUE_MASK_14_VALUE … #define BNX2_RPM_RC_VALUE_MASK_14_MASK … #define BNX2_RPM_RC_CNTL_15 … #define BNX2_RPM_RC_CNTL_15_A … #define BNX2_RPM_RC_CNTL_15_B … #define BNX2_RPM_RC_CNTL_15_OFFSET_XI … #define BNX2_RPM_RC_CNTL_15_CLASS_XI … #define BNX2_RPM_RC_CNTL_15_PRIORITY_XI … #define BNX2_RPM_RC_CNTL_15_P4_XI … #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI … #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI … #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI … #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI … #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI … #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI … #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI … #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI … #define BNX2_RPM_RC_CNTL_15_COMP_XI … #define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI … #define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI … #define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI … #define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI … #define BNX2_RPM_RC_CNTL_15_MAP_XI … #define BNX2_RPM_RC_CNTL_15_SBIT_XI … #define BNX2_RPM_RC_CNTL_15_CMDSEL_XI … #define BNX2_RPM_RC_CNTL_15_DISCARD_XI … #define BNX2_RPM_RC_CNTL_15_MASK_XI … #define BNX2_RPM_RC_CNTL_15_P1_XI … #define BNX2_RPM_RC_CNTL_15_P2_XI … #define BNX2_RPM_RC_CNTL_15_P3_XI … #define BNX2_RPM_RC_CNTL_15_NBIT_XI … #define BNX2_RPM_RC_VALUE_MASK_15 … #define BNX2_RPM_RC_VALUE_MASK_15_VALUE … #define BNX2_RPM_RC_VALUE_MASK_15_MASK … #define BNX2_RPM_RC_CONFIG … #define BNX2_RPM_RC_CONFIG_RULE_ENABLE … #define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI … #define BNX2_RPM_RC_CONFIG_DEF_CLASS … #define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE … #define BNX2_RPM_DEBUG0 … #define BNX2_RPM_DEBUG0_FM_BCNT … #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD … #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD … #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD … #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD … #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT … #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR … #define BNX2_RPM_DEBUG0_LLC_SNAP … #define BNX2_RPM_DEBUG0_FM_STARTED … #define BNX2_RPM_DEBUG0_DONE … #define BNX2_RPM_DEBUG0_WAIT_4_DONE … #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM … #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM … #define BNX2_RPM_DEBUG0_IGNORE_VLAN … #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE … #define BNX2_RPM_DEBUG1 … #define BNX2_RPM_DEBUG1_FSM_CUR_ST … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT … #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT … #define BNX2_RPM_DEBUG1_HDR_BCNT … #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D … #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 … #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 … #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD … #define BNX2_RPM_DEBUG2 … #define BNX2_RPM_DEBUG2_CMD_HIT_VEC … #define BNX2_RPM_DEBUG2_IP_BCNT … #define BNX2_RPM_DEBUG2_THIS_CMD_M4 … #define BNX2_RPM_DEBUG2_THIS_CMD_M3 … #define BNX2_RPM_DEBUG2_THIS_CMD_M2 … #define BNX2_RPM_DEBUG2_THIS_CMD_M1 … #define BNX2_RPM_DEBUG2_IPIPE_EMPTY … #define BNX2_RPM_DEBUG2_FM_DISCARD … #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 … #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 … #define BNX2_RPM_DEBUG3 … #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR … #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT … #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT … #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT … #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ … #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ … #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL … #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP … #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT … #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL … #define BNX2_RPM_DEBUG3_DROP_NXT_VLD … #define BNX2_RPM_DEBUG3_DROP_NXT … #define BNX2_RPM_DEBUG3_FTQ_FSM … #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE … #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK … #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE … #define BNX2_RPM_DEBUG3_MBWRITE_FSM … #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF … #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF … #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA … #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA … #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF … #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK … #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD … #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE … #define BNX2_RPM_DEBUG3_MBFREE_FSM … #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE … #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK … #define BNX2_RPM_DEBUG3_MBALLOC_FSM … #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF … #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF … #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR … #define BNX2_RPM_DEBUG4 … #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER … #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE … #define BNX2_RPM_DEBUG4_MBWRITE_FSM … #define BNX2_RPM_DEBUG4_DFIFO_EMPTY … #define BNX2_RPM_DEBUG5 … #define BNX2_RPM_DEBUG5_RDROP_WPTR … #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR … #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR … #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR … #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY … #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY … #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR … #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT … #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD … #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL … #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY … #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY … #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY … #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY … #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T … #define BNX2_RPM_DEBUG5_HOLDREG_RD … #define BNX2_RPM_DEBUG6 … #define BNX2_RPM_DEBUG6_ACPI_VEC … #define BNX2_RPM_DEBUG6_VEC … #define BNX2_RPM_DEBUG7 … #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC … #define BNX2_RPM_DEBUG8 … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR … #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF … #define BNX2_RPM_DEBUG8_COMPARE_AT_W0 … #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA … #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT … #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 … #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 … #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES … #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES … #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES … #define BNX2_RPM_DEBUG8_EOF_DET … #define BNX2_RPM_DEBUG8_SOF_DET … #define BNX2_RPM_DEBUG8_WAIT_4_SOF … #define BNX2_RPM_DEBUG8_ALL_DONE … #define BNX2_RPM_DEBUG8_THBUF_ADDR … #define BNX2_RPM_DEBUG8_BYTE_CTR … #define BNX2_RPM_DEBUG9 … #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT … #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY … #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT … #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED … #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED … #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT … #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN … #define BNX2_RPM_DEBUG9_BEMEM_R_XI … #define BNX2_RPM_DEBUG9_EO_XI … #define BNX2_RPM_DEBUG9_AEOF_DE_XI … #define BNX2_RPM_DEBUG9_SO_XI … #define BNX2_RPM_DEBUG9_WD64_CT_XI … #define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI … #define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI … #define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI … #define BNX2_RPM_DEBUG9_DATA_IN_VL_XI … #define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI … #define BNX2_RPM_ACPI_DBG_BUF_W00 … #define BNX2_RPM_ACPI_DBG_BUF_W01 … #define BNX2_RPM_ACPI_DBG_BUF_W02 … #define BNX2_RPM_ACPI_DBG_BUF_W03 … #define BNX2_RPM_ACPI_DBG_BUF_W10 … #define BNX2_RPM_ACPI_DBG_BUF_W11 … #define BNX2_RPM_ACPI_DBG_BUF_W12 … #define BNX2_RPM_ACPI_DBG_BUF_W13 … #define BNX2_RPM_ACPI_DBG_BUF_W20 … #define BNX2_RPM_ACPI_DBG_BUF_W21 … #define BNX2_RPM_ACPI_DBG_BUF_W22 … #define BNX2_RPM_ACPI_DBG_BUF_W23 … #define BNX2_RPM_ACPI_DBG_BUF_W30 … #define BNX2_RPM_ACPI_DBG_BUF_W31 … #define BNX2_RPM_ACPI_DBG_BUF_W32 … #define BNX2_RPM_ACPI_DBG_BUF_W33 … #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL … #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS … #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD … #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE … #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT … #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR … #define BNX2_RPM_ACPI_PATTERN_CTRL … #define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID … #define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR … #define BNX2_RPM_ACPI_PATTERN_CTRL_WR … #define BNX2_RPM_ACPI_DATA … #define BNX2_RPM_ACPI_DATA_PATTERN_BE … #define BNX2_RPM_ACPI_PATTERN_LEN0 … #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3 … #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2 … #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1 … #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0 … #define BNX2_RPM_ACPI_PATTERN_LEN1 … #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7 … #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6 … #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5 … #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4 … #define BNX2_RPM_ACPI_PATTERN_CRC0 … #define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0 … #define BNX2_RPM_ACPI_PATTERN_CRC1 … #define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1 … #define BNX2_RPM_ACPI_PATTERN_CRC2 … #define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2 … #define BNX2_RPM_ACPI_PATTERN_CRC3 … #define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3 … #define BNX2_RPM_ACPI_PATTERN_CRC4 … #define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4 … #define BNX2_RPM_ACPI_PATTERN_CRC5 … #define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5 … #define BNX2_RPM_ACPI_PATTERN_CRC6 … #define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6 … #define BNX2_RPM_ACPI_PATTERN_CRC7 … #define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7 … /* * rlup_reg definition * offset: 0x2000 */ #define BNX2_RLUP_RSS_CONFIG … #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI … #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI … #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI … #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI … #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI … #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI … #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI … #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI … #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI … #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI … #define BNX2_RLUP_RSS_COMMAND … #define BNX2_RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR … #define BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK … #define BNX2_RLUP_RSS_COMMAND_WRITE … #define BNX2_RLUP_RSS_COMMAND_READ … #define BNX2_RLUP_RSS_COMMAND_HASH_MASK … #define BNX2_RLUP_RSS_DATA … /* * rbuf_reg definition * offset: 0x200000 */ #define BNX2_RBUF_COMMAND … #define BNX2_RBUF_COMMAND_ENABLED … #define BNX2_RBUF_COMMAND_FREE_INIT … #define BNX2_RBUF_COMMAND_RAM_INIT … #define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL … #define BNX2_RBUF_COMMAND_OVER_FREE … #define BNX2_RBUF_COMMAND_ALLOC_REQ … #define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE … #define BNX2_RBUF_COMMAND_CU_ISOLATE_XI … #define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI … #define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI … #define BNX2_RBUF_STATUS1 … #define BNX2_RBUF_STATUS1_FREE_COUNT … #define BNX2_RBUF_STATUS2 … #define BNX2_RBUF_STATUS2_FREE_TAIL … #define BNX2_RBUF_STATUS2_FREE_HEAD … #define BNX2_RBUF_CONFIG … #define BNX2_RBUF_CONFIG_XOFF_TRIP … #define BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu) … #define BNX2_RBUF_CONFIG_XON_TRIP … #define BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu) … #define BNX2_RBUF_CONFIG_VAL(mtu) … #define BNX2_RBUF_FW_BUF_ALLOC … #define BNX2_RBUF_FW_BUF_ALLOC_VALUE … #define BNX2_RBUF_FW_BUF_ALLOC_TYPE … #define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ … #define BNX2_RBUF_FW_BUF_FREE … #define BNX2_RBUF_FW_BUF_FREE_COUNT … #define BNX2_RBUF_FW_BUF_FREE_TAIL … #define BNX2_RBUF_FW_BUF_FREE_HEAD … #define BNX2_RBUF_FW_BUF_FREE_TYPE … #define BNX2_RBUF_FW_BUF_FREE_FREE_REQ … #define BNX2_RBUF_FW_BUF_SEL … #define BNX2_RBUF_FW_BUF_SEL_COUNT … #define BNX2_RBUF_FW_BUF_SEL_TAIL … #define BNX2_RBUF_FW_BUF_SEL_HEAD … #define BNX2_RBUF_FW_BUF_SEL_SEL_REQ … #define BNX2_RBUF_CONFIG2 … #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP … #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu) … #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP … #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu) … #define BNX2_RBUF_CONFIG2_VAL(mtu) … #define BNX2_RBUF_CONFIG3 … #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP … #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu) … #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP … #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu) … #define BNX2_RBUF_CONFIG3_VAL(mtu) … #define BNX2_RBUF_PKT_DATA … #define BNX2_RBUF_CLIST_DATA … #define BNX2_RBUF_BUF_DATA … /* * rv2p_reg definition * offset: 0x2800 */ #define BNX2_RV2P_COMMAND … #define BNX2_RV2P_COMMAND_ENABLED … #define BNX2_RV2P_COMMAND_PROC1_INTRPT … #define BNX2_RV2P_COMMAND_PROC2_INTRPT … #define BNX2_RV2P_COMMAND_ABORT0 … #define BNX2_RV2P_COMMAND_ABORT1 … #define BNX2_RV2P_COMMAND_ABORT2 … #define BNX2_RV2P_COMMAND_ABORT3 … #define BNX2_RV2P_COMMAND_ABORT4 … #define BNX2_RV2P_COMMAND_ABORT5 … #define BNX2_RV2P_COMMAND_PROC1_RESET … #define BNX2_RV2P_COMMAND_PROC2_RESET … #define BNX2_RV2P_COMMAND_CTXIF_RESET … #define BNX2_RV2P_STATUS … #define BNX2_RV2P_STATUS_ALWAYS_0 … #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT … #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT … #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT … #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT … #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT … #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT … #define BNX2_RV2P_CONFIG … #define BNX2_RV2P_CONFIG_STALL_PROC1 … #define BNX2_RV2P_CONFIG_STALL_PROC2 … #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 … #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 … #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 … #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 … #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 … #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 … #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 … #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 … #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 … #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 … #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 … #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 … #define BNX2_RV2P_CONFIG_PAGE_SIZE … #define BNX2_RV2P_CONFIG_PAGE_SIZE_256 … #define BNX2_RV2P_CONFIG_PAGE_SIZE_512 … #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K … #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K … #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K … #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K … #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K … #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K … #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K … #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K … #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K … #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K … #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M … #define BNX2_RV2P_GEN_BFR_ADDR_0 … #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE … #define BNX2_RV2P_GEN_BFR_ADDR_1 … #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE … #define BNX2_RV2P_GEN_BFR_ADDR_2 … #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE … #define BNX2_RV2P_GEN_BFR_ADDR_3 … #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE … #define BNX2_RV2P_INSTR_HIGH … #define BNX2_RV2P_INSTR_HIGH_HIGH … #define BNX2_RV2P_INSTR_LOW … #define BNX2_RV2P_INSTR_LOW_LOW … #define BNX2_RV2P_PROC1_ADDR_CMD … #define BNX2_RV2P_PROC1_ADDR_CMD_ADD … #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR … #define BNX2_RV2P_PROC2_ADDR_CMD … #define BNX2_RV2P_PROC2_ADDR_CMD_ADD … #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR … #define BNX2_RV2P_PROC1_GRC_DEBUG … #define BNX2_RV2P_PROC2_GRC_DEBUG … #define BNX2_RV2P_GRC_PROC_DEBUG … #define BNX2_RV2P_DEBUG_VECT_PEEK … #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE … #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN … #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL … #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE … #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN … #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL … #define BNX2_RV2P_MPFE_PFE_CTL … #define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15 … #define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT … #define BNX2_RV2P_MPFE_PFE_CTL_OFFSET … #define BNX2_RV2P_RV2PPQ … #define BNX2_RV2P_PFTQ_CMD … #define BNX2_RV2P_PFTQ_CMD_OFFSET … #define BNX2_RV2P_PFTQ_CMD_WR_TOP … #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 … #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 … #define BNX2_RV2P_PFTQ_CMD_SFT_RESET … #define BNX2_RV2P_PFTQ_CMD_RD_DATA … #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN … #define BNX2_RV2P_PFTQ_CMD_ADD_DATA … #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR … #define BNX2_RV2P_PFTQ_CMD_POP … #define BNX2_RV2P_PFTQ_CMD_BUSY … #define BNX2_RV2P_PFTQ_CTL … #define BNX2_RV2P_PFTQ_CTL_INTERVENE … #define BNX2_RV2P_PFTQ_CTL_OVERFLOW … #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE … #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH … #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH … #define BNX2_RV2P_RV2PTQ … #define BNX2_RV2P_TFTQ_CMD … #define BNX2_RV2P_TFTQ_CMD_OFFSET … #define BNX2_RV2P_TFTQ_CMD_WR_TOP … #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 … #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 … #define BNX2_RV2P_TFTQ_CMD_SFT_RESET … #define BNX2_RV2P_TFTQ_CMD_RD_DATA … #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN … #define BNX2_RV2P_TFTQ_CMD_ADD_DATA … #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR … #define BNX2_RV2P_TFTQ_CMD_POP … #define BNX2_RV2P_TFTQ_CMD_BUSY … #define BNX2_RV2P_TFTQ_CTL … #define BNX2_RV2P_TFTQ_CTL_INTERVENE … #define BNX2_RV2P_TFTQ_CTL_OVERFLOW … #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE … #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH … #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH … #define BNX2_RV2P_RV2PMQ … #define BNX2_RV2P_MFTQ_CMD … #define BNX2_RV2P_MFTQ_CMD_OFFSET … #define BNX2_RV2P_MFTQ_CMD_WR_TOP … #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 … #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 … #define BNX2_RV2P_MFTQ_CMD_SFT_RESET … #define BNX2_RV2P_MFTQ_CMD_RD_DATA … #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN … #define BNX2_RV2P_MFTQ_CMD_ADD_DATA … #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR … #define BNX2_RV2P_MFTQ_CMD_POP … #define BNX2_RV2P_MFTQ_CMD_BUSY … #define BNX2_RV2P_MFTQ_CTL … #define BNX2_RV2P_MFTQ_CTL_INTERVENE … #define BNX2_RV2P_MFTQ_CTL_OVERFLOW … #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE … #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH … #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH … /* * mq_reg definition * offset: 0x3c00 */ #define BNX2_MQ_COMMAND … #define BNX2_MQ_COMMAND_ENABLED … #define BNX2_MQ_COMMAND_INIT … #define BNX2_MQ_COMMAND_OVERFLOW … #define BNX2_MQ_COMMAND_WR_ERROR … #define BNX2_MQ_COMMAND_RD_ERROR … #define BNX2_MQ_COMMAND_IDB_CFG_ERROR … #define BNX2_MQ_COMMAND_IDB_OVERFLOW … #define BNX2_MQ_COMMAND_NO_BIN_ERROR … #define BNX2_MQ_COMMAND_NO_MAP_ERROR … #define BNX2_MQ_STATUS … #define BNX2_MQ_STATUS_CTX_ACCESS_STAT … #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT … #define BNX2_MQ_STATUS_PCI_STALL_STAT … #define BNX2_MQ_STATUS_IDB_OFLOW_STAT … #define BNX2_MQ_CONFIG … #define BNX2_MQ_CONFIG_TX_HIGH_PRI … #define BNX2_MQ_CONFIG_HALT_DIS … #define BNX2_MQ_CONFIG_BIN_MQ_MODE … #define BNX2_MQ_CONFIG_DIS_IDB_DROP … #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE … #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 … #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 … #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K … #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K … #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K … #define BNX2_MQ_CONFIG_MAX_DEPTH … #define BNX2_MQ_CONFIG_CUR_DEPTH … #define BNX2_MQ_ENQUEUE1 … #define BNX2_MQ_ENQUEUE1_OFFSET … #define BNX2_MQ_ENQUEUE1_CID … #define BNX2_MQ_ENQUEUE1_BYTE_MASK … #define BNX2_MQ_ENQUEUE1_KNL_MODE … #define BNX2_MQ_ENQUEUE2 … #define BNX2_MQ_BAD_WR_ADDR … #define BNX2_MQ_BAD_RD_ADDR … #define BNX2_MQ_KNL_BYP_WIND_START … #define BNX2_MQ_KNL_BYP_WIND_START_VALUE … #define BNX2_MQ_KNL_WIND_END … #define BNX2_MQ_KNL_WIND_END_VALUE … #define BNX2_MQ_KNL_WRITE_MASK1 … #define BNX2_MQ_KNL_TX_MASK1 … #define BNX2_MQ_KNL_CMD_MASK1 … #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 … #define BNX2_MQ_KNL_RX_V2P_MASK1 … #define BNX2_MQ_KNL_WRITE_MASK2 … #define BNX2_MQ_KNL_TX_MASK2 … #define BNX2_MQ_KNL_CMD_MASK2 … #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 … #define BNX2_MQ_KNL_RX_V2P_MASK2 … #define BNX2_MQ_KNL_BYP_WRITE_MASK1 … #define BNX2_MQ_KNL_BYP_TX_MASK1 … #define BNX2_MQ_KNL_BYP_CMD_MASK1 … #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 … #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 … #define BNX2_MQ_KNL_BYP_WRITE_MASK2 … #define BNX2_MQ_KNL_BYP_TX_MASK2 … #define BNX2_MQ_KNL_BYP_CMD_MASK2 … #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 … #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 … #define BNX2_MQ_MEM_WR_ADDR … #define BNX2_MQ_MEM_WR_ADDR_VALUE … #define BNX2_MQ_MEM_WR_DATA0 … #define BNX2_MQ_MEM_WR_DATA0_VALUE … #define BNX2_MQ_MEM_WR_DATA1 … #define BNX2_MQ_MEM_WR_DATA1_VALUE … #define BNX2_MQ_MEM_WR_DATA2 … #define BNX2_MQ_MEM_WR_DATA2_VALUE … #define BNX2_MQ_MEM_WR_DATA2_VALUE_XI … #define BNX2_MQ_MEM_RD_ADDR … #define BNX2_MQ_MEM_RD_ADDR_VALUE … #define BNX2_MQ_MEM_RD_DATA0 … #define BNX2_MQ_MEM_RD_DATA0_VALUE … #define BNX2_MQ_MEM_RD_DATA1 … #define BNX2_MQ_MEM_RD_DATA1_VALUE … #define BNX2_MQ_MEM_RD_DATA2 … #define BNX2_MQ_MEM_RD_DATA2_VALUE … #define BNX2_MQ_MEM_RD_DATA2_VALUE_XI … #define BNX2_MQ_MAP_L2_3 … #define BNX2_MQ_MAP_L2_3_MQ_OFFSET … #define BNX2_MQ_MAP_L2_3_SZ … #define BNX2_MQ_MAP_L2_3_CTX_OFFSET … #define BNX2_MQ_MAP_L2_3_BIN_OFFSET … #define BNX2_MQ_MAP_L2_3_ARM … #define BNX2_MQ_MAP_L2_3_ENA … #define BNX2_MQ_MAP_L2_3_DEFAULT … #define BNX2_MQ_MAP_L2_5 … #define BNX2_MQ_MAP_L2_5_ARM … /* * tsch_reg definition * offset: 0x4c00 */ #define BNX2_TSCH_TSS_CFG … #define BNX2_TSCH_TSS_CFG_TSS_START_CID … #define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON … /* * tbdr_reg definition * offset: 0x5000 */ #define BNX2_TBDR_COMMAND … #define BNX2_TBDR_COMMAND_ENABLE … #define BNX2_TBDR_COMMAND_SOFT_RST … #define BNX2_TBDR_COMMAND_MSTR_ABORT … #define BNX2_TBDR_STATUS … #define BNX2_TBDR_STATUS_DMA_WAIT … #define BNX2_TBDR_STATUS_FTQ_WAIT … #define BNX2_TBDR_STATUS_FIFO_OVERFLOW … #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW … #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR … #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT … #define BNX2_TBDR_STATUS_BURST_CNT … #define BNX2_TBDR_CONFIG … #define BNX2_TBDR_CONFIG_MAX_BDS … #define BNX2_TBDR_CONFIG_SWAP_MODE … #define BNX2_TBDR_CONFIG_PRIORITY … #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS … #define BNX2_TBDR_CONFIG_PAGE_SIZE … #define BNX2_TBDR_CONFIG_PAGE_SIZE_256 … #define BNX2_TBDR_CONFIG_PAGE_SIZE_512 … #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K … #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K … #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K … #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K … #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K … #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K … #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K … #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K … #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K … #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K … #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M … #define BNX2_TBDR_DEBUG_VECT_PEEK … #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE … #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN … #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL … #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE … #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN … #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL … #define BNX2_TBDR_CKSUM_ERROR_STATUS … #define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED … #define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED … #define BNX2_TBDR_TBDRQ … #define BNX2_TBDR_FTQ_CMD … #define BNX2_TBDR_FTQ_CMD_OFFSET … #define BNX2_TBDR_FTQ_CMD_WR_TOP … #define BNX2_TBDR_FTQ_CMD_WR_TOP_0 … #define BNX2_TBDR_FTQ_CMD_WR_TOP_1 … #define BNX2_TBDR_FTQ_CMD_SFT_RESET … #define BNX2_TBDR_FTQ_CMD_RD_DATA … #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN … #define BNX2_TBDR_FTQ_CMD_ADD_DATA … #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR … #define BNX2_TBDR_FTQ_CMD_POP … #define BNX2_TBDR_FTQ_CMD_BUSY … #define BNX2_TBDR_FTQ_CTL … #define BNX2_TBDR_FTQ_CTL_INTERVENE … #define BNX2_TBDR_FTQ_CTL_OVERFLOW … #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE … #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH … #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH … /* * tbdc definition * offset: 0x5400 */ #define BNX2_TBDC_COMMAND … #define BNX2_TBDC_COMMAND_CMD_ENABLED … #define BNX2_TBDC_COMMAND_CMD_FLUSH … #define BNX2_TBDC_COMMAND_CMD_SOFT_RST … #define BNX2_TBDC_COMMAND_CMD_REG_ARB … #define BNX2_TBDC_COMMAND_WRCHK_RANGE_ERROR … #define BNX2_TBDC_COMMAND_WRCHK_ALL_ONES_ERROR … #define BNX2_TBDC_COMMAND_WRCHK_ALL_ZEROS_ERROR … #define BNX2_TBDC_COMMAND_WRCHK_ANY_ONES_ERROR … #define BNX2_TBDC_COMMAND_WRCHK_ANY_ZEROS_ERROR … #define BNX2_TBDC_STATUS … #define BNX2_TBDC_STATUS_FREE_CNT … #define BNX2_TBDC_BD_ADDR … #define BNX2_TBDC_BIDX … #define BNX2_TBDC_BDIDX_BDIDX … #define BNX2_TBDC_BDIDX_CMD … #define BNX2_TBDC_CID … #define BNX2_TBDC_CAM_OPCODE … #define BNX2_TBDC_CAM_OPCODE_OPCODE … #define BNX2_TBDC_CAM_OPCODE_OPCODE_SEARCH … #define BNX2_TBDC_CAM_OPCODE_OPCODE_CACHE_WRITE … #define BNX2_TBDC_CAM_OPCODE_OPCODE_INVALIDATE … #define BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_WRITE … #define BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ … #define BNX2_TBDC_CAM_OPCODE_OPCODE_RAM_WRITE … #define BNX2_TBDC_CAM_OPCODE_OPCODE_RAM_READ … #define BNX2_TBDC_CAM_OPCODE_SMASK_BDIDX … #define BNX2_TBDC_CAM_OPCODE_SMASK_CID … #define BNX2_TBDC_CAM_OPCODE_SMASK_CMD … #define BNX2_TBDC_CAM_OPCODE_WMT_FAILED … #define BNX2_TBDC_CAM_OPCODE_CAM_VALIDS … /* * tdma_reg definition * offset: 0x5c00 */ #define BNX2_TDMA_COMMAND … #define BNX2_TDMA_COMMAND_ENABLED … #define BNX2_TDMA_COMMAND_MASTER_ABORT … #define BNX2_TDMA_COMMAND_CS16_ERR … #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT … #define BNX2_TDMA_COMMAND_MASK_CS1 … #define BNX2_TDMA_COMMAND_MASK_CS2 … #define BNX2_TDMA_COMMAND_MASK_CS3 … #define BNX2_TDMA_COMMAND_MASK_CS4 … #define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR … #define BNX2_TDMA_COMMAND_OFIFO_CLR … #define BNX2_TDMA_COMMAND_IFIFO_CLR … #define BNX2_TDMA_STATUS … #define BNX2_TDMA_STATUS_DMA_WAIT … #define BNX2_TDMA_STATUS_PAYLOAD_WAIT … #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT … #define BNX2_TDMA_STATUS_LOCK_WAIT … #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT … #define BNX2_TDMA_STATUS_BURST_CNT … #define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH … #define BNX2_TDMA_STATUS_OFIFO_OVERFLOW … #define BNX2_TDMA_STATUS_IFIFO_OVERFLOW … #define BNX2_TDMA_CONFIG … #define BNX2_TDMA_CONFIG_ONE_DMA … #define BNX2_TDMA_CONFIG_ONE_RECORD … #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN … #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0 … #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1 … #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2 … #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3 … #define BNX2_TDMA_CONFIG_LIMIT_SZ … #define BNX2_TDMA_CONFIG_LIMIT_SZ_64 … #define BNX2_TDMA_CONFIG_LIMIT_SZ_128 … #define BNX2_TDMA_CONFIG_LIMIT_SZ_256 … #define BNX2_TDMA_CONFIG_LIMIT_SZ_512 … #define BNX2_TDMA_CONFIG_LINE_SZ … #define BNX2_TDMA_CONFIG_LINE_SZ_64 … #define BNX2_TDMA_CONFIG_LINE_SZ_128 … #define BNX2_TDMA_CONFIG_LINE_SZ_256 … #define BNX2_TDMA_CONFIG_LINE_SZ_512 … #define BNX2_TDMA_CONFIG_ALIGN_ENA … #define BNX2_TDMA_CONFIG_CHK_L2_BD … #define BNX2_TDMA_CONFIG_CMPL_ENTRY … #define BNX2_TDMA_CONFIG_OFIFO_CMP … #define BNX2_TDMA_CONFIG_OFIFO_CMP_3 … #define BNX2_TDMA_CONFIG_OFIFO_CMP_2 … #define BNX2_TDMA_CONFIG_FIFO_CMP … #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI … #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI … #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI … #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI … #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI … #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI … #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI … #define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI … #define BNX2_TDMA_CONFIG_BYTES_OST_XI … #define BNX2_TDMA_CONFIG_BYTES_OST_512_XI … #define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI … #define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI … #define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI … #define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI … #define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI … #define BNX2_TDMA_CONFIG_HC_BYPASS_XI … #define BNX2_TDMA_CONFIG_LCL_MRRS_XI … #define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI … #define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI … #define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI … #define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI … #define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI … #define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI … #define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI … #define BNX2_TDMA_PAYLOAD_PROD … #define BNX2_TDMA_PAYLOAD_PROD_VALUE … #define BNX2_TDMA_DBG_WATCHDOG … #define BNX2_TDMA_DBG_TRIGGER … #define BNX2_TDMA_DMAD_FSM … #define BNX2_TDMA_DMAD_FSM_BD_INVLD … #define BNX2_TDMA_DMAD_FSM_PUSH … #define BNX2_TDMA_DMAD_FSM_ARB_TBDC … #define BNX2_TDMA_DMAD_FSM_ARB_CTX … #define BNX2_TDMA_DMAD_FSM_DR_INTF … #define BNX2_TDMA_DMAD_FSM_DMAD … #define BNX2_TDMA_DMAD_FSM_BD … #define BNX2_TDMA_DMAD_STATUS … #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY … #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY … #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY … #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM … #define BNX2_TDMA_DR_INTF_FSM … #define BNX2_TDMA_DR_INTF_FSM_L2_COMP … #define BNX2_TDMA_DR_INTF_FSM_TPATQ … #define BNX2_TDMA_DR_INTF_FSM_TPBUF … #define BNX2_TDMA_DR_INTF_FSM_DR_BUF … #define BNX2_TDMA_DR_INTF_FSM_DMAD … #define BNX2_TDMA_DR_INTF_STATUS … #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE … #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL … #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR … #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR … #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT … #define BNX2_TDMA_PUSH_FSM … #define BNX2_TDMA_BD_IF_DEBUG … #define BNX2_TDMA_DMAD_IF_DEBUG … #define BNX2_TDMA_CTX_IF_DEBUG … #define BNX2_TDMA_TPBUF_IF_DEBUG … #define BNX2_TDMA_DR_IF_DEBUG … #define BNX2_TDMA_TPATQ_IF_DEBUG … #define BNX2_TDMA_TDMA_ILOCK_CKSUM … #define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED … #define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED … #define BNX2_TDMA_TDMA_PCIE_CKSUM … #define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED … #define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED … #define BNX2_TDMA_TDMAQ … #define BNX2_TDMA_FTQ_CMD … #define BNX2_TDMA_FTQ_CMD_OFFSET … #define BNX2_TDMA_FTQ_CMD_WR_TOP … #define BNX2_TDMA_FTQ_CMD_WR_TOP_0 … #define BNX2_TDMA_FTQ_CMD_WR_TOP_1 … #define BNX2_TDMA_FTQ_CMD_SFT_RESET … #define BNX2_TDMA_FTQ_CMD_RD_DATA … #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN … #define BNX2_TDMA_FTQ_CMD_ADD_DATA … #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR … #define BNX2_TDMA_FTQ_CMD_POP … #define BNX2_TDMA_FTQ_CMD_BUSY … #define BNX2_TDMA_FTQ_CTL … #define BNX2_TDMA_FTQ_CTL_INTERVENE … #define BNX2_TDMA_FTQ_CTL_OVERFLOW … #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE … #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH … #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH … /* * hc_reg definition * offset: 0x6800 */ #define BNX2_HC_COMMAND … #define BNX2_HC_COMMAND_ENABLE … #define BNX2_HC_COMMAND_SKIP_ABORT … #define BNX2_HC_COMMAND_COAL_NOW … #define BNX2_HC_COMMAND_COAL_NOW_WO_INT … #define BNX2_HC_COMMAND_STATS_NOW … #define BNX2_HC_COMMAND_FORCE_INT … #define BNX2_HC_COMMAND_FORCE_INT_NULL … #define BNX2_HC_COMMAND_FORCE_INT_HIGH … #define BNX2_HC_COMMAND_FORCE_INT_LOW … #define BNX2_HC_COMMAND_FORCE_INT_FREE … #define BNX2_HC_COMMAND_CLR_STAT_NOW … #define BNX2_HC_COMMAND_MAIN_PWR_INT … #define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT … #define BNX2_HC_STATUS … #define BNX2_HC_STATUS_MASTER_ABORT … #define BNX2_HC_STATUS_PARITY_ERROR_STATE … #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT … #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT … #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT … #define BNX2_HC_STATUS_NUM_INT_GEN_STAT … #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT … #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT … #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT … #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT … #define BNX2_HC_CONFIG … #define BNX2_HC_CONFIG_COLLECT_STATS … #define BNX2_HC_CONFIG_RX_TMR_MODE … #define BNX2_HC_CONFIG_TX_TMR_MODE … #define BNX2_HC_CONFIG_COM_TMR_MODE … #define BNX2_HC_CONFIG_CMD_TMR_MODE … #define BNX2_HC_CONFIG_STATISTIC_PRIORITY … #define BNX2_HC_CONFIG_STATUS_PRIORITY … #define BNX2_HC_CONFIG_STAT_MEM_ADDR … #define BNX2_HC_CONFIG_PER_MODE … #define BNX2_HC_CONFIG_ONE_SHOT … #define BNX2_HC_CONFIG_USE_INT_PARAM … #define BNX2_HC_CONFIG_SET_MASK_AT_RD … #define BNX2_HC_CONFIG_PER_COLLECT_LIMIT … #define BNX2_HC_CONFIG_SB_ADDR_INC … #define BNX2_HC_CONFIG_SB_ADDR_INC_64B … #define BNX2_HC_CONFIG_SB_ADDR_INC_128B … #define BNX2_HC_CONFIG_SB_ADDR_INC_256B … #define BNX2_HC_CONFIG_SB_ADDR_INC_512B … #define BNX2_HC_CONFIG_SB_ADDR_INC_1024B … #define BNX2_HC_CONFIG_SB_ADDR_INC_2048B … #define BNX2_HC_CONFIG_SB_ADDR_INC_4096B … #define BNX2_HC_CONFIG_SB_ADDR_INC_8192B … #define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR … #define BNX2_HC_CONFIG_UNMASK_ALL … #define BNX2_HC_CONFIG_TX_SEL … #define BNX2_HC_ATTN_BITS_ENABLE … #define BNX2_HC_STATUS_ADDR_L … #define BNX2_HC_STATUS_ADDR_H … #define BNX2_HC_STATISTICS_ADDR_L … #define BNX2_HC_STATISTICS_ADDR_H … #define BNX2_HC_TX_QUICK_CONS_TRIP … #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE … #define BNX2_HC_TX_QUICK_CONS_TRIP_INT … #define BNX2_HC_COMP_PROD_TRIP … #define BNX2_HC_COMP_PROD_TRIP_VALUE … #define BNX2_HC_COMP_PROD_TRIP_INT … #define BNX2_HC_RX_QUICK_CONS_TRIP … #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE … #define BNX2_HC_RX_QUICK_CONS_TRIP_INT … #define BNX2_HC_RX_TICKS … #define BNX2_HC_RX_TICKS_VALUE … #define BNX2_HC_RX_TICKS_INT … #define BNX2_HC_TX_TICKS … #define BNX2_HC_TX_TICKS_VALUE … #define BNX2_HC_TX_TICKS_INT … #define BNX2_HC_COM_TICKS … #define BNX2_HC_COM_TICKS_VALUE … #define BNX2_HC_COM_TICKS_INT … #define BNX2_HC_CMD_TICKS … #define BNX2_HC_CMD_TICKS_VALUE … #define BNX2_HC_CMD_TICKS_INT … #define BNX2_HC_PERIODIC_TICKS … #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS … #define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS … #define BNX2_HC_STAT_COLLECT_TICKS … #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS … #define BNX2_HC_STATS_TICKS … #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS … #define BNX2_HC_STATS_INTERRUPT_STATUS … #define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS … #define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS … #define BNX2_HC_STAT_MEM_DATA … #define BNX2_HC_STAT_GEN_SEL_0 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI … #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI … #define BNX2_HC_STAT_GEN_SEL_1 … #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 … #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 … #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 … #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 … #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI … #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI … #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI … #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI … #define BNX2_HC_STAT_GEN_SEL_2 … #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 … #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 … #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 … #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 … #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI … #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI … #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI … #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI … #define BNX2_HC_STAT_GEN_SEL_3 … #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 … #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 … #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 … #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 … #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI … #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI … #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI … #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI … #define BNX2_HC_STAT_GEN_STAT0 … #define BNX2_HC_STAT_GEN_STAT1 … #define BNX2_HC_STAT_GEN_STAT2 … #define BNX2_HC_STAT_GEN_STAT3 … #define BNX2_HC_STAT_GEN_STAT4 … #define BNX2_HC_STAT_GEN_STAT5 … #define BNX2_HC_STAT_GEN_STAT6 … #define BNX2_HC_STAT_GEN_STAT7 … #define BNX2_HC_STAT_GEN_STAT8 … #define BNX2_HC_STAT_GEN_STAT9 … #define BNX2_HC_STAT_GEN_STAT10 … #define BNX2_HC_STAT_GEN_STAT11 … #define BNX2_HC_STAT_GEN_STAT12 … #define BNX2_HC_STAT_GEN_STAT13 … #define BNX2_HC_STAT_GEN_STAT14 … #define BNX2_HC_STAT_GEN_STAT15 … #define BNX2_HC_STAT_GEN_STAT_AC0 … #define BNX2_HC_STAT_GEN_STAT_AC1 … #define BNX2_HC_STAT_GEN_STAT_AC2 … #define BNX2_HC_STAT_GEN_STAT_AC3 … #define BNX2_HC_STAT_GEN_STAT_AC4 … #define BNX2_HC_STAT_GEN_STAT_AC5 … #define BNX2_HC_STAT_GEN_STAT_AC6 … #define BNX2_HC_STAT_GEN_STAT_AC7 … #define BNX2_HC_STAT_GEN_STAT_AC8 … #define BNX2_HC_STAT_GEN_STAT_AC9 … #define BNX2_HC_STAT_GEN_STAT_AC10 … #define BNX2_HC_STAT_GEN_STAT_AC11 … #define BNX2_HC_STAT_GEN_STAT_AC12 … #define BNX2_HC_STAT_GEN_STAT_AC13 … #define BNX2_HC_STAT_GEN_STAT_AC14 … #define BNX2_HC_STAT_GEN_STAT_AC15 … #define BNX2_HC_STAT_GEN_STAT_AC … #define BNX2_HC_VIS … #define BNX2_HC_VIS_STAT_BUILD_STATE … #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE … #define BNX2_HC_VIS_STAT_BUILD_STATE_START … #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST … #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 … #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 … #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE … #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA … #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL … #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW … #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH … #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA … #define BNX2_HC_VIS_DMA_STAT_STATE … #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE … #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM … #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA … #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP … #define BNX2_HC_VIS_DMA_STAT_STATE_COMP … #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM … #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA … #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 … #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 … #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT … #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT … #define BNX2_HC_VIS_DMA_MSI_STATE … #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE … #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE … #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT … #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START … #define BNX2_HC_VIS_1 … #define BNX2_HC_VIS_1_HW_INTACK_STATE … #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE … #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT … #define BNX2_HC_VIS_1_SW_INTACK_STATE … #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE … #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT … #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE … #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE … #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT … #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE … #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE … #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT … #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE … #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE … #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA … #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE … #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN … #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT … #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE … #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN … #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT … #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE … #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL … #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR … #define BNX2_HC_VIS_1_INT_GEN_STATE … #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE … #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT … #define BNX2_HC_VIS_1_STAT_CHAN_ID … #define BNX2_HC_VIS_1_INT_B … #define BNX2_HC_DEBUG_VECT_PEEK … #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE … #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN … #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL … #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE … #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN … #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL … #define BNX2_HC_COALESCE_NOW … #define BNX2_HC_COALESCE_NOW_COAL_NOW … #define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT … #define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT … #define BNX2_HC_MSIX_BIT_VECTOR … #define BNX2_HC_MSIX_BIT_VECTOR_VAL … #define BNX2_HC_SB_CONFIG_1 … #define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE … #define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE … #define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE … #define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE … #define BNX2_HC_SB_CONFIG_1_PER_MODE … #define BNX2_HC_SB_CONFIG_1_ONE_SHOT … #define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM … #define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT … #define BNX2_HC_TX_QUICK_CONS_TRIP_1 … #define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE … #define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT … #define BNX2_HC_COMP_PROD_TRIP_1 … #define BNX2_HC_COMP_PROD_TRIP_1_VALUE … #define BNX2_HC_COMP_PROD_TRIP_1_INT … #define BNX2_HC_RX_QUICK_CONS_TRIP_1 … #define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE … #define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT … #define BNX2_HC_RX_TICKS_1 … #define BNX2_HC_RX_TICKS_1_VALUE … #define BNX2_HC_RX_TICKS_1_INT … #define BNX2_HC_TX_TICKS_1 … #define BNX2_HC_TX_TICKS_1_VALUE … #define BNX2_HC_TX_TICKS_1_INT … #define BNX2_HC_COM_TICKS_1 … #define BNX2_HC_COM_TICKS_1_VALUE … #define BNX2_HC_COM_TICKS_1_INT … #define BNX2_HC_CMD_TICKS_1 … #define BNX2_HC_CMD_TICKS_1_VALUE … #define BNX2_HC_CMD_TICKS_1_INT … #define BNX2_HC_PERIODIC_TICKS_1 … #define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS … #define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS … #define BNX2_HC_SB_CONFIG_2 … #define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE … #define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE … #define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE … #define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE … #define BNX2_HC_SB_CONFIG_2_PER_MODE … #define BNX2_HC_SB_CONFIG_2_ONE_SHOT … #define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM … #define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT … #define BNX2_HC_TX_QUICK_CONS_TRIP_2 … #define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE … #define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT … #define BNX2_HC_COMP_PROD_TRIP_2 … #define BNX2_HC_COMP_PROD_TRIP_2_VALUE … #define BNX2_HC_COMP_PROD_TRIP_2_INT … #define BNX2_HC_RX_QUICK_CONS_TRIP_2 … #define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE … #define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT … #define BNX2_HC_RX_TICKS_2 … #define BNX2_HC_RX_TICKS_2_VALUE … #define BNX2_HC_RX_TICKS_2_INT … #define BNX2_HC_TX_TICKS_2 … #define BNX2_HC_TX_TICKS_2_VALUE … #define BNX2_HC_TX_TICKS_2_INT … #define BNX2_HC_COM_TICKS_2 … #define BNX2_HC_COM_TICKS_2_VALUE … #define BNX2_HC_COM_TICKS_2_INT … #define BNX2_HC_CMD_TICKS_2 … #define BNX2_HC_CMD_TICKS_2_VALUE … #define BNX2_HC_CMD_TICKS_2_INT … #define BNX2_HC_PERIODIC_TICKS_2 … #define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS … #define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS … #define BNX2_HC_SB_CONFIG_3 … #define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE … #define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE … #define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE … #define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE … #define BNX2_HC_SB_CONFIG_3_PER_MODE … #define BNX2_HC_SB_CONFIG_3_ONE_SHOT … #define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM … #define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT … #define BNX2_HC_TX_QUICK_CONS_TRIP_3 … #define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE … #define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT … #define BNX2_HC_COMP_PROD_TRIP_3 … #define BNX2_HC_COMP_PROD_TRIP_3_VALUE … #define BNX2_HC_COMP_PROD_TRIP_3_INT … #define BNX2_HC_RX_QUICK_CONS_TRIP_3 … #define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE … #define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT … #define BNX2_HC_RX_TICKS_3 … #define BNX2_HC_RX_TICKS_3_VALUE … #define BNX2_HC_RX_TICKS_3_INT … #define BNX2_HC_TX_TICKS_3 … #define BNX2_HC_TX_TICKS_3_VALUE … #define BNX2_HC_TX_TICKS_3_INT … #define BNX2_HC_COM_TICKS_3 … #define BNX2_HC_COM_TICKS_3_VALUE … #define BNX2_HC_COM_TICKS_3_INT … #define BNX2_HC_CMD_TICKS_3 … #define BNX2_HC_CMD_TICKS_3_VALUE … #define BNX2_HC_CMD_TICKS_3_INT … #define BNX2_HC_PERIODIC_TICKS_3 … #define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS … #define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS … #define BNX2_HC_SB_CONFIG_4 … #define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE … #define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE … #define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE … #define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE … #define BNX2_HC_SB_CONFIG_4_PER_MODE … #define BNX2_HC_SB_CONFIG_4_ONE_SHOT … #define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM … #define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT … #define BNX2_HC_TX_QUICK_CONS_TRIP_4 … #define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE … #define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT … #define BNX2_HC_COMP_PROD_TRIP_4 … #define BNX2_HC_COMP_PROD_TRIP_4_VALUE … #define BNX2_HC_COMP_PROD_TRIP_4_INT … #define BNX2_HC_RX_QUICK_CONS_TRIP_4 … #define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE … #define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT … #define BNX2_HC_RX_TICKS_4 … #define BNX2_HC_RX_TICKS_4_VALUE … #define BNX2_HC_RX_TICKS_4_INT … #define BNX2_HC_TX_TICKS_4 … #define BNX2_HC_TX_TICKS_4_VALUE … #define BNX2_HC_TX_TICKS_4_INT … #define BNX2_HC_COM_TICKS_4 … #define BNX2_HC_COM_TICKS_4_VALUE … #define BNX2_HC_COM_TICKS_4_INT … #define BNX2_HC_CMD_TICKS_4 … #define BNX2_HC_CMD_TICKS_4_VALUE … #define BNX2_HC_CMD_TICKS_4_INT … #define BNX2_HC_PERIODIC_TICKS_4 … #define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS … #define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS … #define BNX2_HC_SB_CONFIG_5 … #define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE … #define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE … #define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE … #define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE … #define BNX2_HC_SB_CONFIG_5_PER_MODE … #define BNX2_HC_SB_CONFIG_5_ONE_SHOT … #define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM … #define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT … #define BNX2_HC_TX_QUICK_CONS_TRIP_5 … #define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE … #define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT … #define BNX2_HC_COMP_PROD_TRIP_5 … #define BNX2_HC_COMP_PROD_TRIP_5_VALUE … #define BNX2_HC_COMP_PROD_TRIP_5_INT … #define BNX2_HC_RX_QUICK_CONS_TRIP_5 … #define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE … #define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT … #define BNX2_HC_RX_TICKS_5 … #define BNX2_HC_RX_TICKS_5_VALUE … #define BNX2_HC_RX_TICKS_5_INT … #define BNX2_HC_TX_TICKS_5 … #define BNX2_HC_TX_TICKS_5_VALUE … #define BNX2_HC_TX_TICKS_5_INT … #define BNX2_HC_COM_TICKS_5 … #define BNX2_HC_COM_TICKS_5_VALUE … #define BNX2_HC_COM_TICKS_5_INT … #define BNX2_HC_CMD_TICKS_5 … #define BNX2_HC_CMD_TICKS_5_VALUE … #define BNX2_HC_CMD_TICKS_5_INT … #define BNX2_HC_PERIODIC_TICKS_5 … #define BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS … #define BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS … #define BNX2_HC_SB_CONFIG_6 … #define BNX2_HC_SB_CONFIG_6_RX_TMR_MODE … #define BNX2_HC_SB_CONFIG_6_TX_TMR_MODE … #define BNX2_HC_SB_CONFIG_6_COM_TMR_MODE … #define BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE … #define BNX2_HC_SB_CONFIG_6_PER_MODE … #define BNX2_HC_SB_CONFIG_6_ONE_SHOT … #define BNX2_HC_SB_CONFIG_6_USE_INT_PARAM … #define BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT … #define BNX2_HC_TX_QUICK_CONS_TRIP_6 … #define BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE … #define BNX2_HC_TX_QUICK_CONS_TRIP_6_INT … #define BNX2_HC_COMP_PROD_TRIP_6 … #define BNX2_HC_COMP_PROD_TRIP_6_VALUE … #define BNX2_HC_COMP_PROD_TRIP_6_INT … #define BNX2_HC_RX_QUICK_CONS_TRIP_6 … #define BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE … #define BNX2_HC_RX_QUICK_CONS_TRIP_6_INT … #define BNX2_HC_RX_TICKS_6 … #define BNX2_HC_RX_TICKS_6_VALUE … #define BNX2_HC_RX_TICKS_6_INT … #define BNX2_HC_TX_TICKS_6 … #define BNX2_HC_TX_TICKS_6_VALUE … #define BNX2_HC_TX_TICKS_6_INT … #define BNX2_HC_COM_TICKS_6 … #define BNX2_HC_COM_TICKS_6_VALUE … #define BNX2_HC_COM_TICKS_6_INT … #define BNX2_HC_CMD_TICKS_6 … #define BNX2_HC_CMD_TICKS_6_VALUE … #define BNX2_HC_CMD_TICKS_6_INT … #define BNX2_HC_PERIODIC_TICKS_6 … #define BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS … #define BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS … #define BNX2_HC_SB_CONFIG_7 … #define BNX2_HC_SB_CONFIG_7_RX_TMR_MODE … #define BNX2_HC_SB_CONFIG_7_TX_TMR_MODE … #define BNX2_HC_SB_CONFIG_7_COM_TMR_MODE … #define BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE … #define BNX2_HC_SB_CONFIG_7_PER_MODE … #define BNX2_HC_SB_CONFIG_7_ONE_SHOT … #define BNX2_HC_SB_CONFIG_7_USE_INT_PARAM … #define BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT … #define BNX2_HC_TX_QUICK_CONS_TRIP_7 … #define BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE … #define BNX2_HC_TX_QUICK_CONS_TRIP_7_INT … #define BNX2_HC_COMP_PROD_TRIP_7 … #define BNX2_HC_COMP_PROD_TRIP_7_VALUE … #define BNX2_HC_COMP_PROD_TRIP_7_INT … #define BNX2_HC_RX_QUICK_CONS_TRIP_7 … #define BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE … #define BNX2_HC_RX_QUICK_CONS_TRIP_7_INT … #define BNX2_HC_RX_TICKS_7 … #define BNX2_HC_RX_TICKS_7_VALUE … #define BNX2_HC_RX_TICKS_7_INT … #define BNX2_HC_TX_TICKS_7 … #define BNX2_HC_TX_TICKS_7_VALUE … #define BNX2_HC_TX_TICKS_7_INT … #define BNX2_HC_COM_TICKS_7 … #define BNX2_HC_COM_TICKS_7_VALUE … #define BNX2_HC_COM_TICKS_7_INT … #define BNX2_HC_CMD_TICKS_7 … #define BNX2_HC_CMD_TICKS_7_VALUE … #define BNX2_HC_CMD_TICKS_7_INT … #define BNX2_HC_PERIODIC_TICKS_7 … #define BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS … #define BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS … #define BNX2_HC_SB_CONFIG_8 … #define BNX2_HC_SB_CONFIG_8_RX_TMR_MODE … #define BNX2_HC_SB_CONFIG_8_TX_TMR_MODE … #define BNX2_HC_SB_CONFIG_8_COM_TMR_MODE … #define BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE … #define BNX2_HC_SB_CONFIG_8_PER_MODE … #define BNX2_HC_SB_CONFIG_8_ONE_SHOT … #define BNX2_HC_SB_CONFIG_8_USE_INT_PARAM … #define BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT … #define BNX2_HC_TX_QUICK_CONS_TRIP_8 … #define BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE … #define BNX2_HC_TX_QUICK_CONS_TRIP_8_INT … #define BNX2_HC_COMP_PROD_TRIP_8 … #define BNX2_HC_COMP_PROD_TRIP_8_VALUE … #define BNX2_HC_COMP_PROD_TRIP_8_INT … #define BNX2_HC_RX_QUICK_CONS_TRIP_8 … #define BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE … #define BNX2_HC_RX_QUICK_CONS_TRIP_8_INT … #define BNX2_HC_RX_TICKS_8 … #define BNX2_HC_RX_TICKS_8_VALUE … #define BNX2_HC_RX_TICKS_8_INT … #define BNX2_HC_TX_TICKS_8 … #define BNX2_HC_TX_TICKS_8_VALUE … #define BNX2_HC_TX_TICKS_8_INT … #define BNX2_HC_COM_TICKS_8 … #define BNX2_HC_COM_TICKS_8_VALUE … #define BNX2_HC_COM_TICKS_8_INT … #define BNX2_HC_CMD_TICKS_8 … #define BNX2_HC_CMD_TICKS_8_VALUE … #define BNX2_HC_CMD_TICKS_8_INT … #define BNX2_HC_PERIODIC_TICKS_8 … #define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS … #define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS … #define BNX2_HC_SB_CONFIG_SIZE … #define BNX2_HC_COMP_PROD_TRIP_OFF … #define BNX2_HC_COM_TICKS_OFF … #define BNX2_HC_CMD_TICKS_OFF … #define BNX2_HC_TX_QUICK_CONS_TRIP_OFF … #define BNX2_HC_TX_TICKS_OFF … #define BNX2_HC_RX_QUICK_CONS_TRIP_OFF … #define BNX2_HC_RX_TICKS_OFF … /* * txp_reg definition * offset: 0x40000 */ #define BNX2_TXP_CPU_MODE … #define BNX2_TXP_CPU_MODE_LOCAL_RST … #define BNX2_TXP_CPU_MODE_STEP_ENA … #define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA … #define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA … #define BNX2_TXP_CPU_MODE_MSG_BIT1 … #define BNX2_TXP_CPU_MODE_INTERRUPT_ENA … #define BNX2_TXP_CPU_MODE_SOFT_HALT … #define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA … #define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA … #define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA … #define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA … #define BNX2_TXP_CPU_STATE … #define BNX2_TXP_CPU_STATE_BREAKPOINT … #define BNX2_TXP_CPU_STATE_BAD_INST_HALTED … #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED … #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED … #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED … #define BNX2_TXP_CPU_STATE_BAD_PC_HALTED … #define BNX2_TXP_CPU_STATE_ALIGN_HALTED … #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED … #define BNX2_TXP_CPU_STATE_SOFT_HALTED … #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW … #define BNX2_TXP_CPU_STATE_INTERRUPT … #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL … #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL … #define BNX2_TXP_CPU_STATE_BLOCKED_READ … #define BNX2_TXP_CPU_EVENT_MASK … #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK … #define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK … #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK … #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK … #define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK … #define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK … #define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK … #define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK … #define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK … #define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK … #define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK … #define BNX2_TXP_CPU_PROGRAM_COUNTER … #define BNX2_TXP_CPU_INSTRUCTION … #define BNX2_TXP_CPU_DATA_ACCESS … #define BNX2_TXP_CPU_INTERRUPT_ENABLE … #define BNX2_TXP_CPU_INTERRUPT_VECTOR … #define BNX2_TXP_CPU_INTERRUPT_SAVED_PC … #define BNX2_TXP_CPU_HW_BREAKPOINT … #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE … #define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS … #define BNX2_TXP_CPU_DEBUG_VECT_PEEK … #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE … #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN … #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL … #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE … #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN … #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL … #define BNX2_TXP_CPU_LAST_BRANCH_ADDR … #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE … #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP … #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH … #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA … #define BNX2_TXP_CPU_REG_FILE … #define BNX2_TXP_TXPQ … #define BNX2_TXP_FTQ_CMD … #define BNX2_TXP_FTQ_CMD_OFFSET … #define BNX2_TXP_FTQ_CMD_WR_TOP … #define BNX2_TXP_FTQ_CMD_WR_TOP_0 … #define BNX2_TXP_FTQ_CMD_WR_TOP_1 … #define BNX2_TXP_FTQ_CMD_SFT_RESET … #define BNX2_TXP_FTQ_CMD_RD_DATA … #define BNX2_TXP_FTQ_CMD_ADD_INTERVEN … #define BNX2_TXP_FTQ_CMD_ADD_DATA … #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR … #define BNX2_TXP_FTQ_CMD_POP … #define BNX2_TXP_FTQ_CMD_BUSY … #define BNX2_TXP_FTQ_CTL … #define BNX2_TXP_FTQ_CTL_INTERVENE … #define BNX2_TXP_FTQ_CTL_OVERFLOW … #define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE … #define BNX2_TXP_FTQ_CTL_MAX_DEPTH … #define BNX2_TXP_FTQ_CTL_CUR_DEPTH … #define BNX2_TXP_SCRATCH … /* * tpat_reg definition * offset: 0x80000 */ #define BNX2_TPAT_CPU_MODE … #define BNX2_TPAT_CPU_MODE_LOCAL_RST … #define BNX2_TPAT_CPU_MODE_STEP_ENA … #define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA … #define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA … #define BNX2_TPAT_CPU_MODE_MSG_BIT1 … #define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA … #define BNX2_TPAT_CPU_MODE_SOFT_HALT … #define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA … #define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA … #define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA … #define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA … #define BNX2_TPAT_CPU_STATE … #define BNX2_TPAT_CPU_STATE_BREAKPOINT … #define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED … #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED … #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED … #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED … #define BNX2_TPAT_CPU_STATE_BAD_PC_HALTED … #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED … #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED … #define BNX2_TPAT_CPU_STATE_SOFT_HALTED … #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW … #define BNX2_TPAT_CPU_STATE_INTERRUPT … #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL … #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL … #define BNX2_TPAT_CPU_STATE_BLOCKED_READ … #define BNX2_TPAT_CPU_EVENT_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK … #define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK … #define BNX2_TPAT_CPU_PROGRAM_COUNTER … #define BNX2_TPAT_CPU_INSTRUCTION … #define BNX2_TPAT_CPU_DATA_ACCESS … #define BNX2_TPAT_CPU_INTERRUPT_ENABLE … #define BNX2_TPAT_CPU_INTERRUPT_VECTOR … #define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC … #define BNX2_TPAT_CPU_HW_BREAKPOINT … #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE … #define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS … #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK … #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE … #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN … #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL … #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE … #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN … #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL … #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR … #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE … #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP … #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH … #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA … #define BNX2_TPAT_CPU_REG_FILE … #define BNX2_TPAT_TPATQ … #define BNX2_TPAT_FTQ_CMD … #define BNX2_TPAT_FTQ_CMD_OFFSET … #define BNX2_TPAT_FTQ_CMD_WR_TOP … #define BNX2_TPAT_FTQ_CMD_WR_TOP_0 … #define BNX2_TPAT_FTQ_CMD_WR_TOP_1 … #define BNX2_TPAT_FTQ_CMD_SFT_RESET … #define BNX2_TPAT_FTQ_CMD_RD_DATA … #define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN … #define BNX2_TPAT_FTQ_CMD_ADD_DATA … #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR … #define BNX2_TPAT_FTQ_CMD_POP … #define BNX2_TPAT_FTQ_CMD_BUSY … #define BNX2_TPAT_FTQ_CTL … #define BNX2_TPAT_FTQ_CTL_INTERVENE … #define BNX2_TPAT_FTQ_CTL_OVERFLOW … #define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE … #define BNX2_TPAT_FTQ_CTL_MAX_DEPTH … #define BNX2_TPAT_FTQ_CTL_CUR_DEPTH … #define BNX2_TPAT_SCRATCH … /* * rxp_reg definition * offset: 0xc0000 */ #define BNX2_RXP_CPU_MODE … #define BNX2_RXP_CPU_MODE_LOCAL_RST … #define BNX2_RXP_CPU_MODE_STEP_ENA … #define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA … #define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA … #define BNX2_RXP_CPU_MODE_MSG_BIT1 … #define BNX2_RXP_CPU_MODE_INTERRUPT_ENA … #define BNX2_RXP_CPU_MODE_SOFT_HALT … #define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA … #define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA … #define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA … #define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA … #define BNX2_RXP_CPU_STATE … #define BNX2_RXP_CPU_STATE_BREAKPOINT … #define BNX2_RXP_CPU_STATE_BAD_INST_HALTED … #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED … #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED … #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED … #define BNX2_RXP_CPU_STATE_BAD_PC_HALTED … #define BNX2_RXP_CPU_STATE_ALIGN_HALTED … #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED … #define BNX2_RXP_CPU_STATE_SOFT_HALTED … #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW … #define BNX2_RXP_CPU_STATE_INTERRUPT … #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL … #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL … #define BNX2_RXP_CPU_STATE_BLOCKED_READ … #define BNX2_RXP_CPU_EVENT_MASK … #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK … #define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK … #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK … #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK … #define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK … #define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK … #define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK … #define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK … #define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK … #define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK … #define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK … #define BNX2_RXP_CPU_PROGRAM_COUNTER … #define BNX2_RXP_CPU_INSTRUCTION … #define BNX2_RXP_CPU_DATA_ACCESS … #define BNX2_RXP_CPU_INTERRUPT_ENABLE … #define BNX2_RXP_CPU_INTERRUPT_VECTOR … #define BNX2_RXP_CPU_INTERRUPT_SAVED_PC … #define BNX2_RXP_CPU_HW_BREAKPOINT … #define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE … #define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS … #define BNX2_RXP_CPU_DEBUG_VECT_PEEK … #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE … #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN … #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL … #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE … #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN … #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL … #define BNX2_RXP_CPU_LAST_BRANCH_ADDR … #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE … #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP … #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH … #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA … #define BNX2_RXP_CPU_REG_FILE … #define BNX2_RXP_PFE_PFE_CTL … #define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14 … #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15 … #define BNX2_RXP_PFE_PFE_CTL_PFE_COUNT … #define BNX2_RXP_PFE_PFE_CTL_OFFSET … #define BNX2_RXP_RXPCQ … #define BNX2_RXP_CFTQ_CMD … #define BNX2_RXP_CFTQ_CMD_OFFSET … #define BNX2_RXP_CFTQ_CMD_WR_TOP … #define BNX2_RXP_CFTQ_CMD_WR_TOP_0 … #define BNX2_RXP_CFTQ_CMD_WR_TOP_1 … #define BNX2_RXP_CFTQ_CMD_SFT_RESET … #define BNX2_RXP_CFTQ_CMD_RD_DATA … #define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN … #define BNX2_RXP_CFTQ_CMD_ADD_DATA … #define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR … #define BNX2_RXP_CFTQ_CMD_POP … #define BNX2_RXP_CFTQ_CMD_BUSY … #define BNX2_RXP_CFTQ_CTL … #define BNX2_RXP_CFTQ_CTL_INTERVENE … #define BNX2_RXP_CFTQ_CTL_OVERFLOW … #define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE … #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH … #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH … #define BNX2_RXP_RXPQ … #define BNX2_RXP_FTQ_CMD … #define BNX2_RXP_FTQ_CMD_OFFSET … #define BNX2_RXP_FTQ_CMD_WR_TOP … #define BNX2_RXP_FTQ_CMD_WR_TOP_0 … #define BNX2_RXP_FTQ_CMD_WR_TOP_1 … #define BNX2_RXP_FTQ_CMD_SFT_RESET … #define BNX2_RXP_FTQ_CMD_RD_DATA … #define BNX2_RXP_FTQ_CMD_ADD_INTERVEN … #define BNX2_RXP_FTQ_CMD_ADD_DATA … #define BNX2_RXP_FTQ_CMD_INTERVENE_CLR … #define BNX2_RXP_FTQ_CMD_POP … #define BNX2_RXP_FTQ_CMD_BUSY … #define BNX2_RXP_FTQ_CTL … #define BNX2_RXP_FTQ_CTL_INTERVENE … #define BNX2_RXP_FTQ_CTL_OVERFLOW … #define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE … #define BNX2_RXP_FTQ_CTL_MAX_DEPTH … #define BNX2_RXP_FTQ_CTL_CUR_DEPTH … #define BNX2_RXP_SCRATCH … #define BNX2_RXP_SCRATCH_RXP_FLOOD … #define BNX2_RXP_SCRATCH_RSS_TBL_SZ … #define BNX2_RXP_SCRATCH_RSS_TBL … #define BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES … /* * com_reg definition * offset: 0x100000 */ #define BNX2_COM_CKSUM_ERROR_STATUS … #define BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED … #define BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED … #define BNX2_COM_CPU_MODE … #define BNX2_COM_CPU_MODE_LOCAL_RST … #define BNX2_COM_CPU_MODE_STEP_ENA … #define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA … #define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA … #define BNX2_COM_CPU_MODE_MSG_BIT1 … #define BNX2_COM_CPU_MODE_INTERRUPT_ENA … #define BNX2_COM_CPU_MODE_SOFT_HALT … #define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA … #define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA … #define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA … #define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA … #define BNX2_COM_CPU_STATE … #define BNX2_COM_CPU_STATE_BREAKPOINT … #define BNX2_COM_CPU_STATE_BAD_INST_HALTED … #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED … #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED … #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED … #define BNX2_COM_CPU_STATE_BAD_PC_HALTED … #define BNX2_COM_CPU_STATE_ALIGN_HALTED … #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED … #define BNX2_COM_CPU_STATE_SOFT_HALTED … #define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW … #define BNX2_COM_CPU_STATE_INTERRUPT … #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL … #define BNX2_COM_CPU_STATE_INST_FETCH_STALL … #define BNX2_COM_CPU_STATE_BLOCKED_READ … #define BNX2_COM_CPU_EVENT_MASK … #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK … #define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK … #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK … #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK … #define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK … #define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK … #define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK … #define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK … #define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK … #define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK … #define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK … #define BNX2_COM_CPU_PROGRAM_COUNTER … #define BNX2_COM_CPU_INSTRUCTION … #define BNX2_COM_CPU_DATA_ACCESS … #define BNX2_COM_CPU_INTERRUPT_ENABLE … #define BNX2_COM_CPU_INTERRUPT_VECTOR … #define BNX2_COM_CPU_INTERRUPT_SAVED_PC … #define BNX2_COM_CPU_HW_BREAKPOINT … #define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE … #define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS … #define BNX2_COM_CPU_DEBUG_VECT_PEEK … #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE … #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN … #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL … #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE … #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN … #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL … #define BNX2_COM_CPU_LAST_BRANCH_ADDR … #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE … #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP … #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH … #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA … #define BNX2_COM_CPU_REG_FILE … #define BNX2_COM_COMTQ_PFE_PFE_CTL … #define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15 … #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT … #define BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET … #define BNX2_COM_COMXQ … #define BNX2_COM_COMXQ_FTQ_CMD … #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET … #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP … #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 … #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 … #define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET … #define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA … #define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN … #define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA … #define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR … #define BNX2_COM_COMXQ_FTQ_CMD_POP … #define BNX2_COM_COMXQ_FTQ_CMD_BUSY … #define BNX2_COM_COMXQ_FTQ_CTL … #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE … #define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW … #define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE … #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH … #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH … #define BNX2_COM_COMTQ … #define BNX2_COM_COMTQ_FTQ_CMD … #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET … #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP … #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 … #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 … #define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET … #define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA … #define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN … #define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA … #define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR … #define BNX2_COM_COMTQ_FTQ_CMD_POP … #define BNX2_COM_COMTQ_FTQ_CMD_BUSY … #define BNX2_COM_COMTQ_FTQ_CTL … #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE … #define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW … #define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE … #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH … #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH … #define BNX2_COM_COMQ … #define BNX2_COM_COMQ_FTQ_CMD … #define BNX2_COM_COMQ_FTQ_CMD_OFFSET … #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP … #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 … #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 … #define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET … #define BNX2_COM_COMQ_FTQ_CMD_RD_DATA … #define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN … #define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA … #define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR … #define BNX2_COM_COMQ_FTQ_CMD_POP … #define BNX2_COM_COMQ_FTQ_CMD_BUSY … #define BNX2_COM_COMQ_FTQ_CTL … #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE … #define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW … #define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE … #define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH … #define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH … #define BNX2_COM_SCRATCH … #define BNX2_FW_RX_LOW_LATENCY … #define BNX2_FW_RX_DROP_COUNT … /* * cp_reg definition * offset: 0x180000 */ #define BNX2_CP_CKSUM_ERROR_STATUS … #define BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED … #define BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED … #define BNX2_CP_CPU_MODE … #define BNX2_CP_CPU_MODE_LOCAL_RST … #define BNX2_CP_CPU_MODE_STEP_ENA … #define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA … #define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA … #define BNX2_CP_CPU_MODE_MSG_BIT1 … #define BNX2_CP_CPU_MODE_INTERRUPT_ENA … #define BNX2_CP_CPU_MODE_SOFT_HALT … #define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA … #define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA … #define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA … #define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA … #define BNX2_CP_CPU_STATE … #define BNX2_CP_CPU_STATE_BREAKPOINT … #define BNX2_CP_CPU_STATE_BAD_INST_HALTED … #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED … #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED … #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED … #define BNX2_CP_CPU_STATE_BAD_PC_HALTED … #define BNX2_CP_CPU_STATE_ALIGN_HALTED … #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED … #define BNX2_CP_CPU_STATE_SOFT_HALTED … #define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW … #define BNX2_CP_CPU_STATE_INTERRUPT … #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL … #define BNX2_CP_CPU_STATE_INST_FETCH_STALL … #define BNX2_CP_CPU_STATE_BLOCKED_READ … #define BNX2_CP_CPU_EVENT_MASK … #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK … #define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK … #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK … #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK … #define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK … #define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK … #define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK … #define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK … #define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK … #define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK … #define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK … #define BNX2_CP_CPU_PROGRAM_COUNTER … #define BNX2_CP_CPU_INSTRUCTION … #define BNX2_CP_CPU_DATA_ACCESS … #define BNX2_CP_CPU_INTERRUPT_ENABLE … #define BNX2_CP_CPU_INTERRUPT_VECTOR … #define BNX2_CP_CPU_INTERRUPT_SAVED_PC … #define BNX2_CP_CPU_HW_BREAKPOINT … #define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE … #define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS … #define BNX2_CP_CPU_DEBUG_VECT_PEEK … #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE … #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN … #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL … #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE … #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN … #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL … #define BNX2_CP_CPU_LAST_BRANCH_ADDR … #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE … #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP … #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH … #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA … #define BNX2_CP_CPU_REG_FILE … #define BNX2_CP_CPQ_PFE_PFE_CTL … #define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15 … #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT … #define BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET … #define BNX2_CP_CPQ … #define BNX2_CP_CPQ_FTQ_CMD … #define BNX2_CP_CPQ_FTQ_CMD_OFFSET … #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP … #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 … #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 … #define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET … #define BNX2_CP_CPQ_FTQ_CMD_RD_DATA … #define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN … #define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA … #define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR … #define BNX2_CP_CPQ_FTQ_CMD_POP … #define BNX2_CP_CPQ_FTQ_CMD_BUSY … #define BNX2_CP_CPQ_FTQ_CTL … #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE … #define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW … #define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE … #define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH … #define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH … #define BNX2_CP_SCRATCH … #define BNX2_FW_MAX_ISCSI_CONN … /* * mcp_reg definition * offset: 0x140000 */ #define BNX2_MCP_MCP_CONTROL … #define BNX2_MCP_MCP_CONTROL_SMBUS_SEL … #define BNX2_MCP_MCP_CONTROL_MCP_ISOLATE … #define BNX2_MCP_MCP_ATTENTION_STATUS … #define BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL … #define BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT … #define BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT … #define BNX2_MCP_MCP_HEARTBEAT_CONTROL … #define BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE … #define BNX2_MCP_MCP_HEARTBEAT_STATUS … #define BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD … #define BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID … #define BNX2_MCP_MCP_HEARTBEAT … #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT … #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC … #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET … #define BNX2_MCP_WATCHDOG_RESET … #define BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET … #define BNX2_MCP_WATCHDOG_CONTROL … #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT … #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN … #define BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE … #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE … #define BNX2_MCP_ACCESS_LOCK … #define BNX2_MCP_ACCESS_LOCK_LOCK … #define BNX2_MCP_TOE_ID … #define BNX2_MCP_TOE_ID_FUNCTION_ID … #define BNX2_MCP_MAILBOX_CFG … #define BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET … #define BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE … #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC … #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET … #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE … #define BNX2_MCP_MCP_DOORBELL … #define BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL … #define BNX2_MCP_DRIVER_DOORBELL … #define BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL … #define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC … #define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL … #define BNX2_MCP_CPU_MODE … #define BNX2_MCP_CPU_MODE_LOCAL_RST … #define BNX2_MCP_CPU_MODE_STEP_ENA … #define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA … #define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA … #define BNX2_MCP_CPU_MODE_MSG_BIT1 … #define BNX2_MCP_CPU_MODE_INTERRUPT_ENA … #define BNX2_MCP_CPU_MODE_SOFT_HALT … #define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA … #define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA … #define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA … #define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA … #define BNX2_MCP_CPU_STATE … #define BNX2_MCP_CPU_STATE_BREAKPOINT … #define BNX2_MCP_CPU_STATE_BAD_INST_HALTED … #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED … #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED … #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED … #define BNX2_MCP_CPU_STATE_BAD_PC_HALTED … #define BNX2_MCP_CPU_STATE_ALIGN_HALTED … #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED … #define BNX2_MCP_CPU_STATE_SOFT_HALTED … #define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW … #define BNX2_MCP_CPU_STATE_INTERRUPT … #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL … #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL … #define BNX2_MCP_CPU_STATE_BLOCKED_READ … #define BNX2_MCP_CPU_EVENT_MASK … #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK … #define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK … #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK … #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK … #define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK … #define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK … #define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK … #define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK … #define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK … #define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK … #define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK … #define BNX2_MCP_CPU_PROGRAM_COUNTER … #define BNX2_MCP_CPU_INSTRUCTION … #define BNX2_MCP_CPU_DATA_ACCESS … #define BNX2_MCP_CPU_INTERRUPT_ENABLE … #define BNX2_MCP_CPU_INTERRUPT_VECTOR … #define BNX2_MCP_CPU_INTERRUPT_SAVED_PC … #define BNX2_MCP_CPU_HW_BREAKPOINT … #define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE … #define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS … #define BNX2_MCP_CPU_DEBUG_VECT_PEEK … #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE … #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN … #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL … #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE … #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN … #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL … #define BNX2_MCP_CPU_LAST_BRANCH_ADDR … #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE … #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP … #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH … #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA … #define BNX2_MCP_CPU_REG_FILE … #define BNX2_MCP_MCPQ … #define BNX2_MCP_MCPQ_FTQ_CMD … #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET … #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP … #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 … #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 … #define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET … #define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA … #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN … #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA … #define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR … #define BNX2_MCP_MCPQ_FTQ_CMD_POP … #define BNX2_MCP_MCPQ_FTQ_CMD_BUSY … #define BNX2_MCP_MCPQ_FTQ_CTL … #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE … #define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW … #define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE … #define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH … #define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH … #define BNX2_MCP_ROM … #define BNX2_MCP_SCRATCH … #define BNX2_MCP_STATE_P1 … #define BNX2_MCP_STATE_P0 … #define BNX2_MCP_STATE_P1_5708 … #define BNX2_MCP_STATE_P0_5708 … #define BNX2_SHM_HDR_SIGNATURE … #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK … #define BNX2_SHM_HDR_SIGNATURE_SIG … #define BNX2_SHM_HDR_SIGNATURE_VER_MASK … #define BNX2_SHM_HDR_SIGNATURE_VER_ONE … #define BNX2_SHM_HDR_ADDR_0 … #define BNX2_SHM_HDR_ADDR_1 … #define NUM_MC_HASH_REGISTERS … /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ #define PHY_BCM5706_PHY_ID … #define PHY_ID(id) … #define PHY_REV_ID(id) … /* 5708 Serdes PHY registers */ #define BCM5708S_BMCR_FORCE_2500 … #define BCM5708S_UP1 … #define BCM5708S_UP1_2G5 … #define BCM5708S_BLK_ADDR … #define BCM5708S_BLK_ADDR_DIG … #define BCM5708S_BLK_ADDR_DIG3 … #define BCM5708S_BLK_ADDR_TX_MISC … /* Digital Block */ #define BCM5708S_1000X_CTL1 … #define BCM5708S_1000X_CTL1_FIBER_MODE … #define BCM5708S_1000X_CTL1_AUTODET_EN … #define BCM5708S_1000X_CTL2 … #define BCM5708S_1000X_CTL2_PLLEL_DET_EN … #define BCM5708S_1000X_STAT1 … #define BCM5708S_1000X_STAT1_SGMII … #define BCM5708S_1000X_STAT1_LINK … #define BCM5708S_1000X_STAT1_FD … #define BCM5708S_1000X_STAT1_SPEED_MASK … #define BCM5708S_1000X_STAT1_SPEED_10 … #define BCM5708S_1000X_STAT1_SPEED_100 … #define BCM5708S_1000X_STAT1_SPEED_1G … #define BCM5708S_1000X_STAT1_SPEED_2G5 … #define BCM5708S_1000X_STAT1_TX_PAUSE … #define BCM5708S_1000X_STAT1_RX_PAUSE … /* Digital3 Block */ #define BCM5708S_DIG_3_0 … #define BCM5708S_DIG_3_0_USE_IEEE … /* Tx/Misc Block */ #define BCM5708S_TX_ACTL1 … #define BCM5708S_TX_ACTL1_DRIVER_VCM … #define BCM5708S_TX_ACTL3 … #define MII_BNX2_EXT_STATUS … #define EXT_STATUS_MDIX … #define MII_BNX2_AUX_CTL … #define AUX_CTL_MISC_CTL … #define AUX_CTL_MISC_CTL_WIRESPEED … #define AUX_CTL_MISC_CTL_AUTOMDIX … #define AUX_CTL_MISC_CTL_WR … #define MII_BNX2_DSP_RW_PORT … #define MII_BNX2_DSP_ADDRESS … #define MII_BNX2_DSP_EXPAND_REG … #define MII_EXPAND_REG1 … #define MII_EXPAND_REG1_RUDI_C … #define MII_EXPAND_SERDES_CTL … #define MII_BNX2_MISC_SHADOW … #define MISC_SHDW_AN_DBG … #define MISC_SHDW_AN_DBG_NOSYNC … #define MISC_SHDW_AN_DBG_RUDI_INVALID … #define MISC_SHDW_MODE_CTL … #define MISC_SHDW_MODE_CTL_SIG_DET … #define MII_BNX2_BLK_ADDR … #define MII_BNX2_BLK_ADDR_IEEE0 … #define MII_BNX2_BLK_ADDR_GP_STATUS … #define MII_BNX2_GP_TOP_AN_STATUS1 … #define MII_BNX2_GP_TOP_AN_SPEED_MSK … #define MII_BNX2_GP_TOP_AN_SPEED_10 … #define MII_BNX2_GP_TOP_AN_SPEED_100 … #define MII_BNX2_GP_TOP_AN_SPEED_1G … #define MII_BNX2_GP_TOP_AN_SPEED_2_5G … #define MII_BNX2_GP_TOP_AN_SPEED_1GKV … #define MII_BNX2_GP_TOP_AN_FD … #define MII_BNX2_BLK_ADDR_SERDES_DIG … #define MII_BNX2_SERDES_DIG_1000XCTL1 … #define MII_BNX2_SD_1000XCTL1_FIBER … #define MII_BNX2_SD_1000XCTL1_AUTODET … #define MII_BNX2_SERDES_DIG_MISC1 … #define MII_BNX2_SD_MISC1_FORCE_MSK … #define MII_BNX2_SD_MISC1_FORCE_2_5G … #define MII_BNX2_SD_MISC1_FORCE … #define MII_BNX2_BLK_ADDR_OVER1G … #define MII_BNX2_OVER1G_UP1 … #define MII_BNX2_BLK_ADDR_BAM_NXTPG … #define MII_BNX2_BAM_NXTPG_CTL … #define MII_BNX2_NXTPG_CTL_BAM … #define MII_BNX2_NXTPG_CTL_T2 … #define MII_BNX2_BLK_ADDR_CL73_USERB0 … #define MII_BNX2_CL73_BAM_CTL1 … #define MII_BNX2_CL73_BAM_EN … #define MII_BNX2_CL73_BAM_STA_MGR_EN … #define MII_BNX2_CL73_BAM_NP_AFT_BP_EN … #define MII_BNX2_BLK_ADDR_AER … #define MII_BNX2_AER_AER … #define MII_BNX2_AER_AER_AN_MMD … #define MII_BNX2_BLK_ADDR_COMBO_IEEEB0 … #define MIN_ETHERNET_PACKET_SIZE … #define MAX_ETHERNET_PACKET_SIZE … #define MAX_ETHERNET_JUMBO_PACKET_SIZE … #define BNX2_RX_COPY_THRESH … #define BNX2_MISC_ENABLE_DEFAULT … #define BNX2_START_UNICAST_ADDRESS_INDEX … #define BNX2_END_UNICAST_ADDRESS_INDEX … #define BNX2_MAX_UNICAST_ADDRESSES … #define DMA_READ_CHANS … #define DMA_WRITE_CHANS … /* Use CPU native page size up to 16K for the ring sizes. */ #if (PAGE_SHIFT > 14) #define BNX2_PAGE_BITS … #else #define BNX2_PAGE_BITS … #endif #define BNX2_PAGE_SIZE … #define BNX2_TX_DESC_CNT … #define BNX2_MAX_TX_DESC_CNT … #define BNX2_MAX_RX_RINGS … #define BNX2_MAX_RX_PG_RINGS … #define BNX2_RX_DESC_CNT … #define BNX2_MAX_RX_DESC_CNT … #define BNX2_MAX_TOTAL_RX_DESC_CNT … #define BNX2_MAX_TOTAL_RX_PG_DESC_CNT … #define BNX2_NEXT_TX_BD(x) … #define BNX2_TX_RING_IDX(x) … #define BNX2_NEXT_RX_BD(x) … #define BNX2_RX_RING_IDX(x) … #define BNX2_RX_PG_RING_IDX(x) … #define BNX2_RX_RING(x) … #define BNX2_RX_IDX(x) … /* Context size. */ #define CTX_SHIFT … #define CTX_SIZE … #define CTX_MASK … #define GET_CID_ADDR(_cid) … #define GET_CID(_cid_addr) … #define PHY_CTX_SHIFT … #define PHY_CTX_SIZE … #define PHY_CTX_MASK … #define GET_PCID_ADDR(_pcid) … #define GET_PCID(_pcid_addr) … #define MB_KERNEL_CTX_SHIFT … #define MB_KERNEL_CTX_SIZE … #define MB_KERNEL_CTX_MASK … #define MB_GET_CID_ADDR(_cid) … #define MAX_CID_CNT … #define MAX_CID_ADDR … #define INVALID_CID_ADDR … #define TX_CID … #define TX_TSS_CID … #define RX_CID … #define RX_RSS_CID … #define RX_MAX_RSS_RINGS … #define RX_MAX_RINGS … #define TX_MAX_TSS_RINGS … #define TX_MAX_RINGS … #define MB_TX_CID_ADDR … #define MB_RX_CID_ADDR … /* * This driver uses new build_skb() API : * RX ring buffer contains pointer to kmalloc() data only, * skb are built only after Hardware filled the frame. */ struct bnx2_sw_bd { … }; /* Its faster to compute this from data than storing it in sw_bd * (less cache misses) */ static inline struct l2_fhdr *get_l2_fhdr(u8 *data) { … } struct bnx2_sw_pg { … }; struct bnx2_sw_tx_bd { … }; #define SW_RXBD_RING_SIZE … #define SW_RXPG_RING_SIZE … #define RXBD_RING_SIZE … #define SW_TXBD_RING_SIZE … #define TXBD_RING_SIZE … /* Buffered flash (Atmel: AT45DB011B) specific information */ #define SEEPROM_PAGE_BITS … #define SEEPROM_PHY_PAGE_SIZE … #define SEEPROM_BYTE_ADDR_MASK … #define SEEPROM_PAGE_SIZE … #define SEEPROM_TOTAL_SIZE … #define BUFFERED_FLASH_PAGE_BITS … #define BUFFERED_FLASH_PHY_PAGE_SIZE … #define BUFFERED_FLASH_BYTE_ADDR_MASK … #define BUFFERED_FLASH_PAGE_SIZE … #define BUFFERED_FLASH_TOTAL_SIZE … #define SAIFUN_FLASH_PAGE_BITS … #define SAIFUN_FLASH_PHY_PAGE_SIZE … #define SAIFUN_FLASH_BYTE_ADDR_MASK … #define SAIFUN_FLASH_PAGE_SIZE … #define SAIFUN_FLASH_BASE_TOTAL_SIZE … #define ST_MICRO_FLASH_PAGE_BITS … #define ST_MICRO_FLASH_PHY_PAGE_SIZE … #define ST_MICRO_FLASH_BYTE_ADDR_MASK … #define ST_MICRO_FLASH_PAGE_SIZE … #define ST_MICRO_FLASH_BASE_TOTAL_SIZE … #define BCM5709_FLASH_PAGE_BITS … #define BCM5709_FLASH_PHY_PAGE_SIZE … #define BCM5709_FLASH_BYTE_ADDR_MASK … #define BCM5709_FLASH_PAGE_SIZE … #define NVRAM_TIMEOUT_COUNT … #define FLASH_STRAP_MASK … #define FLASH_BACKUP_STRAP_MASK … struct flash_spec { … }; #define BNX2_MAX_MSIX_HW_VEC … #define BNX2_MAX_MSIX_VEC … #ifdef BCM_CNIC #define BNX2_MIN_MSIX_VEC … #else #define BNX2_MIN_MSIX_VEC … #endif struct bnx2_irq { … }; struct bnx2_tx_ring_info { … }; struct bnx2_rx_ring_info { … }; struct bnx2_napi { … }; struct bnx2 { … }; #define BNX2_RD(bp, offset) … #define BNX2_WR(bp, offset, val) … #define BNX2_WR16(bp, offset, val) … struct cpu_reg { … }; struct bnx2_fw_file_section { … }; struct bnx2_mips_fw_file_entry { … }; struct bnx2_rv2p_fw_file_entry { … }; struct bnx2_mips_fw_file { … }; struct bnx2_rv2p_fw_file { … }; #define RV2P_P1_FIXUP_PAGE_SIZE_IDX … #define RV2P_BD_PAGE_SIZE_MSK … #define RV2P_BD_PAGE_SIZE … #define RV2P_PROC1 … #define RV2P_PROC2 … /* This value (in milliseconds) determines the frequency of the driver * issuing the PULSE message code. The firmware monitors this periodic * pulse to determine when to switch to an OS-absent mode. */ #define BNX2_DRV_PULSE_PERIOD_MS … /* This value (in milliseconds) determines how long the driver should * wait for an acknowledgement from the firmware before timing out. Once * the firmware has timed out, the driver will assume there is no firmware * running and there won't be any firmware-driver synchronization during a * driver reset. */ #define BNX2_FW_ACK_TIME_OUT_MS … #define BNX2_DRV_RESET_SIGNATURE … #define BNX2_DRV_RESET_SIGNATURE_MAGIC … //#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */ #define BNX2_DRV_MB … #define BNX2_DRV_MSG_CODE … #define BNX2_DRV_MSG_CODE_RESET … #define BNX2_DRV_MSG_CODE_UNLOAD … #define BNX2_DRV_MSG_CODE_SHUTDOWN … #define BNX2_DRV_MSG_CODE_SUSPEND_WOL … #define BNX2_DRV_MSG_CODE_FW_TIMEOUT … #define BNX2_DRV_MSG_CODE_PULSE … #define BNX2_DRV_MSG_CODE_DIAG … #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL … #define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN … #define BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE … #define BNX2_DRV_MSG_CODE_CMD_SET_LINK … #define BNX2_DRV_MSG_DATA … #define BNX2_DRV_MSG_DATA_WAIT0 … #define BNX2_DRV_MSG_DATA_WAIT1 … #define BNX2_DRV_MSG_DATA_WAIT2 … #define BNX2_DRV_MSG_DATA_WAIT3 … #define BNX2_DRV_MSG_SEQ … #define BNX2_FW_MB … #define BNX2_FW_MSG_ACK … #define BNX2_FW_MSG_STATUS_MASK … #define BNX2_FW_MSG_STATUS_OK … #define BNX2_FW_MSG_STATUS_FAILURE … #define BNX2_LINK_STATUS … #define BNX2_LINK_STATUS_INIT_VALUE … #define BNX2_LINK_STATUS_LINK_UP … #define BNX2_LINK_STATUS_LINK_DOWN … #define BNX2_LINK_STATUS_SPEED_MASK … #define BNX2_LINK_STATUS_AN_INCOMPLETE … #define BNX2_LINK_STATUS_10HALF … #define BNX2_LINK_STATUS_10FULL … #define BNX2_LINK_STATUS_100HALF … #define BNX2_LINK_STATUS_100BASE_T4 … #define BNX2_LINK_STATUS_100FULL … #define BNX2_LINK_STATUS_1000HALF … #define BNX2_LINK_STATUS_1000FULL … #define BNX2_LINK_STATUS_2500HALF … #define BNX2_LINK_STATUS_2500FULL … #define BNX2_LINK_STATUS_AN_ENABLED … #define BNX2_LINK_STATUS_AN_COMPLETE … #define BNX2_LINK_STATUS_PARALLEL_DET … #define BNX2_LINK_STATUS_RESERVED … #define BNX2_LINK_STATUS_PARTNER_AD_1000FULL … #define BNX2_LINK_STATUS_PARTNER_AD_1000HALF … #define BNX2_LINK_STATUS_PARTNER_AD_100BT4 … #define BNX2_LINK_STATUS_PARTNER_AD_100FULL … #define BNX2_LINK_STATUS_PARTNER_AD_100HALF … #define BNX2_LINK_STATUS_PARTNER_AD_10FULL … #define BNX2_LINK_STATUS_PARTNER_AD_10HALF … #define BNX2_LINK_STATUS_TX_FC_ENABLED … #define BNX2_LINK_STATUS_RX_FC_ENABLED … #define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP … #define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP … #define BNX2_LINK_STATUS_SERDES_LINK … #define BNX2_LINK_STATUS_PARTNER_AD_2500FULL … #define BNX2_LINK_STATUS_PARTNER_AD_2500HALF … #define BNX2_LINK_STATUS_HEART_BEAT_EXPIRED … #define BNX2_DRV_PULSE_MB … #define BNX2_DRV_PULSE_SEQ_MASK … /* Indicate to the firmware not to go into the * OS absent when it is not getting driver pulse. * This is used for debugging. */ #define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE … #define BNX2_DRV_MB_ARG0 … #define BNX2_NETLINK_SET_LINK_SPEED_10HALF … #define BNX2_NETLINK_SET_LINK_SPEED_10FULL … #define BNX2_NETLINK_SET_LINK_SPEED_10 … #define BNX2_NETLINK_SET_LINK_SPEED_100HALF … #define BNX2_NETLINK_SET_LINK_SPEED_100FULL … #define BNX2_NETLINK_SET_LINK_SPEED_100 … #define BNX2_NETLINK_SET_LINK_SPEED_1GHALF … #define BNX2_NETLINK_SET_LINK_SPEED_1GFULL … #define BNX2_NETLINK_SET_LINK_SPEED_2G5HALF … #define BNX2_NETLINK_SET_LINK_SPEED_2G5FULL … #define BNX2_NETLINK_SET_LINK_SPEED_10GHALF … #define BNX2_NETLINK_SET_LINK_SPEED_10GFULL … #define BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG … #define BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE … #define BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE … #define BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE … #define BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED … #define BNX2_NETLINK_SET_LINK_PHY_RESET … #define BNX2_DEV_INFO_SIGNATURE … #define BNX2_DEV_INFO_SIGNATURE_MAGIC … #define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK … #define BNX2_DEV_INFO_FEATURE_CFG_VALID … #define BNX2_DEV_INFO_SECONDARY_PORT … #define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE … #define BNX2_SHARED_HW_CFG_PART_NUM … #define BNX2_SHARED_HW_CFG_POWER_DISSIPATED … #define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK … #define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK … #define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK … #define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK … #define BNX2_SHARED_HW_CFG … #define BNX2_SHARED_HW_CFG_CONFIG … #define BNX2_SHARED_HW_CFG_DESIGN_NIC … #define BNX2_SHARED_HW_CFG_DESIGN_LOM … #define BNX2_SHARED_HW_CFG_PHY_COPPER … #define BNX2_SHARED_HW_CFG_PHY_FIBER … #define BNX2_SHARED_HW_CFG_PHY_2_5G … #define BNX2_SHARED_HW_CFG_PHY_BACKPLANE … #define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS … #define BNX2_SHARED_HW_CFG_LED_MODE_MASK … #define BNX2_SHARED_HW_CFG_LED_MODE_MAC … #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 … #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 … #define BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX … #define BNX2_SHARED_HW_CFG_CONFIG2 … #define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK … #define BNX2_DEV_INFO_BC_REV … #define BNX2_PORT_HW_CFG_MAC_UPPER … #define BNX2_PORT_HW_CFG_UPPERMAC_MASK … #define BNX2_PORT_HW_CFG_MAC_LOWER … #define BNX2_PORT_HW_CFG_CONFIG … #define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK … #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK … #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN … #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G … #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G … #define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER … #define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER … #define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER … #define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER … #define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER … #define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER … #define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 … #define BNX2_DEV_INFO_FORMAT_REV … #define BNX2_DEV_INFO_FORMAT_REV_MASK … #define BNX2_DEV_INFO_FORMAT_REV_ID … #define BNX2_SHARED_FEATURE … #define BNX2_SHARED_FEATURE_MASK … #define BNX2_PORT_FEATURE … #define BNX2_PORT2_FEATURE … #define BNX2_PORT_FEATURE_WOL_ENABLED … #define BNX2_PORT_FEATURE_MBA_ENABLED … #define BNX2_PORT_FEATURE_ASF_ENABLED … #define BNX2_PORT_FEATURE_IMD_ENABLED … #define BNX2_PORT_FEATURE_BAR1_SIZE_MASK … #define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED … #define BNX2_PORT_FEATURE_BAR1_SIZE_64K … #define BNX2_PORT_FEATURE_BAR1_SIZE_128K … #define BNX2_PORT_FEATURE_BAR1_SIZE_256K … #define BNX2_PORT_FEATURE_BAR1_SIZE_512K … #define BNX2_PORT_FEATURE_BAR1_SIZE_1M … #define BNX2_PORT_FEATURE_BAR1_SIZE_2M … #define BNX2_PORT_FEATURE_BAR1_SIZE_4M … #define BNX2_PORT_FEATURE_BAR1_SIZE_8M … #define BNX2_PORT_FEATURE_BAR1_SIZE_16M … #define BNX2_PORT_FEATURE_BAR1_SIZE_32M … #define BNX2_PORT_FEATURE_BAR1_SIZE_64M … #define BNX2_PORT_FEATURE_BAR1_SIZE_128M … #define BNX2_PORT_FEATURE_BAR1_SIZE_256M … #define BNX2_PORT_FEATURE_BAR1_SIZE_512M … #define BNX2_PORT_FEATURE_BAR1_SIZE_1G … #define BNX2_PORT_FEATURE_WOL … #define BNX2_PORT2_FEATURE_WOL … #define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS … #define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK … #define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE … #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC … #define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI … #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI … #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK … #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG … #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF … #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL … #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF … #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL … #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF … #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL … #define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 … #define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP … #define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP … #define BNX2_PORT_FEATURE_MBA … #define BNX2_PORT2_FEATURE_MBA … #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS … #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK … #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE … #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL … #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP … #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS … #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK … #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG … #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF … #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL … #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF … #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL … #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF … #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL … #define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE … #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S … #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M … #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M … #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS … #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK … #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS … #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK … #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO … #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS … #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H … #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H … #define BNX2_PORT_FEATURE_IMD … #define BNX2_PORT2_FEATURE_IMD … #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT … #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE … #define BNX2_PORT_FEATURE_VLAN … #define BNX2_PORT2_FEATURE_VLAN … #define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK … #define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE … #define BNX2_MFW_VER_PTR … #define BNX2_BC_STATE_RESET_TYPE … #define BNX2_BC_STATE_RESET_TYPE_SIG … #define BNX2_BC_STATE_RESET_TYPE_SIG_MASK … #define BNX2_BC_STATE_RESET_TYPE_NONE … #define BNX2_BC_STATE_RESET_TYPE_PCI … #define BNX2_BC_STATE_RESET_TYPE_VAUX … #define BNX2_BC_STATE_RESET_TYPE_DRV_MASK … #define BNX2_BC_STATE_RESET_TYPE_DRV_RESET … #define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD … #define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN … #define BNX2_BC_STATE_RESET_TYPE_DRV_WOL … #define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG … #define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) … #define BNX2_BC_RESET_TYPE … #define BNX2_BC_STATE … #define BNX2_BC_STATE_ERR_MASK … #define BNX2_BC_STATE_SIGN … #define BNX2_BC_STATE_SIGN_MASK … #define BNX2_BC_STATE_BC1_START … #define BNX2_BC_STATE_GET_NVM_CFG1 … #define BNX2_BC_STATE_PROG_BAR … #define BNX2_BC_STATE_INIT_VID … #define BNX2_BC_STATE_GET_NVM_CFG2 … #define BNX2_BC_STATE_APPLY_WKARND … #define BNX2_BC_STATE_LOAD_BC2 … #define BNX2_BC_STATE_GOING_BC2 … #define BNX2_BC_STATE_GOING_DIAG … #define BNX2_BC_STATE_RT_FINAL_INIT … #define BNX2_BC_STATE_RT_WKARND … #define BNX2_BC_STATE_RT_DRV_PULSE … #define BNX2_BC_STATE_RT_FIOEVTS … #define BNX2_BC_STATE_RT_DRV_CMD … #define BNX2_BC_STATE_RT_LOW_POWER … #define BNX2_BC_STATE_RT_SET_WOL … #define BNX2_BC_STATE_RT_OTHER_FW … #define BNX2_BC_STATE_RT_GOING_D3 … #define BNX2_BC_STATE_ERR_BAD_VERSION … #define BNX2_BC_STATE_ERR_BAD_BC2_CRC … #define BNX2_BC_STATE_ERR_BC1_LOOP … #define BNX2_BC_STATE_ERR_UNKNOWN_CMD … #define BNX2_BC_STATE_ERR_DRV_DEAD … #define BNX2_BC_STATE_ERR_NO_RXP … #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF … #define BNX2_BC_STATE_CONDITION … #define BNX2_CONDITION_MFW_RUN_UNKNOWN … #define BNX2_CONDITION_MFW_RUN_IPMI … #define BNX2_CONDITION_MFW_RUN_UMP … #define BNX2_CONDITION_MFW_RUN_NCSI … #define BNX2_CONDITION_MFW_RUN_NONE … #define BNX2_CONDITION_MFW_RUN_MASK … #define BNX2_CONDITION_PM_STATE_MASK … #define BNX2_CONDITION_PM_STATE_FULL … #define BNX2_CONDITION_PM_STATE_PREP … #define BNX2_CONDITION_PM_STATE_UNPREP … #define BNX2_BC_STATE_DEBUG_CMD … #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE … #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK … #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK … #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE … #define BNX2_FW_EVT_CODE_MB … #define BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT … #define BNX2_FW_EVT_CODE_LINK_EVENT … #define BNX2_DRV_ACK_CAP_MB … #define BNX2_DRV_ACK_CAP_SIGNATURE … #define BNX2_CAPABILITY_SIGNATURE_MASK … #define BNX2_FW_CAP_MB … #define BNX2_FW_CAP_SIGNATURE … #define BNX2_FW_ACK_DRV_SIGNATURE … #define BNX2_FW_CAP_SIGNATURE_MASK … #define BNX2_FW_CAP_REMOTE_PHY_CAPABLE … #define BNX2_FW_CAP_REMOTE_PHY_PRESENT … #define BNX2_FW_CAP_MFW_CAN_KEEP_VLAN … #define BNX2_FW_CAP_BC_CAN_KEEP_VLAN … #define BNX2_FW_CAP_CAN_KEEP_VLAN … #define BNX2_RPHY_SIGNATURE … #define BNX2_RPHY_LOAD_SIGNATURE … #define BNX2_RPHY_FLAGS … #define BNX2_RPHY_SERDES_LINK … #define BNX2_RPHY_COPPER_LINK … #define BNX2_ISCSI_INITIATOR … #define BNX2_ISCSI_INITIATOR_EN … #define BNX2_ISCSI_MAX_CONN … #define BNX2_ISCSI_MAX_CONN_MASK … #define BNX2_ISCSI_MAX_CONN_SHIFT … #define HOST_VIEW_SHMEM_BASE … #define DP_SHMEM_LINE(bp, offset) … #endif
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