/* * tg3.c: Broadcom Tigon3 ethernet driver. * * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller ([email protected]) * Copyright (C) 2001, 2002, 2003 Jeff Garzik ([email protected]) * Copyright (C) 2004 Sun Microsystems Inc. * Copyright (C) 2005-2016 Broadcom Corporation. * Copyright (C) 2016-2017 Broadcom Limited. * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom" * refers to Broadcom Inc. and/or its subsidiaries. * * Firmware is: * Derived from proprietary unpublished source code, * Copyright (C) 2000-2016 Broadcom Corporation. * Copyright (C) 2016-2017 Broadcom Ltd. * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom" * refers to Broadcom Inc. and/or its subsidiaries. * * Permission is hereby granted for the distribution of this firmware * data in hexadecimal or equivalent format, provided this copyright * notice is accompanying it. */ #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/stringify.h> #include <linux/kernel.h> #include <linux/sched/signal.h> #include <linux/types.h> #include <linux/compiler.h> #include <linux/slab.h> #include <linux/delay.h> #include <linux/in.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/pci.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> #include <linux/ethtool.h> #include <linux/mdio.h> #include <linux/mii.h> #include <linux/phy.h> #include <linux/brcmphy.h> #include <linux/if.h> #include <linux/if_vlan.h> #include <linux/ip.h> #include <linux/tcp.h> #include <linux/workqueue.h> #include <linux/prefetch.h> #include <linux/dma-mapping.h> #include <linux/firmware.h> #include <linux/ssb/ssb_driver_gige.h> #include <linux/hwmon.h> #include <linux/hwmon-sysfs.h> #include <linux/crc32poly.h> #include <net/checksum.h> #include <net/gso.h> #include <net/ip.h> #include <linux/io.h> #include <asm/byteorder.h> #include <linux/uaccess.h> #include <uapi/linux/net_tstamp.h> #include <linux/ptp_clock_kernel.h> #define BAR_0 … #define BAR_2 … #include "tg3.h" /* Functions & macros to verify TG3_FLAGS types */ static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) { … } static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) { … } static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) { … } #define tg3_flag(tp, flag) … #define tg3_flag_set(tp, flag) … #define tg3_flag_clear(tp, flag) … #define DRV_MODULE_NAME … /* DO NOT UPDATE TG3_*_NUM defines */ #define TG3_MAJ_NUM … #define TG3_MIN_NUM … #define RESET_KIND_SHUTDOWN … #define RESET_KIND_INIT … #define RESET_KIND_SUSPEND … #define TG3_DEF_RX_MODE … #define TG3_DEF_TX_MODE … #define TG3_DEF_MSG_ENABLE … #define TG3_GRC_LCLCTL_PWRSW_DELAY … /* length of time before we decide the hardware is borked, * and dev->tx_timeout() should be called to fix the problem */ #define TG3_TX_TIMEOUT … /* hardware minimum and maximum for a single frame's data payload */ #define TG3_MIN_MTU … #define TG3_MAX_MTU(tp) … /* These numbers seem to be hard coded in the NIC firmware somehow. * You can't change the ring sizes, but you can change where you place * them in the NIC onboard memory. */ #define TG3_RX_STD_RING_SIZE(tp) … #define TG3_DEF_RX_RING_PENDING … #define TG3_RX_JMB_RING_SIZE(tp) … #define TG3_DEF_RX_JUMBO_RING_PENDING … /* Do not place this n-ring entries value into the tp struct itself, * we really want to expose these constants to GCC so that modulo et * al. operations are done with shifts and masks instead of with * hw multiply/modulo instructions. Another solution would be to * replace things like '% foo' with '& (foo - 1)'. */ #define TG3_TX_RING_SIZE … #define TG3_DEF_TX_RING_PENDING … #define TG3_RX_STD_RING_BYTES(tp) … #define TG3_RX_JMB_RING_BYTES(tp) … #define TG3_RX_RCB_RING_BYTES(tp) … #define TG3_TX_RING_BYTES … #define NEXT_TX(N) … #define TG3_DMA_BYTE_ENAB … #define TG3_RX_STD_DMA_SZ … #define TG3_RX_JMB_DMA_SZ … #define TG3_RX_DMA_TO_MAP_SZ(x) … #define TG3_RX_STD_MAP_SZ … #define TG3_RX_JMB_MAP_SZ … #define TG3_RX_STD_BUFF_RING_SIZE(tp) … #define TG3_RX_JMB_BUFF_RING_SIZE(tp) … /* Due to a hardware bug, the 5701 can only DMA to memory addresses * that are at least dword aligned when used in PCIX mode. The driver * works around this bug by double copying the packet. This workaround * is built into the normal double copy length check for efficiency. * * However, the double copy is only necessary on those architectures * where unaligned memory accesses are inefficient. For those architectures * where unaligned memory accesses incur little penalty, we can reintegrate * the 5701 in the normal rx path. Doing so saves a device structure * dereference by hardcoding the double copy threshold in place. */ #define TG3_RX_COPY_THRESHOLD … #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) #define TG3_RX_COPY_THRESH(tp) … #else #define TG3_RX_COPY_THRESH … #endif #if (NET_IP_ALIGN != 0) #define TG3_RX_OFFSET … #else #define TG3_RX_OFFSET(tp) … #endif /* minimum number of free TX descriptors required to wake up TX process */ #define TG3_TX_WAKEUP_THRESH(tnapi) … #define TG3_TX_BD_DMA_MAX_2K … #define TG3_TX_BD_DMA_MAX_4K … #define TG3_RAW_IP_ALIGN … #define TG3_MAX_UCAST_ADDR(tp) … #define TG3_UCAST_ADDR_IDX(tp) … #define TG3_FW_UPDATE_TIMEOUT_SEC … #define TG3_FW_UPDATE_FREQ_SEC … #define FIRMWARE_TG3 … #define FIRMWARE_TG357766 … #define FIRMWARE_TG3TSO … #define FIRMWARE_TG3TSO5 … MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); static int tg3_debug = …; /* -1 == use TG3_DEF_MSG_ENABLE as value */ module_param(tg3_debug, int, 0); MODULE_PARM_DESC(…) …; #define TG3_DRV_DATA_FLAG_10_100_ONLY … #define TG3_DRV_DATA_FLAG_5705_10_100 … static const struct pci_device_id tg3_pci_tbl[] = …; MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); static const struct { … } ethtool_stats_keys[] = …; #define TG3_NUM_STATS … #define TG3_NVRAM_TEST … #define TG3_LINK_TEST … #define TG3_REGISTER_TEST … #define TG3_MEMORY_TEST … #define TG3_MAC_LOOPB_TEST … #define TG3_PHY_LOOPB_TEST … #define TG3_EXT_LOOPB_TEST … #define TG3_INTERRUPT_TEST … static const struct { … } ethtool_test_keys[] = …; #define TG3_NUM_TEST … static void tg3_write32(struct tg3 *tp, u32 off, u32 val) { … } static u32 tg3_read32(struct tg3 *tp, u32 off) { … } static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) { … } static u32 tg3_ape_read32(struct tg3 *tp, u32 off) { … } static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) { … } static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) { … } static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) { … } static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) { … } static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) { … } /* usec_wait specifies the wait time in usec when writing to certain registers * where it is unsafe to read back the register without some delay. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. */ static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) { … } static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) { … } static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) { … } static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) { … } static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) { … } #define tw32_mailbox(reg, val) … #define tw32_mailbox_f(reg, val) … #define tw32_rx_mbox(reg, val) … #define tw32_tx_mbox(reg, val) … #define tr32_mailbox(reg) … #define tw32(reg, val) … #define tw32_f(reg, val) … #define tw32_wait_f(reg, val, us) … #define tr32(reg) … static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) { … } static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) { … } static void tg3_ape_lock_init(struct tg3 *tp) { … } static int tg3_ape_lock(struct tg3 *tp, int locknum) { … } static void tg3_ape_unlock(struct tg3 *tp, int locknum) { … } static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us) { … } #ifdef CONFIG_TIGON3_HWMON static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us) { … } static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, u32 len) { … } #endif static int tg3_ape_send_event(struct tg3 *tp, u32 event) { … } static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) { … } static void tg3_send_ape_heartbeat(struct tg3 *tp, unsigned long interval) { … } static void tg3_disable_ints(struct tg3 *tp) { … } static void tg3_enable_ints(struct tg3 *tp) { … } static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) { … } /* tg3_int_reenable * similar to tg3_enable_ints, but it accurately determines whether there * is new work pending and can return without flushing the PIO write * which reenables interrupts */ static void tg3_int_reenable(struct tg3_napi *tnapi) { … } static void tg3_switch_clocks(struct tg3 *tp) { … } #define PHY_BUSY_LOOPS … static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val) { … } static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) { … } static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val) { … } static int tg3_writephy(struct tg3 *tp, int reg, u32 val) { … } static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) { … } static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) { … } static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) { … } static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) { … } static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) { … } static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) { … } static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable) { … } static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val) { … } static int tg3_bmcr_reset(struct tg3 *tp) { … } static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) { … } static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) { … } static void tg3_mdio_config_5785(struct tg3 *tp) { … } static void tg3_mdio_start(struct tg3 *tp) { … } static int tg3_mdio_init(struct tg3 *tp) { … } static void tg3_mdio_fini(struct tg3 *tp) { … } /* tp->lock is held. */ static inline void tg3_generate_fw_event(struct tg3 *tp) { … } #define TG3_FW_EVENT_TIMEOUT_USEC … /* tp->lock is held. */ static void tg3_wait_for_event_ack(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data) { … } /* tp->lock is held. */ static void tg3_ump_link_report(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_stop_fw(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) { … } /* tp->lock is held. */ static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) { … } /* tp->lock is held. */ static void tg3_write_sig_legacy(struct tg3 *tp, int kind) { … } static int tg3_poll_fw(struct tg3 *tp) { … } static void tg3_link_report(struct tg3 *tp) { … } static u32 tg3_decode_flowctrl_1000T(u32 adv) { … } static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) { … } static u32 tg3_decode_flowctrl_1000X(u32 adv) { … } static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) { … } static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) { … } static void tg3_adjust_link(struct net_device *dev) { … } static int tg3_phy_init(struct tg3 *tp) { … } static void tg3_phy_start(struct tg3 *tp) { … } static void tg3_phy_stop(struct tg3 *tp) { … } static void tg3_phy_fini(struct tg3 *tp) { … } static int tg3_phy_set_extloopbk(struct tg3 *tp) { … } static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) { … } static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) { … } static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) { … } static void tg3_phy_set_wirespeed(struct tg3 *tp) { … } static void tg3_phy_apply_otp(struct tg3 *tp) { … } static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_keee *eee) { … } static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up) { … } static void tg3_phy_eee_enable(struct tg3 *tp) { … } static int tg3_wait_macro_done(struct tg3 *tp) { … } static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) { … } static int tg3_phy_reset_chanpat(struct tg3 *tp) { … } static int tg3_phy_reset_5703_4_5(struct tg3 *tp) { … } static void tg3_carrier_off(struct tg3 *tp) { … } static void tg3_warn_mgmt_link_flap(struct tg3 *tp) { … } /* This will reset the tigon3 PHY if there is no valid * link unless the FORCE argument is non-zero. */ static int tg3_phy_reset(struct tg3 *tp) { … } #define TG3_GPIO_MSG_DRVR_PRES … #define TG3_GPIO_MSG_NEED_VAUX … #define TG3_GPIO_MSG_MASK … #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK … #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK … static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) { … } static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) { … } static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) { … } static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) { … } static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) { … } static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) { … } static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) { … } static bool tg3_phy_power_bug(struct tg3 *tp) { … } static bool tg3_phy_led_bug(struct tg3 *tp) { … } static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) { … } /* tp->lock is held. */ static int tg3_nvram_lock(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_nvram_unlock(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_enable_nvram_access(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_disable_nvram_access(struct tg3 *tp) { … } static int tg3_nvram_read_using_eeprom(struct tg3 *tp, u32 offset, u32 *val) { … } #define NVRAM_CMD_TIMEOUT … static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) { … } static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) { … } static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) { … } /* NOTE: Data read in from NVRAM is byteswapped according to * the byteswapping settings for all other register accesses. * tg3 devices are BE devices, so on a BE machine, the data * returned will be exactly as it is seen in NVRAM. On a LE * machine, the 32-bit value will be byteswapped. */ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) { … } /* Ensures NVRAM data is in bytestream format. */ static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) { … } static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, u32 offset, u32 len, u8 *buf) { … } /* offset and length are dword aligned */ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, u8 *buf) { … } /* offset and length are dword aligned */ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, u8 *buf) { … } /* offset and length are dword aligned */ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) { … } #define RX_CPU_SCRATCH_BASE … #define RX_CPU_SCRATCH_SIZE … #define TX_CPU_SCRATCH_BASE … #define TX_CPU_SCRATCH_SIZE … /* tp->lock is held. */ static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) { … } /* tp->lock is held. */ static int tg3_rxcpu_pause(struct tg3 *tp) { … } /* tp->lock is held. */ static int tg3_txcpu_pause(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) { … } /* tp->lock is held. */ static void tg3_rxcpu_resume(struct tg3 *tp) { … } /* tp->lock is held. */ static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) { … } static int tg3_fw_data_len(struct tg3 *tp, const struct tg3_firmware_hdr *fw_hdr) { … } /* tp->lock is held. */ static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, int cpu_scratch_size, const struct tg3_firmware_hdr *fw_hdr) { … } /* tp->lock is held. */ static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc) { … } /* tp->lock is held. */ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) { … } static int tg3_validate_rxcpu_state(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_load_57766_firmware(struct tg3 *tp) { … } /* tp->lock is held. */ static int tg3_load_tso_firmware(struct tg3 *tp) { … } /* tp->lock is held. */ static void __tg3_set_one_mac_addr(struct tg3 *tp, const u8 *mac_addr, int index) { … } /* tp->lock is held. */ static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1) { … } static void tg3_enable_register_access(struct tg3 *tp) { … } static int tg3_power_up(struct tg3 *tp) { … } static int tg3_setup_phy(struct tg3 *, bool); static void tg3_power_down_prepare(struct tg3 *tp) { … } static void tg3_power_down(struct tg3 *tp) { … } static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex) { … } static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) { … } static void tg3_phy_copper_begin(struct tg3 *tp) { … } static int tg3_phy_pull_config(struct tg3 *tp) { … } static int tg3_init_5401phy_dsp(struct tg3 *tp) { … } static bool tg3_phy_eee_config_ok(struct tg3 *tp) { … } static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) { … } static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) { … } static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up) { … } static void tg3_clear_mac_status(struct tg3 *tp) { … } static void tg3_setup_eee(struct tg3 *tp) { … } static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset) { … } struct tg3_fiber_aneginfo { … }; #define ANEG_OK … #define ANEG_DONE … #define ANEG_TIMER_ENAB … #define ANEG_FAILED … #define ANEG_STATE_SETTLE_TIME … static int tg3_fiber_aneg_smachine(struct tg3 *tp, struct tg3_fiber_aneginfo *ap) { … } static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) { … } static void tg3_init_bcm8002(struct tg3 *tp) { … } static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) { … } static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) { … } static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset) { … } static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) { … } static void tg3_serdes_parallel_detect(struct tg3 *tp) { … } static int tg3_setup_phy(struct tg3 *tp, bool force_reset) { … } /* tp->lock must be held */ static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts) { … } /* tp->lock must be held */ static void tg3_refclk_write(struct tg3 *tp, u64 newval) { … } static inline void tg3_full_lock(struct tg3 *tp, int irq_sync); static inline void tg3_full_unlock(struct tg3 *tp); static int tg3_get_ts_info(struct net_device *dev, struct kernel_ethtool_ts_info *info) { … } static int tg3_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) { … } static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) { … } static int tg3_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, struct ptp_system_timestamp *sts) { … } static int tg3_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts) { … } static int tg3_ptp_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *rq, int on) { … } static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock, struct skb_shared_hwtstamps *timestamp) { … } static void tg3_read_tx_tstamp(struct tg3 *tp, u64 *hwclock) { … } static long tg3_ptp_ts_aux_work(struct ptp_clock_info *ptp) { … } static const struct ptp_clock_info tg3_ptp_caps = …; /* tp->lock must be held */ static void tg3_ptp_init(struct tg3 *tp) { … } /* tp->lock must be held */ static void tg3_ptp_resume(struct tg3 *tp) { … } static void tg3_ptp_fini(struct tg3 *tp) { … } static inline int tg3_irq_sync(struct tg3 *tp) { … } static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) { … } static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) { … } static void tg3_dump_state(struct tg3 *tp) { … } /* This is called whenever we suspect that the system chipset is re- * ordering the sequence of MMIO to the tx send mailbox. The symptom * is bogus tx completions. We try to recover by setting the * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later * in the workqueue. */ static void tg3_tx_recover(struct tg3 *tp) { … } static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) { … } /* Tigon3 never reports partial packet sends. So we do not * need special logic to handle SKBs that have not had all * of their frags sent yet, like SunGEM does. */ static void tg3_tx(struct tg3_napi *tnapi) { … } static void tg3_frag_free(bool is_frag, void *data) { … } static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) { … } /* Returns size of skb allocated or < 0 on error. * * We only need to fill in the address because the other members * of the RX descriptor are invariant, see tg3_init_rings. * * Note the purposeful assymetry of cpu vs. chip accesses. For * posting buffers we only dirty the first cache line of the RX * descriptor (containing the address). Whereas for the RX status * buffers the cpu only reads the last cacheline of the RX descriptor * (to fetch the error flags, vlan tag, checksum, and opaque cookie). */ static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, u32 opaque_key, u32 dest_idx_unmasked, unsigned int *frag_size) { … } /* We only need to move over in the address because the other * members of the RX descriptor are invariant. See notes above * tg3_alloc_rx_data for full details. */ static void tg3_recycle_rx(struct tg3_napi *tnapi, struct tg3_rx_prodring_set *dpr, u32 opaque_key, int src_idx, u32 dest_idx_unmasked) { … } /* The RX ring scheme is composed of multiple rings which post fresh * buffers to the chip, and one special ring the chip uses to report * status back to the host. * * The special ring reports the status of received packets to the * host. The chip does not write into the original descriptor the * RX buffer was obtained from. The chip simply takes the original * descriptor as provided by the host, updates the status and length * field, then writes this into the next status ring entry. * * Each ring the host uses to post buffers to the chip is described * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, * it is first placed into the on-chip ram. When the packet's length * is known, it walks down the TG3_BDINFO entries to select the ring. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO * which is within the range of the new packet's length is chosen. * * The "separate ring for rx status" scheme may sound queer, but it makes * sense from a cache coherency perspective. If only the host writes * to the buffer post rings, and only the chip writes to the rx status * rings, then cache lines never move beyond shared-modified state. * If both the host and chip were to write into the same ring, cache line * eviction could occur since both entities want it in an exclusive state. */ static int tg3_rx(struct tg3_napi *tnapi, int budget) { … } static void tg3_poll_link(struct tg3 *tp) { … } static int tg3_rx_prodring_xfer(struct tg3 *tp, struct tg3_rx_prodring_set *dpr, struct tg3_rx_prodring_set *spr) { … } static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) { … } static inline void tg3_reset_task_schedule(struct tg3 *tp) { … } static inline void tg3_reset_task_cancel(struct tg3 *tp) { … } static int tg3_poll_msix(struct napi_struct *napi, int budget) { … } static void tg3_process_error(struct tg3 *tp) { … } static int tg3_poll(struct napi_struct *napi, int budget) { … } static void tg3_napi_disable(struct tg3 *tp) { … } static void tg3_napi_enable(struct tg3 *tp) { … } static void tg3_napi_init(struct tg3 *tp) { … } static void tg3_napi_fini(struct tg3 *tp) { … } static inline void tg3_netif_stop(struct tg3 *tp) { … } /* tp->lock must be held */ static inline void tg3_netif_start(struct tg3 *tp) { … } static void tg3_irq_quiesce(struct tg3 *tp) __releases(tp->lock) __acquires(tp->lock) { … } /* Fully shutdown all tg3 driver activity elsewhere in the system. * If irq_sync is non-zero, then the IRQ handler must be synchronized * with as well. Most of the time, this is not necessary except when * shutting down the device. */ static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) { … } static inline void tg3_full_unlock(struct tg3 *tp) { … } /* One-shot MSI handler - Chip automatically disables interrupt * after sending MSI so driver doesn't have to do it. */ static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) { … } /* MSI ISR - No need to check for interrupt sharing and no need to * flush status block and interrupt mailbox. PCI ordering rules * guarantee that MSI will arrive after the status block. */ static irqreturn_t tg3_msi(int irq, void *dev_id) { … } static irqreturn_t tg3_interrupt(int irq, void *dev_id) { … } static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) { … } /* ISR for interrupt test */ static irqreturn_t tg3_test_isr(int irq, void *dev_id) { … } #ifdef CONFIG_NET_POLL_CONTROLLER static void tg3_poll_controller(struct net_device *dev) { … } #endif static void tg3_tx_timeout(struct net_device *dev, unsigned int txqueue) { … } /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) { … } /* Test for TSO DMA buffers that cross into regions which are within MSS bytes * of any 4GB boundaries: 4G, 8G, etc */ static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping, u32 len, u32 mss) { … } /* Test for DMA addresses > 40-bit */ static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, int len) { … } static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd, dma_addr_t mapping, u32 len, u32 flags, u32 mss, u32 vlan) { … } static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget, dma_addr_t map, u32 len, u32 flags, u32 mss, u32 vlan) { … } static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last) { … } /* Workaround 4GB and 40-bit hardware DMA bugs. */ static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, struct sk_buff **pskb, u32 *entry, u32 *budget, u32 base_flags, u32 mss, u32 vlan) { … } static bool tg3_tso_bug_gso_check(struct tg3_napi *tnapi, struct sk_buff *skb) { … } static netdev_tx_t __tg3_start_xmit(struct sk_buff *, struct net_device *); /* Use GSO to workaround all TSO packets that meet HW bug conditions * indicated in tg3_tx_frag_set() */ static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi, struct netdev_queue *txq, struct sk_buff *skb) { … } /* hard_start_xmit for all devices */ static netdev_tx_t __tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) { … } static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) { … } static void tg3_mac_loopback(struct tg3 *tp, bool enable) { … } static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) { … } static void tg3_set_loopback(struct net_device *dev, netdev_features_t features) { … } static netdev_features_t tg3_fix_features(struct net_device *dev, netdev_features_t features) { … } static int tg3_set_features(struct net_device *dev, netdev_features_t features) { … } static void tg3_rx_prodring_free(struct tg3 *tp, struct tg3_rx_prodring_set *tpr) { … } /* Initialize rx rings for packet processing. * * The chip has been shut down and the driver detached from * the networking, so no interrupts or new tx packets will * end up in the driver. tp->{tx,}lock are held and thus * we may not sleep. */ static int tg3_rx_prodring_alloc(struct tg3 *tp, struct tg3_rx_prodring_set *tpr) { … } static void tg3_rx_prodring_fini(struct tg3 *tp, struct tg3_rx_prodring_set *tpr) { … } static int tg3_rx_prodring_init(struct tg3 *tp, struct tg3_rx_prodring_set *tpr) { … } /* Free up pending packets in all rx/tx rings. * * The chip has been shut down and the driver detached from * the networking, so no interrupts or new tx packets will * end up in the driver. tp->{tx,}lock is not held and we are not * in an interrupt context and thus may sleep. */ static void tg3_free_rings(struct tg3 *tp) { … } /* Initialize tx/rx rings for packet processing. * * The chip has been shut down and the driver detached from * the networking, so no interrupts or new tx packets will * end up in the driver. tp->{tx,}lock are held and thus * we may not sleep. */ static int tg3_init_rings(struct tg3 *tp) { … } static void tg3_mem_tx_release(struct tg3 *tp) { … } static int tg3_mem_tx_acquire(struct tg3 *tp) { … } static void tg3_mem_rx_release(struct tg3 *tp) { … } static int tg3_mem_rx_acquire(struct tg3 *tp) { … } /* * Must not be invoked with interrupt sources disabled and * the hardware shutdown down. */ static void tg3_free_consistent(struct tg3 *tp) { … } /* * Must not be invoked with interrupt sources disabled and * the hardware shutdown down. Can sleep. */ static int tg3_alloc_consistent(struct tg3 *tp) { … } #define MAX_WAIT_CNT … /* To stop a block, clear the enable bit and poll till it * clears. tp->lock is held. */ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) { … } /* tp->lock is held. */ static int tg3_abort_hw(struct tg3 *tp, bool silent) { … } /* Save PCI command register before chip reset */ static void tg3_save_pci_state(struct tg3 *tp) { … } /* Restore PCI state after chip reset */ static void tg3_restore_pci_state(struct tg3 *tp) { … } static void tg3_override_clk(struct tg3 *tp) { … } static void tg3_restore_clk(struct tg3 *tp) { … } /* tp->lock is held. */ static int tg3_chip_reset(struct tg3 *tp) __releases(tp->lock) __acquires(tp->lock) { … } static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *); static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *); static void __tg3_set_rx_mode(struct net_device *); /* tp->lock is held. */ static int tg3_halt(struct tg3 *tp, int kind, bool silent) { … } static int tg3_set_mac_addr(struct net_device *dev, void *p) { … } /* tp->lock is held. */ static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, dma_addr_t mapping, u32 maxlen_flags, u32 nic_addr) { … } static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec) { … } static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec) { … } static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) { … } /* tp->lock is held. */ static void tg3_tx_rcbs_disable(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_tx_rcbs_init(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_rx_ret_rcbs_disable(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_rx_ret_rcbs_init(struct tg3 *tp) { … } /* tp->lock is held. */ static void tg3_rings_reset(struct tg3 *tp) { … } static void tg3_setup_rxbd_thresholds(struct tg3 *tp) { … } static inline u32 calc_crc(unsigned char *buf, int len) { … } static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) { … } static void __tg3_set_rx_mode(struct net_device *dev) { … } static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt) { … } static void tg3_rss_check_indir_tbl(struct tg3 *tp) { … } static void tg3_rss_write_indir_tbl(struct tg3 *tp) { … } static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp) { … } /* tp->lock is held. */ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) { … } /* Called at device open time to get the chip ready for * packet processing. Invoked with tp->lock held. */ static int tg3_init_hw(struct tg3 *tp, bool reset_phy) { … } #ifdef CONFIG_TIGON3_HWMON static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir) { … } /* sysfs attributes for hwmon */ static ssize_t tg3_show_temp(struct device *dev, struct device_attribute *devattr, char *buf) { … } static SENSOR_DEVICE_ATTR(temp1_input, 0444, tg3_show_temp, NULL, TG3_TEMP_SENSOR_OFFSET); static SENSOR_DEVICE_ATTR(temp1_crit, 0444, tg3_show_temp, NULL, TG3_TEMP_CAUTION_OFFSET); static SENSOR_DEVICE_ATTR(temp1_max, 0444, tg3_show_temp, NULL, TG3_TEMP_MAX_OFFSET); static struct attribute *tg3_attrs[] = …; ATTRIBUTE_GROUPS(…); static void tg3_hwmon_close(struct tg3 *tp) { … } static void tg3_hwmon_open(struct tg3 *tp) { … } #else static inline void tg3_hwmon_close(struct tg3 *tp) { } static inline void tg3_hwmon_open(struct tg3 *tp) { } #endif /* CONFIG_TIGON3_HWMON */ #define TG3_STAT_ADD32(PSTAT, REG) … static void tg3_periodic_fetch_stats(struct tg3 *tp) { … } static void tg3_chk_missed_msi(struct tg3 *tp) { … } static void tg3_timer(struct timer_list *t) { … } static void tg3_timer_init(struct tg3 *tp) { … } static void tg3_timer_start(struct tg3 *tp) { … } static void tg3_timer_stop(struct tg3 *tp) { … } /* Restart hardware after configuration changes, self-test, etc. * Invoked with tp->lock held. */ static int tg3_restart_hw(struct tg3 *tp, bool reset_phy) __releases(tp->lock) __acquires(tp->lock) { … } static void tg3_reset_task(struct work_struct *work) { … } static int tg3_request_irq(struct tg3 *tp, int irq_num) { … } static int tg3_test_interrupt(struct tg3 *tp) { … } /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is * successfully restored */ static int tg3_test_msi(struct tg3 *tp) { … } static int tg3_request_firmware(struct tg3 *tp) { … } static u32 tg3_irq_count(struct tg3 *tp) { … } static bool tg3_enable_msix(struct tg3 *tp) { … } static void tg3_ints_init(struct tg3 *tp) { … } static void tg3_ints_fini(struct tg3 *tp) { … } static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq, bool init) { … } static void tg3_stop(struct tg3 *tp) { … } static int tg3_open(struct net_device *dev) { … } static int tg3_close(struct net_device *dev) { … } static inline u64 get_stat64(tg3_stat64_t *val) { … } static u64 tg3_calc_crc_errors(struct tg3 *tp) { … } #define ESTAT_ADD(member) … static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats) { … } static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats) { … } static int tg3_get_regs_len(struct net_device *dev) { … } static void tg3_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p) { … } static int tg3_get_eeprom_len(struct net_device *dev) { … } static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) { … } static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) { … } static int tg3_get_link_ksettings(struct net_device *dev, struct ethtool_link_ksettings *cmd) { … } static int tg3_set_link_ksettings(struct net_device *dev, const struct ethtool_link_ksettings *cmd) { … } static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) { … } static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { … } static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { … } static u32 tg3_get_msglevel(struct net_device *dev) { … } static void tg3_set_msglevel(struct net_device *dev, u32 value) { … } static int tg3_nway_reset(struct net_device *dev) { … } static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering, struct kernel_ethtool_ringparam *kernel_ering, struct netlink_ext_ack *extack) { … } static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering, struct kernel_ethtool_ringparam *kernel_ering, struct netlink_ext_ack *extack) { … } static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) { … } static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) { … } static int tg3_get_sset_count(struct net_device *dev, int sset) { … } static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, u32 *rules __always_unused) { … } static u32 tg3_get_rxfh_indir_size(struct net_device *dev) { … } static int tg3_get_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh) { … } static int tg3_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh, struct netlink_ext_ack *extack) { … } static void tg3_get_channels(struct net_device *dev, struct ethtool_channels *channel) { … } static int tg3_set_channels(struct net_device *dev, struct ethtool_channels *channel) { … } static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) { … } static int tg3_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state) { … } static void tg3_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *tmp_stats) { … } static __be32 *tg3_vpd_readblock(struct tg3 *tp, unsigned int *vpdlen) { … } #define NVRAM_TEST_SIZE … #define NVRAM_SELFBOOT_FORMAT1_0_SIZE … #define NVRAM_SELFBOOT_FORMAT1_2_SIZE … #define NVRAM_SELFBOOT_FORMAT1_3_SIZE … #define NVRAM_SELFBOOT_FORMAT1_4_SIZE … #define NVRAM_SELFBOOT_FORMAT1_5_SIZE … #define NVRAM_SELFBOOT_FORMAT1_6_SIZE … #define NVRAM_SELFBOOT_HW_SIZE … #define NVRAM_SELFBOOT_DATA_SIZE … static int tg3_test_nvram(struct tg3 *tp) { … } #define TG3_SERDES_TIMEOUT_SEC … #define TG3_COPPER_TIMEOUT_SEC … static int tg3_test_link(struct tg3 *tp) { … } /* Only test the commonly used registers */ static int tg3_test_registers(struct tg3 *tp) { … } static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) { … } static int tg3_test_memory(struct tg3 *tp) { … } #define TG3_TSO_MSS … #define TG3_TSO_IP_HDR_LEN … #define TG3_TSO_TCP_HDR_LEN … #define TG3_TSO_TCP_OPT_LEN … static const u8 tg3_tso_header[] = …; static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) { … } #define TG3_STD_LOOPBACK_FAILED … #define TG3_JMB_LOOPBACK_FAILED … #define TG3_TSO_LOOPBACK_FAILED … #define TG3_LOOPBACK_FAILED … static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) { … } static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *data) { … } static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) { … } static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) { … } static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { … } static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec, struct kernel_ethtool_coalesce *kernel_coal, struct netlink_ext_ack *extack) { … } static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec, struct kernel_ethtool_coalesce *kernel_coal, struct netlink_ext_ack *extack) { … } static int tg3_set_eee(struct net_device *dev, struct ethtool_keee *edata) { … } static int tg3_get_eee(struct net_device *dev, struct ethtool_keee *edata) { … } static const struct ethtool_ops tg3_ethtool_ops = …; static void tg3_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) { … } static void tg3_set_rx_mode(struct net_device *dev) { … } static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, int new_mtu) { … } static int tg3_change_mtu(struct net_device *dev, int new_mtu) { … } static const struct net_device_ops tg3_netdev_ops = …; static void tg3_get_eeprom_size(struct tg3 *tp) { … } static void tg3_get_nvram_size(struct tg3 *tp) { … } static void tg3_get_nvram_info(struct tg3 *tp) { … } static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) { … } static void tg3_get_5752_nvram_info(struct tg3 *tp) { … } static void tg3_get_5755_nvram_info(struct tg3 *tp) { … } static void tg3_get_5787_nvram_info(struct tg3 *tp) { … } static void tg3_get_5761_nvram_info(struct tg3 *tp) { … } static void tg3_get_5906_nvram_info(struct tg3 *tp) { … } static void tg3_get_57780_nvram_info(struct tg3 *tp) { … } static void tg3_get_5717_nvram_info(struct tg3 *tp) { … } static void tg3_get_5720_nvram_info(struct tg3 *tp) { … } /* Chips other than 5700/5701 use the NVRAM for fetching info. */ static void tg3_nvram_init(struct tg3 *tp) { … } struct subsys_tbl_ent { … }; static struct subsys_tbl_ent subsys_id_to_phy_id[] = …; static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp) { … } static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) { … } static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val) { … } static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd) { … } /* Read the gphy configuration from the OTP region of the chip. The gphy * configuration is a 32-bit value that straddles the alignment boundary. * We do two 32-bit reads and then shift and merge the results. */ static u32 tg3_read_otp_phycfg(struct tg3 *tp) { … } static void tg3_phy_init_link_config(struct tg3 *tp) { … } static int tg3_phy_probe(struct tg3 *tp) { … } static void tg3_read_vpd(struct tg3 *tp) { … } static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) { … } static void tg3_read_bc_ver(struct tg3 *tp) { … } static void tg3_read_hwsb_ver(struct tg3 *tp) { … } static void tg3_read_sb_ver(struct tg3 *tp, u32 val) { … } static void tg3_read_mgmtfw_ver(struct tg3 *tp) { … } static void tg3_probe_ncsi(struct tg3 *tp) { … } static void tg3_read_dash_ver(struct tg3 *tp) { … } static void tg3_read_otp_ver(struct tg3 *tp) { … } static void tg3_read_fw_ver(struct tg3 *tp) { … } static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) { … } static const struct pci_device_id tg3_write_reorder_chipsets[] = …; static struct pci_dev *tg3_find_peer(struct tg3 *tp) { … } static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) { … } static bool tg3_10_100_only_device(struct tg3 *tp, const struct pci_device_id *ent) { … } static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) { … } static int tg3_get_device_address(struct tg3 *tp, u8 *addr) { … } #define BOUNDARY_SINGLE_CACHELINE … #define BOUNDARY_MULTI_CACHELINE … static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val) { … } static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, bool to_device) { … } #define TEST_BUFFER_SIZE … static const struct pci_device_id tg3_dma_wait_state_chipsets[] = …; static int tg3_test_dma(struct tg3 *tp) { … } static void tg3_init_bufmgr_config(struct tg3 *tp) { … } static char *tg3_phy_string(struct tg3 *tp) { … } static char *tg3_bus_string(struct tg3 *tp, char *str) { … } static void tg3_init_coal(struct tg3 *tp) { … } static int tg3_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { … } static void tg3_remove_one(struct pci_dev *pdev) { … } #ifdef CONFIG_PM_SLEEP static int tg3_suspend(struct device *device) { … } static int tg3_resume(struct device *device) { … } #endif /* CONFIG_PM_SLEEP */ static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); static void tg3_shutdown(struct pci_dev *pdev) { … } /** * tg3_io_error_detected - called when PCI error is detected * @pdev: Pointer to PCI device * @state: The current pci connection state * * This function is called after a PCI bus error affecting * this device has been detected. */ static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { … } /** * tg3_io_slot_reset - called after the pci bus has been reset. * @pdev: Pointer to PCI device * * Restart the card from scratch, as if from a cold-boot. * At this point, the card has exprienced a hard reset, * followed by fixups by BIOS, and has its config space * set up identically to what it was at cold boot. */ static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) { … } /** * tg3_io_resume - called when traffic can start flowing again. * @pdev: Pointer to PCI device * * This callback is called when the error recovery driver tells * us that its OK to resume normal operation. */ static void tg3_io_resume(struct pci_dev *pdev) { … } static const struct pci_error_handlers tg3_err_handler = …; static struct pci_driver tg3_driver = …; module_pci_driver(…) …;
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