/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 1999 - 2018 Intel Corporation. */ #ifndef _E1000E_PHY_H_ #define _E1000E_PHY_H_ s32 e1000e_check_downshift(struct e1000_hw *hw); s32 e1000_check_polarity_m88(struct e1000_hw *hw); s32 e1000_check_polarity_igp(struct e1000_hw *hw); s32 e1000_check_polarity_ife(struct e1000_hw *hw); s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw); s32 e1000e_get_phy_id(struct e1000_hw *hw); s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); s32 e1000_get_phy_info_ife(struct e1000_hw *hw); s32 e1000e_phy_sw_reset(struct e1000_hw *hw); void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); s32 e1000e_setup_copper_link(struct e1000_hw *hw); s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, u32 usec_interval, bool *success); s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); s32 e1000e_determine_phy_address(struct e1000_hw *hw); s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); void e1000_power_up_phy_copper(struct e1000_hw *hw); void e1000_power_down_phy_copper(struct e1000_hw *hw); void e1000e_disable_phy_retry(struct e1000_hw *hw); void e1000e_enable_phy_retry(struct e1000_hw *hw); s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); s32 e1000_check_polarity_82577(struct e1000_hw *hw); s32 e1000_get_phy_info_82577(struct e1000_hw *hw); s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); s32 e1000_get_cable_length_82577(struct e1000_hw *hw); #define E1000_MAX_PHY_ADDR … /* IGP01E1000 Specific Registers */ #define IGP01E1000_PHY_PORT_CONFIG … #define IGP01E1000_PHY_PORT_STATUS … #define IGP01E1000_PHY_PORT_CTRL … #define IGP01E1000_PHY_LINK_HEALTH … #define IGP02E1000_PHY_POWER_MGMT … #define IGP01E1000_PHY_PAGE_SELECT … #define BM_PHY_PAGE_SELECT … #define IGP_PAGE_SHIFT … #define PHY_REG_MASK … /* BM/HV Specific Registers */ #define BM_PORT_CTRL_PAGE … #define BM_WUC_PAGE … #define BM_WUC_ADDRESS_OPCODE … #define BM_WUC_DATA_OPCODE … #define BM_WUC_ENABLE_PAGE … #define BM_WUC_ENABLE_REG … #define BM_WUC_ENABLE_BIT … #define BM_WUC_HOST_WU_BIT … #define BM_WUC_ME_WU_BIT … #define PHY_UPPER_SHIFT … #define BM_PHY_REG(page, reg) … #define BM_PHY_REG_PAGE(offset) … #define BM_PHY_REG_NUM(offset) … #define HV_INTC_FC_PAGE_START … #define I82578_ADDR_REG … #define I82577_ADDR_REG … #define I82577_CFG_REG … #define I82577_CFG_ASSERT_CRS_ON_TX … #define I82577_CFG_ENABLE_DOWNSHIFT … #define I82577_CTRL_REG … /* 82577 specific PHY registers */ #define I82577_PHY_CTRL_2 … #define I82577_PHY_LBK_CTRL … #define I82577_PHY_STATUS_2 … #define I82577_PHY_DIAG_STATUS … /* I82577 PHY Status 2 */ #define I82577_PHY_STATUS2_REV_POLARITY … #define I82577_PHY_STATUS2_MDIX … #define I82577_PHY_STATUS2_SPEED_MASK … #define I82577_PHY_STATUS2_SPEED_1000MBPS … /* I82577 PHY Control 2 */ #define I82577_PHY_CTRL2_MANUAL_MDIX … #define I82577_PHY_CTRL2_AUTO_MDI_MDIX … #define I82577_PHY_CTRL2_MDIX_CFG_MASK … /* I82577 PHY Diagnostics Status */ #define I82577_DSTATUS_CABLE_LENGTH … #define I82577_DSTATUS_CABLE_LENGTH_SHIFT … /* BM PHY Copper Specific Control 1 */ #define BM_CS_CTRL1 … /* BM PHY Copper Specific Status */ #define BM_CS_STATUS … #define BM_CS_STATUS_LINK_UP … #define BM_CS_STATUS_RESOLVED … #define BM_CS_STATUS_SPEED_MASK … #define BM_CS_STATUS_SPEED_1000 … /* 82577 Mobile Phy Status Register */ #define HV_M_STATUS … #define HV_M_STATUS_AUTONEG_COMPLETE … #define HV_M_STATUS_SPEED_MASK … #define HV_M_STATUS_SPEED_1000 … #define HV_M_STATUS_SPEED_100 … #define HV_M_STATUS_LINK_UP … #define IGP01E1000_PHY_PCS_INIT_REG … #define IGP01E1000_PHY_POLARITY_MASK … #define IGP01E1000_PSCR_AUTO_MDIX … #define IGP01E1000_PSCR_FORCE_MDI_MDIX … #define IGP01E1000_PSCFR_SMART_SPEED … #define IGP02E1000_PM_SPD … #define IGP02E1000_PM_D0_LPLU … #define IGP02E1000_PM_D3_LPLU … #define IGP01E1000_PLHR_SS_DOWNGRADE … #define IGP01E1000_PSSR_POLARITY_REVERSED … #define IGP01E1000_PSSR_MDIX … #define IGP01E1000_PSSR_SPEED_MASK … #define IGP01E1000_PSSR_SPEED_1000MBPS … #define IGP02E1000_PHY_CHANNEL_NUM … #define IGP02E1000_PHY_AGC_A … #define IGP02E1000_PHY_AGC_B … #define IGP02E1000_PHY_AGC_C … #define IGP02E1000_PHY_AGC_D … #define IGP02E1000_AGC_LENGTH_SHIFT … #define IGP02E1000_AGC_LENGTH_MASK … #define IGP02E1000_AGC_RANGE … #define E1000_CABLE_LENGTH_UNDEFINED … #define E1000_KMRNCTRLSTA_OFFSET … #define E1000_KMRNCTRLSTA_OFFSET_SHIFT … #define E1000_KMRNCTRLSTA_REN … #define E1000_KMRNCTRLSTA_CTRL_OFFSET … #define E1000_KMRNCTRLSTA_DIAG_OFFSET … #define E1000_KMRNCTRLSTA_TIMEOUTS … #define E1000_KMRNCTRLSTA_INBAND_PARAM … #define E1000_KMRNCTRLSTA_IBIST_DISABLE … #define E1000_KMRNCTRLSTA_DIAG_NELPBK … #define E1000_KMRNCTRLSTA_K1_CONFIG … #define E1000_KMRNCTRLSTA_K1_ENABLE … #define E1000_KMRNCTRLSTA_HD_CTRL … #define IFE_PHY_EXTENDED_STATUS_CONTROL … #define IFE_PHY_SPECIAL_CONTROL … #define IFE_PHY_SPECIAL_CONTROL_LED … #define IFE_PHY_MDIX_CONTROL … /* IFE PHY Extended Status Control */ #define IFE_PESC_POLARITY_REVERSED … /* IFE PHY Special Control */ #define IFE_PSC_AUTO_POLARITY_DISABLE … #define IFE_PSC_FORCE_POLARITY … /* IFE PHY Special Control and LED Control */ #define IFE_PSCL_PROBE_MODE … #define IFE_PSCL_PROBE_LEDS_OFF … #define IFE_PSCL_PROBE_LEDS_ON … /* IFE PHY MDIX Control */ #define IFE_PMC_MDIX_STATUS … #define IFE_PMC_FORCE_MDIX … #define IFE_PMC_AUTO_MDIX … #endif
Codebase Browser
linux