/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 1999 - 2018 Intel Corporation. */ /* Linux PRO/1000 Ethernet Driver main header file */ #ifndef _E1000_H_ #define _E1000_H_ #include <linux/bitops.h> #include <linux/types.h> #include <linux/timer.h> #include <linux/workqueue.h> #include <linux/io.h> #include <linux/netdevice.h> #include <linux/pci.h> #include <linux/crc32.h> #include <linux/if_vlan.h> #include <linux/timecounter.h> #include <linux/net_tstamp.h> #include <linux/ptp_clock_kernel.h> #include <linux/ptp_classify.h> #include <linux/mii.h> #include <linux/mdio.h> #include <linux/mutex.h> #include <linux/pm_qos.h> #include "hw.h" struct e1000_info; #define e_dbg(format, arg...) … #define e_err(format, arg...) … #define e_info(format, arg...) … #define e_warn(format, arg...) … #define e_notice(format, arg...) … /* Interrupt modes, as used by the IntMode parameter */ #define E1000E_INT_MODE_LEGACY … #define E1000E_INT_MODE_MSI … #define E1000E_INT_MODE_MSIX … /* Tx/Rx descriptor defines */ #define E1000_DEFAULT_TXD … #define E1000_MAX_TXD … #define E1000_MIN_TXD … #define E1000_DEFAULT_RXD … #define E1000_MAX_RXD … #define E1000_MIN_RXD … #define E1000_MIN_ITR_USECS … #define E1000_MAX_ITR_USECS … #define E1000_FC_PAUSE_TIME … /* How many Tx Descriptors do we need to call netif_wake_queue ? */ /* How many Rx Buffers do we bundle into one write to the hardware ? */ #define E1000_RX_BUFFER_WRITE … #define AUTO_ALL_MODES … #define E1000_EEPROM_APME … #define E1000_MNG_VLAN_NONE … #define DEFAULT_JUMBO … /* Time to wait before putting the device into D3 if there's no link (in ms). */ #define LINK_TIMEOUT … /* Count for polling __E1000_RESET condition every 10-20msec. * Experimentation has shown the reset can take approximately 210msec. */ #define E1000_CHECK_RESET_COUNT … #define PCICFG_DESC_RING_STATUS … #define FLUSH_DESC_REQUIRED … /* in the case of WTHRESH, it appears at least the 82571/2 hardware * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when * WTHRESH=4, so a setting of 5 gives the most efficient bus * utilization but to avoid possible Tx stalls, set it to 1 */ #define E1000_TXDCTL_DMA_BURST_ENABLE … #define E1000_RXDCTL_DMA_BURST_ENABLE … #define E1000_TIDV_FPD … #define E1000_RDTR_FPD … enum e1000_boards { … }; struct e1000_ps_page { … }; /* wrappers around a pointer to a socket buffer, * so a DMA handle can be stored along with the buffer */ struct e1000_buffer { … }; struct e1000_ring { … }; /* PHY register snapshot values */ struct e1000_phy_regs { … }; /* board specific private data structure */ struct e1000_adapter { … }; struct e1000_info { … }; s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); /* The system time is maintained by a 64-bit counter comprised of the 32-bit * SYSTIMH and SYSTIML registers. How the counter increments (and therefore * its resolution) is based on the contents of the TIMINCA register - it * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). * For the best accuracy, the incperiod should be as small as possible. The * incvalue is scaled by a factor as large as possible (while still fitting * in bits 23:0) so that relatively small clock corrections can be made. * * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) * bits to count nanoseconds leaving the rest for fractional nonseconds. * * Any given INCVALUE also has an associated maximum adjustment value. This * maximum adjustment value is the largest increase (or decrease) which can be * safely applied without overflowing the INCVALUE. Since INCVALUE has * a maximum range of 24 bits, its largest value is 0xFFFFFF. * * To understand where the maximum value comes from, consider the following * equation: * * new_incval = base_incval + (base_incval * adjustment) / 1billion * * To avoid overflow that means: * max_incval = base_incval + (base_incval * max_adj) / billion * * Re-arranging: * max_adj = floor(((max_incval - base_incval) * 1billion) / 1billion) */ #define INCVALUE_96MHZ … #define INCVALUE_SHIFT_96MHZ … #define INCPERIOD_SHIFT_96MHZ … #define INCPERIOD_96MHZ … #define MAX_PPB_96MHZ … #define INCVALUE_25MHZ … #define INCVALUE_SHIFT_25MHZ … #define INCPERIOD_25MHZ … #define MAX_PPB_25MHZ … #define INCVALUE_24MHZ … #define INCVALUE_SHIFT_24MHZ … #define INCPERIOD_24MHZ … #define MAX_PPB_24MHZ … #define INCVALUE_38400KHZ … #define INCVALUE_SHIFT_38400KHZ … #define INCPERIOD_38400KHZ … #define MAX_PPB_38400KHZ … /* Another drawback of scaling the incvalue by a large factor is the * 64-bit SYSTIM register overflows more quickly. This is dealt with * by simply reading the clock before it overflows. * * Clock ns bits Overflows after * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours */ #define E1000_SYSTIM_OVERFLOW_PERIOD … #define E1000_MAX_82574_SYSTIM_REREADS … #define E1000_82574_SYSTIM_EPSILON … /* hardware capability, feature, and workaround flags */ #define FLAG_HAS_AMT … #define FLAG_HAS_FLASH … #define FLAG_HAS_HW_VLAN_FILTER … #define FLAG_HAS_WOL … /* reserved BIT(4) */ #define FLAG_HAS_CTRLEXT_ON_LOAD … #define FLAG_HAS_SWSM_ON_LOAD … #define FLAG_HAS_JUMBO_FRAMES … #define FLAG_READ_ONLY_NVM … #define FLAG_IS_ICH … #define FLAG_HAS_MSIX … #define FLAG_HAS_SMART_POWER_DOWN … #define FLAG_IS_QUAD_PORT_A … #define FLAG_IS_QUAD_PORT … #define FLAG_HAS_HW_TIMESTAMP … #define FLAG_APME_IN_WUC … #define FLAG_APME_IN_CTRL3 … #define FLAG_APME_CHECK_PORT_B … #define FLAG_DISABLE_FC_PAUSE_TIME … #define FLAG_NO_WAKE_UCAST … #define FLAG_MNG_PT_ENABLED … #define FLAG_RESET_OVERWRITES_LAA … #define FLAG_TARC_SPEED_MODE_BIT … #define FLAG_TARC_SET_BIT_ZERO … #define FLAG_RX_NEEDS_RESTART … #define FLAG_LSC_GIG_SPEED_DROP … #define FLAG_SMART_POWER_DOWN … #define FLAG_MSI_ENABLED … /* reserved BIT(28) */ #define FLAG_TSO_FORCE … #define FLAG_RESTART_NOW … #define FLAG_MSI_TEST_FAILED … #define FLAG2_CRC_STRIPPING … #define FLAG2_HAS_PHY_WAKEUP … #define FLAG2_IS_DISCARDING … #define FLAG2_DISABLE_ASPM_L1 … #define FLAG2_HAS_PHY_STATS … #define FLAG2_HAS_EEE … #define FLAG2_DMA_BURST … #define FLAG2_DISABLE_ASPM_L0S … #define FLAG2_DISABLE_AIM … #define FLAG2_CHECK_PHY_HANG … #define FLAG2_NO_DISABLE_RX … #define FLAG2_PCIM2PCI_ARBITER_WA … #define FLAG2_DFLT_CRC_STRIPPING … #define FLAG2_CHECK_RX_HWTSTAMP … #define FLAG2_CHECK_SYSTIM_OVERFLOW … #define FLAG2_ENABLE_S0IX_FLOWS … #define E1000_RX_DESC_PS(R, i) … #define E1000_RX_DESC_EXT(R, i) … #define E1000_GET_DESC(R, i, type) … #define E1000_TX_DESC(R, i) … #define E1000_CONTEXT_DESC(R, i) … enum e1000_state_t { … }; enum latency_range { … }; extern char e1000e_driver_name[]; void e1000e_check_options(struct e1000_adapter *adapter); void e1000e_set_ethtool_ops(struct net_device *netdev); int e1000e_open(struct net_device *netdev); int e1000e_close(struct net_device *netdev); void e1000e_up(struct e1000_adapter *adapter); void e1000e_down(struct e1000_adapter *adapter, bool reset); void e1000e_reinit_locked(struct e1000_adapter *adapter); void e1000e_reset(struct e1000_adapter *adapter); void e1000e_power_up_phy(struct e1000_adapter *adapter); int e1000e_setup_rx_resources(struct e1000_ring *ring); int e1000e_setup_tx_resources(struct e1000_ring *ring); void e1000e_free_rx_resources(struct e1000_ring *ring); void e1000e_free_tx_resources(struct e1000_ring *ring); void e1000e_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats); void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); void e1000e_get_hw_control(struct e1000_adapter *adapter); void e1000e_release_hw_control(struct e1000_adapter *adapter); void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); extern unsigned int copybreak; extern const struct e1000_info e1000_82571_info; extern const struct e1000_info e1000_82572_info; extern const struct e1000_info e1000_82573_info; extern const struct e1000_info e1000_82574_info; extern const struct e1000_info e1000_82583_info; extern const struct e1000_info e1000_ich8_info; extern const struct e1000_info e1000_ich9_info; extern const struct e1000_info e1000_ich10_info; extern const struct e1000_info e1000_pch_info; extern const struct e1000_info e1000_pch2_info; extern const struct e1000_info e1000_pch_lpt_info; extern const struct e1000_info e1000_pch_spt_info; extern const struct e1000_info e1000_pch_cnp_info; extern const struct e1000_info e1000_pch_tgp_info; extern const struct e1000_info e1000_pch_adp_info; extern const struct e1000_info e1000_pch_mtp_info; extern const struct e1000_info e1000_es2_info; void e1000e_ptp_init(struct e1000_adapter *adapter); void e1000e_ptp_remove(struct e1000_adapter *adapter); u64 e1000e_read_systim(struct e1000_adapter *adapter, struct ptp_system_timestamp *sts); static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) { … } static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) { … } static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) { … } static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) { … } static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) { … } void e1000e_reload_nvm_generic(struct e1000_hw *hw); static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) { … } static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) { … } static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) { … } static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) { … } static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) { … } static inline s32 e1000_get_phy_info(struct e1000_hw *hw) { … } static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) { … } #define er32(reg) … void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); #define ew32(reg, val) … #define e1e_flush() … #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) … #define E1000_READ_REG_ARRAY(a, reg, offset) … #endif /* _E1000_H_ */
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