/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 2007 - 2018 Intel Corporation. */ #ifndef _E1000_PHY_H_ #define _E1000_PHY_H_ enum e1000_ms_type { … }; enum e1000_smart_speed { … }; s32 igb_check_downshift(struct e1000_hw *hw); s32 igb_check_reset_block(struct e1000_hw *hw); s32 igb_copper_link_setup_igp(struct e1000_hw *hw); s32 igb_copper_link_setup_m88(struct e1000_hw *hw); s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw); s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw); s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw); s32 igb_get_cable_length_m88(struct e1000_hw *hw); s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw); s32 igb_get_cable_length_igp_2(struct e1000_hw *hw); s32 igb_get_phy_id(struct e1000_hw *hw); s32 igb_get_phy_info_igp(struct e1000_hw *hw); s32 igb_get_phy_info_m88(struct e1000_hw *hw); s32 igb_phy_sw_reset(struct e1000_hw *hw); s32 igb_phy_hw_reset(struct e1000_hw *hw); s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active); s32 igb_setup_copper_link(struct e1000_hw *hw); s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, u32 usec_interval, bool *success); void igb_power_up_phy_copper(struct e1000_hw *hw); void igb_power_down_phy_copper(struct e1000_hw *hw); s32 igb_phy_init_script_igp3(struct e1000_hw *hw); s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw); s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw); s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); s32 igb_copper_link_setup_82580(struct e1000_hw *hw); s32 igb_get_phy_info_82580(struct e1000_hw *hw); s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw); s32 igb_get_cable_length_82580(struct e1000_hw *hw); s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data); s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data); s32 igb_check_polarity_m88(struct e1000_hw *hw); /* IGP01E1000 Specific Registers */ #define IGP01E1000_PHY_PORT_CONFIG … #define IGP01E1000_PHY_PORT_STATUS … #define IGP01E1000_PHY_PORT_CTRL … #define IGP01E1000_PHY_LINK_HEALTH … #define IGP02E1000_PHY_POWER_MGMT … #define IGP01E1000_PHY_PAGE_SELECT … #define IGP01E1000_PHY_PCS_INIT_REG … #define IGP01E1000_PHY_POLARITY_MASK … #define IGP01E1000_PSCR_AUTO_MDIX … #define IGP01E1000_PSCR_FORCE_MDI_MDIX … #define IGP01E1000_PSCFR_SMART_SPEED … #define I82580_ADDR_REG … #define I82580_CFG_REG … #define I82580_CFG_ASSERT_CRS_ON_TX … #define I82580_CFG_ENABLE_DOWNSHIFT … #define I82580_CTRL_REG … #define I82580_CTRL_DOWNSHIFT_MASK … /* 82580 specific PHY registers */ #define I82580_PHY_CTRL_2 … #define I82580_PHY_LBK_CTRL … #define I82580_PHY_STATUS_2 … #define I82580_PHY_DIAG_STATUS … /* I82580 PHY Status 2 */ #define I82580_PHY_STATUS2_REV_POLARITY … #define I82580_PHY_STATUS2_MDIX … #define I82580_PHY_STATUS2_SPEED_MASK … #define I82580_PHY_STATUS2_SPEED_1000MBPS … #define I82580_PHY_STATUS2_SPEED_100MBPS … /* I82580 PHY Control 2 */ #define I82580_PHY_CTRL2_MANUAL_MDIX … #define I82580_PHY_CTRL2_AUTO_MDI_MDIX … #define I82580_PHY_CTRL2_MDIX_CFG_MASK … /* I82580 PHY Diagnostics Status */ #define I82580_DSTATUS_CABLE_LENGTH … #define I82580_DSTATUS_CABLE_LENGTH_SHIFT … /* 82580 PHY Power Management */ #define E1000_82580_PHY_POWER_MGMT … #define E1000_82580_PM_SPD … #define E1000_82580_PM_D0_LPLU … #define E1000_82580_PM_D3_LPLU … #define E1000_82580_PM_GO_LINKD … /* Enable flexible speed on link-up */ #define IGP02E1000_PM_D0_LPLU … #define IGP02E1000_PM_D3_LPLU … #define IGP01E1000_PLHR_SS_DOWNGRADE … #define IGP01E1000_PSSR_POLARITY_REVERSED … #define IGP01E1000_PSSR_MDIX … #define IGP01E1000_PSSR_SPEED_MASK … #define IGP01E1000_PSSR_SPEED_1000MBPS … #define IGP02E1000_PHY_CHANNEL_NUM … #define IGP02E1000_PHY_AGC_A … #define IGP02E1000_PHY_AGC_B … #define IGP02E1000_PHY_AGC_C … #define IGP02E1000_PHY_AGC_D … #define IGP02E1000_AGC_LENGTH_SHIFT … #define IGP02E1000_AGC_LENGTH_MASK … #define IGP02E1000_AGC_RANGE … #define E1000_CABLE_LENGTH_UNDEFINED … /* SFP modules ID memory locations */ #define E1000_SFF_IDENTIFIER_OFFSET … #define E1000_SFF_IDENTIFIER_SFF … #define E1000_SFF_IDENTIFIER_SFP … #define E1000_SFF_ETH_FLAGS_OFFSET … /* Flags for SFP modules compatible with ETH up to 1Gb */ struct e1000_sfp_flags { … }; #endif
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