// SPDX-License-Identifier: GPL-2.0 /* Copyright(c) 2007 - 2018 Intel Corporation. */ /* e1000_82575 * e1000_82576 */ #define pr_fmt(fmt) … #include <linux/types.h> #include <linux/if_ether.h> #include <linux/i2c.h> #include "e1000_mac.h" #include "e1000_82575.h" #include "e1000_i210.h" #include "igb.h" static s32 igb_get_invariants_82575(struct e1000_hw *); static s32 igb_acquire_phy_82575(struct e1000_hw *); static void igb_release_phy_82575(struct e1000_hw *); static s32 igb_acquire_nvm_82575(struct e1000_hw *); static void igb_release_nvm_82575(struct e1000_hw *); static s32 igb_check_for_link_82575(struct e1000_hw *); static s32 igb_get_cfg_done_82575(struct e1000_hw *); static s32 igb_init_hw_82575(struct e1000_hw *); static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); static s32 igb_reset_hw_82575(struct e1000_hw *); static s32 igb_reset_hw_82580(struct e1000_hw *); static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool); static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool); static s32 igb_setup_copper_link_82575(struct e1000_hw *); static s32 igb_setup_serdes_link_82575(struct e1000_hw *); static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); static void igb_clear_hw_cntrs_82575(struct e1000_hw *); static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, u16 *); static s32 igb_get_phy_id_82575(struct e1000_hw *); static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); static bool igb_sgmii_active_82575(struct e1000_hw *); static s32 igb_reset_init_script_82575(struct e1000_hw *); static s32 igb_read_mac_addr_82575(struct e1000_hw *); static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw); static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw); static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw); static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw); static const u16 e1000_82580_rxpbs_table[] = …; /* Due to a hw errata, if the host tries to configure the VFTA register * while performing queries from the BMC or DMA, then the VFTA in some * cases won't be written. */ /** * igb_write_vfta_i350 - Write value to VLAN filter table * @hw: pointer to the HW structure * @offset: register offset in VLAN filter table * @value: register value written to VLAN filter table * * Writes value at the given offset in the register array which stores * the VLAN filter table. **/ static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) { … } /** * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO * @hw: pointer to the HW structure * * Called to determine if the I2C pins are being used for I2C or as an * external MDIO interface since the two options are mutually exclusive. **/ static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) { … } /** * igb_check_for_link_media_swap - Check which M88E1112 interface linked * @hw: pointer to the HW structure * * Poll the M88E1112 interfaces to see which interface achieved link. */ static s32 igb_check_for_link_media_swap(struct e1000_hw *hw) { … } /** * igb_init_phy_params_82575 - Init PHY func ptrs. * @hw: pointer to the HW structure **/ static s32 igb_init_phy_params_82575(struct e1000_hw *hw) { … } /** * igb_init_nvm_params_82575 - Init NVM func ptrs. * @hw: pointer to the HW structure **/ static s32 igb_init_nvm_params_82575(struct e1000_hw *hw) { … } /** * igb_init_mac_params_82575 - Init MAC func ptrs. * @hw: pointer to the HW structure **/ static s32 igb_init_mac_params_82575(struct e1000_hw *hw) { … } /** * igb_set_sfp_media_type_82575 - derives SFP module media type. * @hw: pointer to the HW structure * * The media type is chosen based on SFP module. * compatibility flags retrieved from SFP ID EEPROM. **/ static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw) { … } static s32 igb_get_invariants_82575(struct e1000_hw *hw) { … } /** * igb_acquire_phy_82575 - Acquire rights to access PHY * @hw: pointer to the HW structure * * Acquire access rights to the correct PHY. This is a * function pointer entry point called by the api module. **/ static s32 igb_acquire_phy_82575(struct e1000_hw *hw) { … } /** * igb_release_phy_82575 - Release rights to access PHY * @hw: pointer to the HW structure * * A wrapper to release access rights to the correct PHY. This is a * function pointer entry point called by the api module. **/ static void igb_release_phy_82575(struct e1000_hw *hw) { … } /** * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii * @hw: pointer to the HW structure * @offset: register offset to be read * @data: pointer to the read data * * Reads the PHY register at offset using the serial gigabit media independent * interface and stores the retrieved information in data. **/ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 *data) { … } /** * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write at register offset * * Writes the data to PHY register at the offset using the serial gigabit * media independent interface. **/ static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 data) { … } /** * igb_get_phy_id_82575 - Retrieve PHY addr and id * @hw: pointer to the HW structure * * Retrieves the PHY address and ID for both PHY's which do and do not use * sgmi interface. **/ static s32 igb_get_phy_id_82575(struct e1000_hw *hw) { … } /** * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset * @hw: pointer to the HW structure * * Resets the PHY using the serial gigabit media independent interface. **/ static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) { … } /** * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state * @hw: pointer to the HW structure * @active: true to enable LPLU, false to disable * * Sets the LPLU D0 state according to the active flag. When * activating LPLU this function also disables smart speed * and vice versa. LPLU will not be activated unless the * device autonegotiation advertisement meets standards of * either 10 or 10/100 or 10/100/1000 at all duplexes. * This is a function pointer entry point only called by * PHY setup routines. **/ static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) { … } /** * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state * @hw: pointer to the HW structure * @active: true to enable LPLU, false to disable * * Sets the LPLU D0 state according to the active flag. When * activating LPLU this function also disables smart speed * and vice versa. LPLU will not be activated unless the * device autonegotiation advertisement meets standards of * either 10 or 10/100 or 10/100/1000 at all duplexes. * This is a function pointer entry point only called by * PHY setup routines. **/ static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) { … } /** * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3 * @hw: pointer to the HW structure * @active: boolean used to enable/disable lplu * * Success returns 0, Failure returns 1 * * The low power link up (lplu) state is set to the power management level D3 * and SmartSpeed is disabled when active is true, else clear lplu for D3 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU * is used during Dx states where the power conservation is most important. * During driver activity, SmartSpeed should be enabled so performance is * maintained. **/ static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) { … } /** * igb_acquire_nvm_82575 - Request for access to EEPROM * @hw: pointer to the HW structure * * Acquire the necessary semaphores for exclusive access to the EEPROM. * Set the EEPROM access request bit and wait for EEPROM access grant bit. * Return successful if access grant bit set, else clear the request for * EEPROM access and return -E1000_ERR_NVM (-1). **/ static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) { … } /** * igb_release_nvm_82575 - Release exclusive access to EEPROM * @hw: pointer to the HW structure * * Stop any current commands to the EEPROM and clear the EEPROM request bit, * then release the semaphores acquired. **/ static void igb_release_nvm_82575(struct e1000_hw *hw) { … } /** * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore * @hw: pointer to the HW structure * @mask: specifies which semaphore to acquire * * Acquire the SW/FW semaphore to access the PHY or NVM. The mask * will also specify which port we're acquiring the lock for. **/ static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) { … } /** * igb_release_swfw_sync_82575 - Release SW/FW semaphore * @hw: pointer to the HW structure * @mask: specifies which semaphore to acquire * * Release the SW/FW semaphore used to access the PHY or NVM. The mask * will also specify which port we're releasing the lock for. **/ static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) { … } /** * igb_get_cfg_done_82575 - Read config done bit * @hw: pointer to the HW structure * * Read the management control register for the config done bit for * completion status. NOTE: silicon which is EEPROM-less will fail trying * to read the config done bit, so an error is *ONLY* logged and returns * 0. If we were to return with error, EEPROM-less silicon * would not be able to be reset or change link. **/ static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) { … } /** * igb_get_link_up_info_82575 - Get link speed/duplex info * @hw: pointer to the HW structure * @speed: stores the current speed * @duplex: stores the current duplex * * This is a wrapper function, if using the serial gigabit media independent * interface, use PCS to retrieve the link speed and duplex information. * Otherwise, use the generic function to get the link speed and duplex info. **/ static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, u16 *duplex) { … } /** * igb_check_for_link_82575 - Check for link * @hw: pointer to the HW structure * * If sgmii is enabled, then use the pcs register to determine link, otherwise * use the generic interface for determining link. **/ static s32 igb_check_for_link_82575(struct e1000_hw *hw) { … } /** * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown * @hw: pointer to the HW structure **/ void igb_power_up_serdes_link_82575(struct e1000_hw *hw) { … } /** * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex * @hw: pointer to the HW structure * @speed: stores the current speed * @duplex: stores the current duplex * * Using the physical coding sub-layer (PCS), retrieve the current speed and * duplex, then store the values in the pointers provided. **/ static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, u16 *duplex) { … } /** * igb_shutdown_serdes_link_82575 - Remove link during power down * @hw: pointer to the HW structure * * In the case of fiber serdes, shut down optics and PCS on driver unload * when management pass thru is not enabled. **/ void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) { … } /** * igb_reset_hw_82575 - Reset hardware * @hw: pointer to the HW structure * * This resets the hardware into a known state. This is a * function pointer entry point called by the api module. **/ static s32 igb_reset_hw_82575(struct e1000_hw *hw) { … } /** * igb_init_hw_82575 - Initialize hardware * @hw: pointer to the HW structure * * This inits the hardware readying it for operation. **/ static s32 igb_init_hw_82575(struct e1000_hw *hw) { … } /** * igb_setup_copper_link_82575 - Configure copper link settings * @hw: pointer to the HW structure * * Configures the link for auto-neg or forced speed and duplex. Then we check * for link, once link is established calls to configure collision distance * and flow control are called. **/ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) { … } /** * igb_setup_serdes_link_82575 - Setup link for serdes * @hw: pointer to the HW structure * * Configure the physical coding sub-layer (PCS) link. The PCS link is * used on copper connections where the serialized gigabit media independent * interface (sgmii), or serdes fiber is being used. Configures the link * for auto-negotiation or forces speed/duplex. **/ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) { … } /** * igb_sgmii_active_82575 - Return sgmii state * @hw: pointer to the HW structure * * 82575 silicon has a serialized gigabit media independent interface (sgmii) * which can be enabled for use in the embedded applications. Simply * return the current state of the sgmii interface. **/ static bool igb_sgmii_active_82575(struct e1000_hw *hw) { … } /** * igb_reset_init_script_82575 - Inits HW defaults after reset * @hw: pointer to the HW structure * * Inits recommended HW defaults after a reset when there is no EEPROM * detected. This is only for the 82575. **/ static s32 igb_reset_init_script_82575(struct e1000_hw *hw) { … } /** * igb_read_mac_addr_82575 - Read device MAC address * @hw: pointer to the HW structure **/ static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) { … } /** * igb_power_down_phy_copper_82575 - Remove link during PHY power down * @hw: pointer to the HW structure * * In the case of a PHY power down to save power, or to turn off link during a * driver unload, or wake on lan is not enabled, remove the link. **/ void igb_power_down_phy_copper_82575(struct e1000_hw *hw) { … } /** * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters * @hw: pointer to the HW structure * * Clears the hardware counters by reading the counter registers. **/ static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) { … } /** * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable * @hw: pointer to the HW structure * * After rx enable if manageability is enabled then there is likely some * bad data at the start of the fifo and possibly in the DMA fifo. This * function clears the fifos and flushes any packets that came in as rx was * being enabled. **/ void igb_rx_fifo_flush_82575(struct e1000_hw *hw) { … } /** * igb_set_pcie_completion_timeout - set pci-e completion timeout * @hw: pointer to the HW structure * * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, * however the hardware default for these parts is 500us to 1ms which is less * than the 10ms recommended by the pci-e spec. To address this we need to * increase the value to either 10ms to 200ms for capability version 1 config, * or 16ms to 55ms for version 2. **/ static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) { … } /** * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing * @hw: pointer to the hardware struct * @enable: state to enter, either enabled or disabled * @pf: Physical Function pool - do not set anti-spoofing for the PF * * enables/disables L2 switch anti-spoofing functionality. **/ void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) { … } /** * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback * @hw: pointer to the hardware struct * @enable: state to enter, either enabled or disabled * * enables/disables L2 switch loopback functionality. **/ void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) { … } /** * igb_vmdq_set_replication_pf - enable or disable vmdq replication * @hw: pointer to the hardware struct * @enable: state to enter, either enabled or disabled * * enables/disables replication of packets across multiple pools. **/ void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) { … } /** * igb_read_phy_reg_82580 - Read 82580 MDI control register * @hw: pointer to the HW structure * @offset: register offset to be read * @data: pointer to the read data * * Reads the MDI control register in the PHY at offset and stores the * information read to data. **/ s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) { … } /** * igb_write_phy_reg_82580 - Write 82580 MDI control register * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write to register at offset * * Writes data to MDI control register in the PHY at offset. **/ s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) { … } /** * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits * @hw: pointer to the HW structure * * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on * the values found in the EEPROM. This addresses an issue in which these * bits are not restored from EEPROM after reset. **/ static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) { … } /** * igb_reset_hw_82580 - Reset hardware * @hw: pointer to the HW structure * * This resets function or entire device (all ports, etc.) * to a known state. **/ static s32 igb_reset_hw_82580(struct e1000_hw *hw) { … } /** * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size * @data: data received by reading RXPBS register * * The 82580 uses a table based approach for packet buffer allocation sizes. * This function converts the retrieved value into the correct table value * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 * 0x0 36 72 144 1 2 4 8 16 * 0x8 35 70 140 rsv rsv rsv rsv rsv */ u16 igb_rxpbs_adjust_82580(u32 data) { … } /** * igb_validate_nvm_checksum_with_offset - Validate EEPROM * checksum * @hw: pointer to the HW structure * @offset: offset in words of the checksum protected region * * Calculates the EEPROM checksum by reading/adding each word of the EEPROM * and then verifies that the sum of the EEPROM is equal to 0xBABA. **/ static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) { … } /** * igb_update_nvm_checksum_with_offset - Update EEPROM * checksum * @hw: pointer to the HW structure * @offset: offset in words of the checksum protected region * * Updates the EEPROM checksum by reading/adding each word of the EEPROM * up to the checksum. Then calculates the EEPROM checksum and writes the * value to the EEPROM. **/ static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) { … } /** * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum * @hw: pointer to the HW structure * * Calculates the EEPROM section checksum by reading/adding each word of * the EEPROM and then verifies that the sum of the EEPROM is * equal to 0xBABA. **/ static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) { … } /** * igb_update_nvm_checksum_82580 - Update EEPROM checksum * @hw: pointer to the HW structure * * Updates the EEPROM section checksums for all 4 ports by reading/adding * each word of the EEPROM up to the checksum. Then calculates the EEPROM * checksum and writes the value to the EEPROM. **/ static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) { … } /** * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum * @hw: pointer to the HW structure * * Calculates the EEPROM section checksum by reading/adding each word of * the EEPROM and then verifies that the sum of the EEPROM is * equal to 0xBABA. **/ static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) { … } /** * igb_update_nvm_checksum_i350 - Update EEPROM checksum * @hw: pointer to the HW structure * * Updates the EEPROM section checksums for all 4 ports by reading/adding * each word of the EEPROM up to the checksum. Then calculates the EEPROM * checksum and writes the value to the EEPROM. **/ static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) { … } /** * __igb_access_emi_reg - Read/write EMI register * @hw: pointer to the HW structure * @address: EMI address to program * @data: pointer to value to read/write from/to the EMI address * @read: boolean flag to indicate read or write **/ static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address, u16 *data, bool read) { … } /** * igb_read_emi_reg - Read Extended Management Interface register * @hw: pointer to the HW structure * @addr: EMI address to program * @data: value to be read from the EMI address **/ s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) { … } /** * igb_set_eee_i350 - Enable/disable EEE support * @hw: pointer to the HW structure * @adv1G: boolean flag enabling 1G EEE advertisement * @adv100M: boolean flag enabling 100M EEE advertisement * * Enable/disable EEE based on setting in dev_spec structure. * **/ s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) { … } /** * igb_set_eee_i354 - Enable/disable EEE support * @hw: pointer to the HW structure * @adv1G: boolean flag enabling 1G EEE advertisement * @adv100M: boolean flag enabling 100M EEE advertisement * * Enable/disable EEE legacy mode based on setting in dev_spec structure. * **/ s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) { … } /** * igb_get_eee_status_i354 - Get EEE status * @hw: pointer to the HW structure * @status: EEE status * * Get EEE status by guessing based on whether Tx or Rx LPI indications have * been received. **/ s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status) { … } #ifdef CONFIG_IGB_HWMON static const u8 e1000_emc_temp_data[4] = …; static const u8 e1000_emc_therm_limit[4] = …; /** * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data * @hw: pointer to hardware structure * * Updates the temperatures in mac.thermal_sensor_data **/ static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw) { … } /** * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds * @hw: pointer to hardware structure * * Sets the thermal sensor thresholds according to the NVM map * and save off the threshold and location values into mac.thermal_sensor_data **/ static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw) { … } #endif static struct e1000_mac_operations e1000_mac_ops_82575 = …; static const struct e1000_phy_operations e1000_phy_ops_82575 = …; static struct e1000_nvm_operations e1000_nvm_ops_82575 = …; const struct e1000_info e1000_82575_info = …;
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