/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018 Intel Corporation */ #ifndef _IGC_DEFINES_H_ #define _IGC_DEFINES_H_ #include <linux/bitfield.h> /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ #define REQ_TX_DESCRIPTOR_MULTIPLE … #define REQ_RX_DESCRIPTOR_MULTIPLE … #define IGC_CTRL_EXT_SDP2_DIR … #define IGC_CTRL_EXT_SDP3_DIR … #define IGC_CTRL_EXT_DRV_LOAD … /* Definitions for power management and wakeup registers */ /* Wake Up Control */ #define IGC_WUC_PME_EN … /* Wake Up Filter Control */ #define IGC_WUFC_LNKC … #define IGC_WUFC_MAG … #define IGC_WUFC_EX … #define IGC_WUFC_MC … #define IGC_WUFC_BC … #define IGC_WUFC_FLEX_HQ … #define IGC_WUFC_FLX0 … #define IGC_WUFC_FLX1 … #define IGC_WUFC_FLX2 … #define IGC_WUFC_FLX3 … #define IGC_WUFC_FLX4 … #define IGC_WUFC_FLX5 … #define IGC_WUFC_FLX6 … #define IGC_WUFC_FLX7 … #define IGC_WUFC_FILTER_MASK … #define IGC_CTRL_ADVD3WUC … /* Wake Up Status */ #define IGC_WUS_EX … #define IGC_WUS_ARPD … #define IGC_WUS_IPV4 … #define IGC_WUS_IPV6 … #define IGC_WUS_NSD … /* Packet types that are enabled for wake packet delivery */ #define WAKE_PKT_WUS … /* Wake Up Packet Length */ #define IGC_WUPL_MASK … /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */ #define IGC_WUPM_BYTES … /* Wakeup Filter Control Extended */ #define IGC_WUFC_EXT_FLX8 … #define IGC_WUFC_EXT_FLX9 … #define IGC_WUFC_EXT_FLX10 … #define IGC_WUFC_EXT_FLX11 … #define IGC_WUFC_EXT_FLX12 … #define IGC_WUFC_EXT_FLX13 … #define IGC_WUFC_EXT_FLX14 … #define IGC_WUFC_EXT_FLX15 … #define IGC_WUFC_EXT_FLX16 … #define IGC_WUFC_EXT_FLX17 … #define IGC_WUFC_EXT_FLX18 … #define IGC_WUFC_EXT_FLX19 … #define IGC_WUFC_EXT_FLX20 … #define IGC_WUFC_EXT_FLX21 … #define IGC_WUFC_EXT_FLX22 … #define IGC_WUFC_EXT_FLX23 … #define IGC_WUFC_EXT_FLX24 … #define IGC_WUFC_EXT_FLX25 … #define IGC_WUFC_EXT_FLX26 … #define IGC_WUFC_EXT_FLX27 … #define IGC_WUFC_EXT_FLX28 … #define IGC_WUFC_EXT_FLX29 … #define IGC_WUFC_EXT_FLX30 … #define IGC_WUFC_EXT_FLX31 … #define IGC_WUFC_EXT_FILTER_MASK … /* Loop limit on how long we wait for auto-negotiation to complete */ #define COPPER_LINK_UP_LIMIT … #define PHY_AUTO_NEG_LIMIT … /* Number of 100 microseconds we wait for PCI Express master disable */ #define MASTER_DISABLE_TIMEOUT … /*Blocks new Master requests */ #define IGC_CTRL_GIO_MASTER_DISABLE … /* Status of Master requests. */ #define IGC_STATUS_GIO_MASTER_ENABLE … /* Receive Address * Number of high/low register pairs in the RAR. The RAR (Receive Address * Registers) holds the directed and multicast addresses that we monitor. * Technically, we have 16 spots. However, we reserve one of these spots * (RAR[15]) for our directed address used by controllers with * manageability enabled, allowing us room for 15 multicast addresses. */ #define IGC_RAH_RAH_MASK … #define IGC_RAH_ASEL_MASK … #define IGC_RAH_ASEL_SRC_ADDR … #define IGC_RAH_QSEL_MASK … #define IGC_RAH_QSEL_SHIFT … #define IGC_RAH_QSEL_ENABLE … #define IGC_RAH_AV … #define IGC_RAL_MAC_ADDR_LEN … #define IGC_RAH_MAC_ADDR_LEN … /* Error Codes */ #define IGC_SUCCESS … #define IGC_ERR_NVM … #define IGC_ERR_PHY … #define IGC_ERR_CONFIG … #define IGC_ERR_PARAM … #define IGC_ERR_MAC_INIT … #define IGC_ERR_RESET … #define IGC_ERR_MASTER_REQUESTS_PENDING … #define IGC_ERR_BLK_PHY_RESET … #define IGC_ERR_SWFW_SYNC … /* Device Control */ #define IGC_CTRL_RST … #define IGC_CTRL_PHY_RST … #define IGC_CTRL_SLU … #define IGC_CTRL_FRCSPD … #define IGC_CTRL_FRCDPX … #define IGC_CTRL_VME … #define IGC_CTRL_RFCE … #define IGC_CTRL_TFCE … #define IGC_CTRL_SDP0_DIR … #define IGC_CTRL_SDP1_DIR … /* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */ #define MAX_JUMBO_FRAME_SIZE … /* PBA constants */ #define IGC_PBA_34K … /* SW Semaphore Register */ #define IGC_SWSM_SMBI … #define IGC_SWSM_SWESMBI … /* SWFW_SYNC Definitions */ #define IGC_SWFW_EEP_SM … #define IGC_SWFW_PHY0_SM … /* Autoneg Advertisement Register */ #define NWAY_AR_10T_HD_CAPS … #define NWAY_AR_10T_FD_CAPS … #define NWAY_AR_100TX_HD_CAPS … #define NWAY_AR_100TX_FD_CAPS … #define NWAY_AR_PAUSE … #define NWAY_AR_ASM_DIR … /* Link Partner Ability Register (Base Page) */ #define NWAY_LPAR_PAUSE … #define NWAY_LPAR_ASM_DIR … /* 1000BASE-T Control Register */ #define CR_1000T_HD_CAPS … #define CR_1000T_FD_CAPS … /* 1000BASE-T Status Register */ #define SR_1000T_REMOTE_RX_STATUS … /* PHY GPY 211 registers */ #define STANDARD_AN_REG_MASK … #define MMD_DEVADDR_SHIFT … #define CR_2500T_FD_CAPS … /* NVM Control */ /* Number of milliseconds for NVM auto read done after MAC reset. */ #define AUTO_READ_DONE_TIMEOUT … #define IGC_EECD_AUTO_RD … #define IGC_EECD_REQ … #define IGC_EECD_GNT … /* NVM Addressing bits based on type 0=small, 1=large */ #define IGC_EECD_ADDR_BITS … #define IGC_NVM_GRANT_ATTEMPTS … #define IGC_EECD_SIZE_EX_MASK … #define IGC_EECD_SIZE_EX_SHIFT … #define IGC_EECD_FLUPD_I225 … #define IGC_EECD_FLUDONE_I225 … #define IGC_EECD_FLASH_DETECTED_I225 … #define IGC_FLUDONE_ATTEMPTS … #define IGC_EERD_EEWR_MAX_COUNT … /* Offset to data in NVM read/write registers */ #define IGC_NVM_RW_REG_DATA … #define IGC_NVM_RW_REG_DONE … #define IGC_NVM_RW_REG_START … #define IGC_NVM_RW_ADDR_SHIFT … #define IGC_NVM_POLL_READ … #define IGC_NVM_DEV_STARTER … /* NVM Word Offsets */ #define NVM_CHECKSUM_REG … /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ #define NVM_SUM … #define NVM_WORD_SIZE_BASE_SHIFT … /* Collision related configuration parameters */ #define IGC_COLLISION_THRESHOLD … #define IGC_CT_SHIFT … #define IGC_COLLISION_DISTANCE … #define IGC_COLD_SHIFT … /* Device Status */ #define IGC_STATUS_FD … #define IGC_STATUS_LU … #define IGC_STATUS_FUNC_MASK … #define IGC_STATUS_FUNC_SHIFT … #define IGC_STATUS_TXOFF … #define IGC_STATUS_SPEED_100 … #define IGC_STATUS_SPEED_1000 … #define IGC_STATUS_SPEED_2500 … #define SPEED_10 … #define SPEED_100 … #define SPEED_1000 … #define SPEED_2500 … #define HALF_DUPLEX … #define FULL_DUPLEX … /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */ #define ADVERTISE_10_HALF … #define ADVERTISE_10_FULL … #define ADVERTISE_100_HALF … #define ADVERTISE_100_FULL … #define ADVERTISE_1000_HALF … #define ADVERTISE_1000_FULL … #define ADVERTISE_2500_HALF … #define ADVERTISE_2500_FULL … #define IGC_ALL_SPEED_DUPLEX_2500 … #define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 … /* Interrupt Cause Read */ #define IGC_ICR_TXDW … #define IGC_ICR_TXQE … #define IGC_ICR_LSC … #define IGC_ICR_RXSEQ … #define IGC_ICR_RXDMT0 … #define IGC_ICR_RXO … #define IGC_ICR_RXT0 … #define IGC_ICR_TS … #define IGC_ICR_DRSTA … /* If this bit asserted, the driver should claim the interrupt */ #define IGC_ICR_INT_ASSERTED … #define IGC_ICS_RXT0 … #define IMS_ENABLE_MASK … /* Interrupt Mask Set */ #define IGC_IMS_TXDW … #define IGC_IMS_RXSEQ … #define IGC_IMS_LSC … #define IGC_IMS_DOUTSYNC … #define IGC_IMS_DRSTA … #define IGC_IMS_RXT0 … #define IGC_IMS_RXDMT0 … #define IGC_IMS_TS … #define IGC_QVECTOR_MASK … #define IGC_ITR_VAL_MASK … /* Interrupt Cause Set */ #define IGC_ICS_LSC … #define IGC_ICS_RXDMT0 … #define IGC_ICR_DOUTSYNC … #define IGC_EITR_CNT_IGNR … #define IGC_IVAR_VALID … #define IGC_GPIE_NSICR … #define IGC_GPIE_MSIX_MODE … #define IGC_GPIE_EIAME … #define IGC_GPIE_PBA … /* Receive Descriptor bit definitions */ #define IGC_RXD_STAT_DD … /* Transmit Descriptor bit definitions */ #define IGC_TXD_DTYP_D … #define IGC_TXD_DTYP_C … #define IGC_TXD_POPTS_IXSM … #define IGC_TXD_POPTS_TXSM … #define IGC_TXD_CMD_EOP … #define IGC_TXD_CMD_IC … #define IGC_TXD_CMD_DEXT … #define IGC_TXD_CMD_VLE … #define IGC_TXD_STAT_DD … #define IGC_TXD_CMD_TCP … #define IGC_TXD_CMD_IP … #define IGC_TXD_CMD_TSE … #define IGC_TXD_EXTCMD_TSTAMP … #define IGC_TXD_PTP2_TIMER_1 … /* IPSec Encrypt Enable */ #define IGC_ADVTXD_L4LEN_SHIFT … #define IGC_ADVTXD_MSS_SHIFT … #define IGC_ADVTXD_TSN_CNTX_FIRST … /* Transmit Control */ #define IGC_TCTL_EN … #define IGC_TCTL_PSP … #define IGC_TCTL_CT … #define IGC_TCTL_COLD … #define IGC_TCTL_RTLC … /* Flow Control Constants */ #define FLOW_CONTROL_ADDRESS_LOW … #define FLOW_CONTROL_ADDRESS_HIGH … #define FLOW_CONTROL_TYPE … /* Enable XON frame transmission */ #define IGC_FCRTL_XONE … /* Management Control */ #define IGC_MANC_RCV_TCO_EN … #define IGC_MANC_BLK_PHY_RST_ON_IDE … /* Receive Control */ #define IGC_RCTL_RST … #define IGC_RCTL_EN … #define IGC_RCTL_SBP … #define IGC_RCTL_UPE … #define IGC_RCTL_MPE … #define IGC_RCTL_LPE … #define IGC_RCTL_LBM_MAC … #define IGC_RCTL_LBM_TCVR … #define IGC_RCTL_RDMTS_HALF … #define IGC_RCTL_BAM … /* Split Replication Receive Control */ #define IGC_SRRCTL_TIMESTAMP … #define IGC_SRRCTL_TIMER1SEL(timer) … #define IGC_SRRCTL_TIMER0SEL(timer) … /* Receive Descriptor bit definitions */ #define IGC_RXD_STAT_EOP … #define IGC_RXD_STAT_IXSM … #define IGC_RXD_STAT_UDPCS … #define IGC_RXD_STAT_TCPCS … #define IGC_RXD_STAT_VP … #define IGC_RXDEXT_STATERR_LB … /* Advanced Receive Descriptor bit definitions */ #define IGC_RXDADV_STAT_TSIP … #define IGC_RXDEXT_STATERR_L4E … #define IGC_RXDEXT_STATERR_IPE … #define IGC_RXDEXT_STATERR_RXE … #define IGC_MRQC_RSS_FIELD_IPV4_TCP … #define IGC_MRQC_RSS_FIELD_IPV4 … #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX … #define IGC_MRQC_RSS_FIELD_IPV6 … #define IGC_MRQC_RSS_FIELD_IPV6_TCP … /* Header split receive */ #define IGC_RFCTL_IPV6_EX_DIS … #define IGC_RFCTL_LEF … #define IGC_RCTL_SZ_256 … #define IGC_RCTL_MO_SHIFT … #define IGC_RCTL_CFIEN … #define IGC_RCTL_DPF … #define IGC_RCTL_PMCF … #define IGC_RCTL_SECRC … #define I225_RXPBSIZE_DEFAULT … #define I225_TXPBSIZE_DEFAULT … #define IGC_RXPBS_CFG_TS_EN … #define IGC_TXPBSIZE_TSN … #define IGC_DTXMXPKTSZ_TSN … #define IGC_DTXMXPKTSZ_DEFAULT … /* Retry Buffer Control */ #define IGC_RETX_CTL … #define IGC_RETX_CTL_WATERMARK_MASK … #define IGC_RETX_CTL_QBVFULLTH_SHIFT … #define IGC_RETX_CTL_QBVFULLEN … /* Transmit Scheduling Latency */ /* Latency between transmission scheduling (LaunchTime) and the time * the packet is transmitted to the network in nanosecond. */ #define IGC_TXOFFSET_SPEED_10 … #define IGC_TXOFFSET_SPEED_100 … #define IGC_TXOFFSET_SPEED_1000 … #define IGC_TXOFFSET_SPEED_2500 … /* Time Sync Interrupt Causes */ #define IGC_TSICR_SYS_WRAP … #define IGC_TSICR_TXTS … #define IGC_TSICR_TT0 … #define IGC_TSICR_TT1 … #define IGC_TSICR_AUTT0 … #define IGC_TSICR_AUTT1 … #define IGC_TSICR_INTERRUPTS … #define IGC_FTQF_VF_BP … #define IGC_FTQF_1588_TIME_STAMP … #define IGC_FTQF_MASK … #define IGC_FTQF_MASK_PROTO_BP … /* Time Sync Receive Control bit definitions */ #define IGC_TSYNCRXCTL_TYPE_MASK … #define IGC_TSYNCRXCTL_TYPE_L2_V2 … #define IGC_TSYNCRXCTL_TYPE_L4_V1 … #define IGC_TSYNCRXCTL_TYPE_L2_L4_V2 … #define IGC_TSYNCRXCTL_TYPE_ALL … #define IGC_TSYNCRXCTL_TYPE_EVENT_V2 … #define IGC_TSYNCRXCTL_ENABLED … #define IGC_TSYNCRXCTL_SYSCFI … #define IGC_TSYNCRXCTL_RXSYNSIG … /* Time Sync Receive Configuration */ #define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK … #define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE … #define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE … /* Immediate Interrupt Receive */ #define IGC_IMIR_CLEAR_MASK … #define IGC_IMIR_PORT_BYPASS … #define IGC_IMIR_PRIORITY_SHIFT … #define IGC_IMIREXT_CLEAR_MASK … /* Immediate Interrupt Receive Extended */ #define IGC_IMIREXT_CTRL_BP … #define IGC_IMIREXT_SIZE_BP … /* Time Sync Transmit Control bit definitions */ #define IGC_TSYNCTXCTL_TXTT_0 … #define IGC_TSYNCTXCTL_TXTT_1 … #define IGC_TSYNCTXCTL_TXTT_2 … #define IGC_TSYNCTXCTL_TXTT_3 … #define IGC_TSYNCTXCTL_ENABLED … #define IGC_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK … #define IGC_TSYNCTXCTL_SYNC_COMP_ERR … #define IGC_TSYNCTXCTL_SYNC_COMP … #define IGC_TSYNCTXCTL_START_SYNC … #define IGC_TSYNCTXCTL_TXSYNSIG … #define IGC_TSYNCTXCTL_TXTT_ANY … /* Timer selection bits */ #define IGC_AUX_IO_TIMER_SEL_SYSTIM0 … #define IGC_AUX_IO_TIMER_SEL_SYSTIM1 … #define IGC_AUX_IO_TIMER_SEL_SYSTIM2 … #define IGC_AUX_IO_TIMER_SEL_SYSTIM3 … #define IGC_TT_IO_TIMER_SEL_SYSTIM0 … #define IGC_TT_IO_TIMER_SEL_SYSTIM1 … #define IGC_TT_IO_TIMER_SEL_SYSTIM2 … #define IGC_TT_IO_TIMER_SEL_SYSTIM3 … /* TSAUXC Configuration Bits */ #define IGC_TSAUXC_EN_TT0 … #define IGC_TSAUXC_EN_TT1 … #define IGC_TSAUXC_EN_CLK0 … #define IGC_TSAUXC_ST0 … #define IGC_TSAUXC_EN_CLK1 … #define IGC_TSAUXC_ST1 … #define IGC_TSAUXC_EN_TS0 … #define IGC_TSAUXC_AUTT0 … #define IGC_TSAUXC_EN_TS1 … #define IGC_TSAUXC_AUTT1 … #define IGC_TSAUXC_PLSG … #define IGC_TSAUXC_DISABLE1 … #define IGC_TSAUXC_DISABLE2 … #define IGC_TSAUXC_DISABLE3 … #define IGC_TSAUXC_DIS_TS_CLEAR … #define IGC_TSAUXC_DISABLE0 … /* SDP Configuration Bits */ #define IGC_AUX0_SEL_SDP0 … #define IGC_AUX0_SEL_SDP1 … #define IGC_AUX0_SEL_SDP2 … #define IGC_AUX0_SEL_SDP3 … #define IGC_AUX0_TS_SDP_EN … #define IGC_AUX1_SEL_SDP0 … #define IGC_AUX1_SEL_SDP1 … #define IGC_AUX1_SEL_SDP2 … #define IGC_AUX1_SEL_SDP3 … #define IGC_AUX1_TS_SDP_EN … #define IGC_TS_SDP0_SEL_TT0 … #define IGC_TS_SDP0_SEL_TT1 … #define IGC_TS_SDP0_SEL_FC0 … #define IGC_TS_SDP0_SEL_FC1 … #define IGC_TS_SDP0_EN … #define IGC_TS_SDP1_SEL_TT0 … #define IGC_TS_SDP1_SEL_TT1 … #define IGC_TS_SDP1_SEL_FC0 … #define IGC_TS_SDP1_SEL_FC1 … #define IGC_TS_SDP1_EN … #define IGC_TS_SDP2_SEL_TT0 … #define IGC_TS_SDP2_SEL_TT1 … #define IGC_TS_SDP2_SEL_FC0 … #define IGC_TS_SDP2_SEL_FC1 … #define IGC_TS_SDP2_EN … #define IGC_TS_SDP3_SEL_TT0 … #define IGC_TS_SDP3_SEL_TT1 … #define IGC_TS_SDP3_SEL_FC0 … #define IGC_TS_SDP3_SEL_FC1 … #define IGC_TS_SDP3_EN … /* Transmit Scheduling */ #define IGC_TQAVCTRL_TRANSMIT_MODE_TSN … #define IGC_TQAVCTRL_ENHANCED_QAV … #define IGC_TQAVCTRL_FUTSCDDIS … #define IGC_TXQCTL_QUEUE_MODE_LAUNCHT … #define IGC_TXQCTL_STRICT_CYCLE … #define IGC_TXQCTL_STRICT_END … #define IGC_TXQCTL_QAV_SEL_MASK … #define IGC_TXQCTL_QAV_SEL_CBS0 … #define IGC_TXQCTL_QAV_SEL_CBS1 … #define IGC_TQAVCC_IDLESLOPE_MASK … #define IGC_TQAVCC_KEEP_CREDITS … #define IGC_MAX_SR_QUEUES … #define IGC_TXARB_TXQ_PRIO_0_MASK … #define IGC_TXARB_TXQ_PRIO_1_MASK … #define IGC_TXARB_TXQ_PRIO_2_MASK … #define IGC_TXARB_TXQ_PRIO_3_MASK … #define IGC_TXARB_TXQ_PRIO_0(x) … #define IGC_TXARB_TXQ_PRIO_1(x) … #define IGC_TXARB_TXQ_PRIO_2(x) … #define IGC_TXARB_TXQ_PRIO_3(x) … /* Receive Checksum Control */ #define IGC_RXCSUM_CRCOFL … #define IGC_RXCSUM_PCSD … /* PCIe PTM Control */ #define IGC_PTM_CTRL_START_NOW … #define IGC_PTM_CTRL_EN … #define IGC_PTM_CTRL_TRIG … #define IGC_PTM_CTRL_SHRT_CYC(usec) … #define IGC_PTM_CTRL_PTM_TO(usec) … #define IGC_PTM_SHORT_CYC_DEFAULT … #define IGC_PTM_CYC_TIME_DEFAULT … #define IGC_PTM_TIMEOUT_DEFAULT … /* PCIe Digital Delay */ #define IGC_PCIE_DIG_DELAY_DEFAULT … /* PCIe PHY Delay */ #define IGC_PCIE_PHY_DELAY_DEFAULT … #define IGC_TIMADJ_ADJUST_METH … /* PCIe PTM Status */ #define IGC_PTM_STAT_VALID … #define IGC_PTM_STAT_RET_ERR … #define IGC_PTM_STAT_BAD_PTM_RES … #define IGC_PTM_STAT_T4M1_OVFL … #define IGC_PTM_STAT_ADJUST_1ST … #define IGC_PTM_STAT_ADJUST_CYC … /* PCIe PTM Cycle Control */ #define IGC_PTM_CYCLE_CTRL_CYC_TIME(msec) … #define IGC_PTM_CYCLE_CTRL_AUTO_CYC_EN … /* GPY211 - I225 defines */ #define GPY_MMD_MASK … #define GPY_MMD_SHIFT … #define GPY_REG_MASK … #define IGC_MMDAC_FUNC_DATA … /* MAC definitions */ #define IGC_FACTPS_MNGCG … #define IGC_FWSM_MODE_MASK … #define IGC_FWSM_MODE_SHIFT … /* Management Control */ #define IGC_MANC_SMBUS_EN … #define IGC_MANC_ASF_EN … /* PHY */ #define PHY_REVISION_MASK … #define MAX_PHY_REG_ADDRESS … #define IGC_GEN_POLL_TIMEOUT … /* PHY Control Register */ #define MII_CR_RESTART_AUTO_NEG … #define MII_CR_POWER_DOWN … #define MII_CR_AUTO_NEG_EN … /* PHY Status Register */ #define MII_SR_LINK_STATUS … #define MII_SR_AUTONEG_COMPLETE … #define IGC_PHY_RST_COMP … /* PHY 1000 MII Register/Bit Definitions */ /* PHY Registers defined by IEEE */ #define PHY_CONTROL … #define PHY_STATUS … #define PHY_ID1 … #define PHY_ID2 … #define PHY_AUTONEG_ADV … #define PHY_LP_ABILITY … #define PHY_1000T_CTRL … #define PHY_1000T_STATUS … /* MDI Control */ #define IGC_MDIC_DATA_MASK … #define IGC_MDIC_REG_MASK … #define IGC_MDIC_REG_SHIFT … #define IGC_MDIC_PHY_MASK … #define IGC_MDIC_PHY_SHIFT … #define IGC_MDIC_OP_WRITE … #define IGC_MDIC_OP_READ … #define IGC_MDIC_READY … #define IGC_MDIC_ERROR … /* EEE Link Ability */ #define IGC_EEE_2500BT_MASK … #define IGC_EEE_1000BT_MASK … #define IGC_EEE_100BT_MASK … /* EEE Link-Partner Ability */ #define IGC_LP_EEE_2500BT_MASK … #define IGC_LP_EEE_1000BT_MASK … #define IGC_LP_EEE_100BT_MASK … #define IGC_N0_QUEUE … #define IGC_MAX_MAC_HDR_LEN … #define IGC_MAX_NETWORK_HDR_LEN … #define IGC_VLANPQF_QSEL(_n, q_idx) … #define IGC_VLANPQF_VALID(_n) … #define IGC_VLANPQF_QUEUE_MASK … #define IGC_ADVTXD_MACLEN_SHIFT … #define IGC_ADVTXD_TUCMD_IPV4 … #define IGC_ADVTXD_TUCMD_L4T_TCP … #define IGC_ADVTXD_TUCMD_L4T_SCTP … /* Maximum size of the MTA register table in all supported adapters */ #define MAX_MTA_REG … /* EEE defines */ #define IGC_IPCNFG_EEE_2_5G_AN … #define IGC_IPCNFG_EEE_1G_AN … #define IGC_IPCNFG_EEE_100M_AN … #define IGC_EEER_EEE_NEG … #define IGC_EEER_TX_LPI_EN … #define IGC_EEER_RX_LPI_EN … #define IGC_EEER_LPI_FC … #define IGC_EEE_SU_LPI_CLK_STP … /* LTR defines */ #define IGC_LTRC_EEEMS_EN … #define IGC_RXPBS_SIZE_I225_MASK … #define IGC_TW_SYSTEM_1000_MASK … /* Minimum time for 100BASE-T where no data will be transmit following move out * of EEE LPI Tx state */ #define IGC_TW_SYSTEM_100_MASK … #define IGC_TW_SYSTEM_100_SHIFT … /* Reg val to set scale to 1024 nsec */ #define IGC_LTRMINV_SCALE_1024 … /* Reg val to set scale to 32768 nsec */ #define IGC_LTRMINV_SCALE_32768 … /* Reg val to set scale to 1024 nsec */ #define IGC_LTRMAXV_SCALE_1024 … /* Reg val to set scale to 32768 nsec */ #define IGC_LTRMAXV_SCALE_32768 … #define IGC_LTRMINV_LTRV_MASK … #define IGC_LTRMAXV_LTRV_MASK … #define IGC_LTRMINV_LSNP_REQ … #define IGC_LTRMINV_SCALE_SHIFT … #define IGC_LTRMAXV_LSNP_REQ … #define IGC_LTRMAXV_SCALE_SHIFT … #endif /* _IGC_DEFINES_H_ */
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