/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 1999 - 2018 Intel Corporation. */ #ifndef _IXGBEVF_DEFINES_H_ #define _IXGBEVF_DEFINES_H_ /* Device IDs */ #define IXGBE_DEV_ID_82599_VF … #define IXGBE_DEV_ID_X540_VF … #define IXGBE_DEV_ID_X550_VF … #define IXGBE_DEV_ID_X550EM_X_VF … #define IXGBE_DEV_ID_X550EM_A_VF … #define IXGBE_DEV_ID_82599_VF_HV … #define IXGBE_DEV_ID_X540_VF_HV … #define IXGBE_DEV_ID_X550_VF_HV … #define IXGBE_DEV_ID_X550EM_X_VF_HV … #define IXGBE_VF_IRQ_CLEAR_MASK … #define IXGBE_VF_MAX_TX_QUEUES … #define IXGBE_VF_MAX_RX_QUEUES … /* DCB define */ #define IXGBE_VF_MAX_TRAFFIC_CLASS … /* Link speed */ ixgbe_link_speed; #define IXGBE_LINK_SPEED_1GB_FULL … #define IXGBE_LINK_SPEED_10GB_FULL … #define IXGBE_LINK_SPEED_100_FULL … #define IXGBE_CTRL_RST … #define IXGBE_RXDCTL_ENABLE … #define IXGBE_TXDCTL_ENABLE … #define IXGBE_LINKS_UP … #define IXGBE_LINKS_SPEED_82599 … #define IXGBE_LINKS_SPEED_10G_82599 … #define IXGBE_LINKS_SPEED_1G_82599 … #define IXGBE_LINKS_SPEED_100_82599 … /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE … #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE … #define IXGBE_REQ_TX_BUFFER_GRANULARITY … /* Interrupt Vector Allocation Registers */ #define IXGBE_IVAR_ALLOC_VAL … #define IXGBE_VF_INIT_TIMEOUT … /* Receive Config masks */ #define IXGBE_RXCTRL_RXEN … #define IXGBE_RXCTRL_DMBYPS … #define IXGBE_RXDCTL_ENABLE … #define IXGBE_RXDCTL_VME … #define IXGBE_RXDCTL_RLPMLMASK … #define IXGBE_RXDCTL_RLPML_EN … /* DCA Control */ #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN … /* PSRTYPE bit definitions */ #define IXGBE_PSRTYPE_TCPHDR … #define IXGBE_PSRTYPE_UDPHDR … #define IXGBE_PSRTYPE_IPV4HDR … #define IXGBE_PSRTYPE_IPV6HDR … #define IXGBE_PSRTYPE_L2HDR … /* SRRCTL bit definitions */ #define IXGBE_SRRCTL_BSIZEPKT_SHIFT … #define IXGBE_SRRCTL_RDMTS_SHIFT … #define IXGBE_SRRCTL_RDMTS_MASK … #define IXGBE_SRRCTL_DROP_EN … #define IXGBE_SRRCTL_BSIZEPKT_MASK … #define IXGBE_SRRCTL_BSIZEHDR_MASK … #define IXGBE_SRRCTL_DESCTYPE_LEGACY … #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF … #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT … #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT … #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS … #define IXGBE_SRRCTL_DESCTYPE_MASK … /* Receive Descriptor bit definitions */ #define IXGBE_RXD_STAT_DD … #define IXGBE_RXD_STAT_EOP … #define IXGBE_RXD_STAT_FLM … #define IXGBE_RXD_STAT_VP … #define IXGBE_RXDADV_NEXTP_MASK … #define IXGBE_RXDADV_NEXTP_SHIFT … #define IXGBE_RXD_STAT_UDPCS … #define IXGBE_RXD_STAT_L4CS … #define IXGBE_RXD_STAT_IPCS … #define IXGBE_RXD_STAT_PIF … #define IXGBE_RXD_STAT_CRCV … #define IXGBE_RXD_STAT_VEXT … #define IXGBE_RXD_STAT_UDPV … #define IXGBE_RXD_STAT_DYNINT … #define IXGBE_RXD_STAT_TS … #define IXGBE_RXD_STAT_SECP … #define IXGBE_RXD_STAT_LB … #define IXGBE_RXD_STAT_ACK … #define IXGBE_RXD_ERR_CE … #define IXGBE_RXD_ERR_LE … #define IXGBE_RXD_ERR_PE … #define IXGBE_RXD_ERR_OSE … #define IXGBE_RXD_ERR_USE … #define IXGBE_RXD_ERR_TCPE … #define IXGBE_RXD_ERR_IPE … #define IXGBE_RXDADV_ERR_MASK … #define IXGBE_RXDADV_ERR_SHIFT … #define IXGBE_RXDADV_ERR_HBO … #define IXGBE_RXDADV_ERR_CE … #define IXGBE_RXDADV_ERR_LE … #define IXGBE_RXDADV_ERR_PE … #define IXGBE_RXDADV_ERR_OSE … #define IXGBE_RXDADV_ERR_USE … #define IXGBE_RXDADV_ERR_TCPE … #define IXGBE_RXDADV_ERR_IPE … #define IXGBE_RXD_VLAN_ID_MASK … #define IXGBE_RXD_PRI_MASK … #define IXGBE_RXD_PRI_SHIFT … #define IXGBE_RXD_CFI_MASK … #define IXGBE_RXD_CFI_SHIFT … #define IXGBE_RXDADV_STAT_DD … #define IXGBE_RXDADV_STAT_EOP … #define IXGBE_RXDADV_STAT_FLM … #define IXGBE_RXDADV_STAT_VP … #define IXGBE_RXDADV_STAT_MASK … #define IXGBE_RXDADV_STAT_FCEOFS … #define IXGBE_RXDADV_STAT_FCSTAT … #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH … #define IXGBE_RXDADV_STAT_FCSTAT_NODDP … #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP … #define IXGBE_RXDADV_STAT_FCSTAT_DDP … #define IXGBE_RXDADV_STAT_SECP … #define IXGBE_RXDADV_RSSTYPE_MASK … #define IXGBE_RXDADV_PKTTYPE_MASK … #define IXGBE_RXDADV_PKTTYPE_IPV4 … #define IXGBE_RXDADV_PKTTYPE_IPV6 … #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP … #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH … #define IXGBE_RXDADV_PKTTYPE_MASK_EX … #define IXGBE_RXDADV_HDRBUFLEN_MASK … #define IXGBE_RXDADV_RSCCNT_MASK … #define IXGBE_RXDADV_RSCCNT_SHIFT … #define IXGBE_RXDADV_HDRBUFLEN_SHIFT … #define IXGBE_RXDADV_SPLITHEADER_EN … #define IXGBE_RXDADV_SPH … /* RSS Hash results */ #define IXGBE_RXDADV_RSSTYPE_NONE … #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP … #define IXGBE_RXDADV_RSSTYPE_IPV4 … #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP … #define IXGBE_RXDADV_RSSTYPE_IPV6_EX … #define IXGBE_RXDADV_RSSTYPE_IPV6 … #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX … #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP … #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP … #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX … #define IXGBE_RXD_ERR_FRAME_ERR_MASK … #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK … #define IXGBE_TXD_POPTS_IXSM … #define IXGBE_TXD_POPTS_TXSM … #define IXGBE_TXD_CMD_EOP … #define IXGBE_TXD_CMD_IFCS … #define IXGBE_TXD_CMD_IC … #define IXGBE_TXD_CMD_RS … #define IXGBE_TXD_CMD_DEXT … #define IXGBE_TXD_CMD_VLE … #define IXGBE_TXD_STAT_DD … #define IXGBE_TXD_CMD … /* Transmit Descriptor - Advanced */ ixgbe_adv_tx_desc; /* Receive Descriptor - Advanced */ ixgbe_adv_rx_desc; /* Context descriptors */ struct ixgbe_adv_tx_context_desc { … }; /* Adv Transmit Descriptor Config Masks */ #define IXGBE_ADVTXD_DTYP_MASK … #define IXGBE_ADVTXD_DTYP_CTXT … #define IXGBE_ADVTXD_DTYP_DATA … #define IXGBE_ADVTXD_DCMD_EOP … #define IXGBE_ADVTXD_DCMD_IFCS … #define IXGBE_ADVTXD_DCMD_RS … #define IXGBE_ADVTXD_DCMD_DEXT … #define IXGBE_ADVTXD_DCMD_VLE … #define IXGBE_ADVTXD_DCMD_TSE … #define IXGBE_ADVTXD_STAT_DD … #define IXGBE_ADVTXD_TUCMD_IPV4 … #define IXGBE_ADVTXD_TUCMD_IPV6 … #define IXGBE_ADVTXD_TUCMD_L4T_UDP … #define IXGBE_ADVTXD_TUCMD_L4T_TCP … #define IXGBE_ADVTXD_TUCMD_L4T_SCTP … #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP … #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN … #define IXGBE_ADVTXD_IDX_SHIFT … #define IXGBE_ADVTXD_CC … #define IXGBE_ADVTXD_POPTS_SHIFT … #define IXGBE_ADVTXD_POPTS_IPSEC … #define IXGBE_ADVTXD_POPTS_IXSM … #define IXGBE_ADVTXD_POPTS_TXSM … #define IXGBE_ADVTXD_PAYLEN_SHIFT … #define IXGBE_ADVTXD_MACLEN_SHIFT … #define IXGBE_ADVTXD_VLAN_SHIFT … #define IXGBE_ADVTXD_L4LEN_SHIFT … #define IXGBE_ADVTXD_MSS_SHIFT … /* Interrupt register bitmasks */ #define IXGBE_EITR_CNT_WDIS … #define IXGBE_MAX_EITR … #define IXGBE_MIN_EITR … /* Error Codes */ #define IXGBE_ERR_INVALID_MAC_ADDR … #define IXGBE_ERR_RESET_FAILED … #define IXGBE_ERR_INVALID_ARGUMENT … #define IXGBE_ERR_CONFIG … #define IXGBE_ERR_MBX … #define IXGBE_ERR_TIMEOUT … #define IXGBE_ERR_PARAM … /* Transmit Config masks */ #define IXGBE_TXDCTL_ENABLE … #define IXGBE_TXDCTL_SWFLSH … #define IXGBE_TXDCTL_WTHRESH_SHIFT … #define IXGBE_DCA_RXCTRL_DESC_DCA_EN … #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN … #define IXGBE_DCA_RXCTRL_DATA_DCA_EN … #define IXGBE_DCA_RXCTRL_DESC_RRO_EN … #define IXGBE_DCA_RXCTRL_DATA_WRO_EN … #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN … #define IXGBE_DCA_TXCTRL_DESC_DCA_EN … #define IXGBE_DCA_TXCTRL_DESC_RRO_EN … #define IXGBE_DCA_TXCTRL_DESC_WRO_EN … #define IXGBE_DCA_TXCTRL_DATA_RRO_EN … #endif /* _IXGBEVF_DEFINES_H_ */
Codebase Browser
linux