/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 2013 - 2019 Intel Corporation. */ #ifndef _FM10K_TYPE_H_ #define _FM10K_TYPE_H_ /* forward declaration */ struct fm10k_hw; #include <linux/types.h> #include <asm/byteorder.h> #include <linux/etherdevice.h> #include "fm10k_mbx.h" #define FM10K_DEV_ID_PF … #define FM10K_DEV_ID_VF … #define FM10K_DEV_ID_SDI_FM10420_QDA2 … #define FM10K_DEV_ID_SDI_FM10420_DA2 … #define FM10K_MAX_QUEUES … #define FM10K_MAX_QUEUES_PF … #define FM10K_MAX_QUEUES_POOL … #define FM10K_48_BIT_MASK … #define FM10K_STAT_VALID … /* PCI Bus Info */ #define FM10K_PCIE_LINK_CAP … #define FM10K_PCIE_LINK_STATUS … #define FM10K_PCIE_LINK_WIDTH … #define FM10K_PCIE_LINK_WIDTH_1 … #define FM10K_PCIE_LINK_WIDTH_2 … #define FM10K_PCIE_LINK_WIDTH_4 … #define FM10K_PCIE_LINK_WIDTH_8 … #define FM10K_PCIE_LINK_SPEED … #define FM10K_PCIE_LINK_SPEED_2500 … #define FM10K_PCIE_LINK_SPEED_5000 … #define FM10K_PCIE_LINK_SPEED_8000 … /* PCIe payload size */ #define FM10K_PCIE_DEV_CAP … #define FM10K_PCIE_DEV_CAP_PAYLOAD … #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 … #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 … #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 … #define FM10K_PCIE_DEV_CTRL … #define FM10K_PCIE_DEV_CTRL_PAYLOAD … #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 … #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 … #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 … /* PCIe MSI-X Capability info */ #define FM10K_PCI_MSIX_MSG_CTRL … #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK … #define FM10K_MAX_MSIX_VECTORS … #define FM10K_MAX_VECTORS_PF … #define FM10K_MAX_VECTORS_POOL … /* PCIe SR-IOV Info */ #define FM10K_PCIE_SRIOV_CTRL … #define FM10K_PCIE_SRIOV_CTRL_VFARI … #define FM10K_ERR_PARAM … #define FM10K_ERR_NO_RESOURCES … #define FM10K_ERR_REQUESTS_PENDING … #define FM10K_ERR_RESET_REQUESTED … #define FM10K_ERR_DMA_PENDING … #define FM10K_ERR_RESET_FAILED … #define FM10K_ERR_INVALID_MAC_ADDR … #define FM10K_ERR_INVALID_VALUE … #define FM10K_NOT_IMPLEMENTED … /* Start of PF registers */ #define FM10K_CTRL … #define FM10K_CTRL_BAR4_ALLOWED … #define FM10K_CTRL_EXT … #define FM10K_GCR … #define FM10K_GCR_EXT … /* Interrupt control registers */ #define FM10K_EICR … #define FM10K_EICR_FAULT_MASK … #define FM10K_EICR_MAILBOX … #define FM10K_EICR_SWITCHREADY … #define FM10K_EICR_SWITCHNOTREADY … #define FM10K_EICR_SWITCHINTERRUPT … #define FM10K_EICR_VFLR … #define FM10K_EICR_MAXHOLDTIME … #define FM10K_EIMR … #define FM10K_EIMR_PCA_FAULT … #define FM10K_EIMR_THI_FAULT … #define FM10K_EIMR_FUM_FAULT … #define FM10K_EIMR_MAILBOX … #define FM10K_EIMR_SWITCHREADY … #define FM10K_EIMR_SWITCHNOTREADY … #define FM10K_EIMR_SWITCHINTERRUPT … #define FM10K_EIMR_SRAMERROR … #define FM10K_EIMR_VFLR … #define FM10K_EIMR_MAXHOLDTIME … #define FM10K_EIMR_ALL … #define FM10K_EIMR_DISABLE(NAME) … #define FM10K_EIMR_ENABLE(NAME) … #define FM10K_FAULT_ADDR_LO … #define FM10K_FAULT_ADDR_HI … #define FM10K_FAULT_SPECINFO … #define FM10K_FAULT_FUNC … #define FM10K_FAULT_SIZE … #define FM10K_FAULT_FUNC_VALID … #define FM10K_FAULT_FUNC_PF … #define FM10K_FAULT_FUNC_VF_MASK … #define FM10K_FAULT_FUNC_VF_SHIFT … #define FM10K_FAULT_FUNC_TYPE_MASK … #define FM10K_PCA_FAULT … #define FM10K_THI_FAULT … #define FM10K_FUM_FAULT … /* Rx queue timeout indicator */ #define FM10K_MAXHOLDQ(_n) … /* Switch Manager info */ #define FM10K_SM_AREA(_n) … /* GLORT mapping registers */ #define FM10K_DGLORTMAP(_n) … #define FM10K_DGLORT_COUNT … #define FM10K_DGLORTMAP_MASK_SHIFT … #define FM10K_DGLORTMAP_ANY … #define FM10K_DGLORTMAP_NONE … #define FM10K_DGLORTMAP_ZERO … #define FM10K_DGLORTDEC(_n) … #define FM10K_DGLORTDEC_VSILENGTH_SHIFT … #define FM10K_DGLORTDEC_VSIBASE_SHIFT … #define FM10K_DGLORTDEC_PCLENGTH_SHIFT … #define FM10K_DGLORTDEC_QBASE_SHIFT … #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT … #define FM10K_DGLORTDEC_INNERRSS_ENABLE … #define FM10K_TUNNEL_CFG … #define FM10K_TUNNEL_CFG_NVGRE_SHIFT … #define FM10K_TUNNEL_CFG_GENEVE … #define FM10K_SWPRI_MAP(_n) … #define FM10K_SWPRI_MAX … #define FM10K_RSSRK(_n, _m) … #define FM10K_RSSRK_SIZE … #define FM10K_RSSRK_ENTRIES_PER_REG … #define FM10K_RETA(_n, _m) … #define FM10K_RETA_SIZE … #define FM10K_RETA_ENTRIES_PER_REG … #define FM10K_MAX_RSS_INDICES … /* Rate limiting registers */ #define FM10K_TC_CREDIT(_n) … #define FM10K_TC_CREDIT_CREDIT_MASK … #define FM10K_TC_MAXCREDIT(_n) … #define FM10K_TC_MAXCREDIT_64K … #define FM10K_TC_RATE(_n) … #define FM10K_TC_RATE_QUANTA_MASK … #define FM10K_TC_RATE_INTERVAL_4US_GEN1 … #define FM10K_TC_RATE_INTERVAL_4US_GEN2 … #define FM10K_TC_RATE_INTERVAL_4US_GEN3 … /* DMA control registers */ #define FM10K_DMA_CTRL … #define FM10K_DMA_CTRL_TX_ENABLE … #define FM10K_DMA_CTRL_TX_ACTIVE … #define FM10K_DMA_CTRL_RX_ENABLE … #define FM10K_DMA_CTRL_RX_ACTIVE … #define FM10K_DMA_CTRL_RX_DESC_SIZE … #define FM10K_DMA_CTRL_MINMSS_64 … #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 … #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 … #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 … #define FM10K_DMA_CTRL_DATAPATH_RESET … #define FM10K_DMA_CTRL_32_DESC … #define FM10K_DMA_CTRL2 … #define FM10K_DMA_CTRL2_SWITCH_READY … /* TSO flags configuration * First packet contains all flags except for fin and psh * Middle packet contains only urg and ack * Last packet contains urg, ack, fin, and psh */ #define FM10K_TSO_FLAGS_LOW … #define FM10K_TSO_FLAGS_HI … #define FM10K_DTXTCPFLGL … #define FM10K_DTXTCPFLGH … #define FM10K_TPH_CTRL … #define FM10K_MRQC(_n) … #define FM10K_MRQC_TCP_IPV4 … #define FM10K_MRQC_IPV4 … #define FM10K_MRQC_IPV6 … #define FM10K_MRQC_TCP_IPV6 … #define FM10K_MRQC_UDP_IPV4 … #define FM10K_MRQC_UDP_IPV6 … #define FM10K_TQMAP(_n) … #define FM10K_TQMAP_TABLE_SIZE … #define FM10K_RQMAP(_n) … /* Hardware Statistics */ #define FM10K_STATS_TIMEOUT … #define FM10K_STATS_UR … #define FM10K_STATS_CA … #define FM10K_STATS_UM … #define FM10K_STATS_XEC … #define FM10K_STATS_VLAN_DROP … #define FM10K_STATS_LOOPBACK_DROP … #define FM10K_STATS_NODESC_DROP … /* PCIe state registers */ #define FM10K_PHYADDR … /* Rx ring registers */ #define FM10K_RDBAL(_n) … #define FM10K_RDBAH(_n) … #define FM10K_RDLEN(_n) … #define FM10K_TPH_RXCTRL(_n) … #define FM10K_TPH_RXCTRL_DESC_TPHEN … #define FM10K_TPH_RXCTRL_DESC_RROEN … #define FM10K_TPH_RXCTRL_DATA_WROEN … #define FM10K_TPH_RXCTRL_HDR_WROEN … #define FM10K_RDH(_n) … #define FM10K_RDT(_n) … #define FM10K_RXQCTL(_n) … #define FM10K_RXQCTL_ENABLE … #define FM10K_RXQCTL_PF … #define FM10K_RXQCTL_VF_SHIFT … #define FM10K_RXQCTL_VF … #define FM10K_RXQCTL_ID_MASK … #define FM10K_RXDCTL(_n) … #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY … #define FM10K_RXDCTL_DROP_ON_EMPTY … #define FM10K_RXINT(_n) … #define FM10K_SRRCTL(_n) … #define FM10K_SRRCTL_BSIZEPKT_SHIFT … #define FM10K_SRRCTL_LOOPBACK_SUPPRESS … #define FM10K_SRRCTL_BUFFER_CHAINING_EN … /* Rx Statistics */ #define FM10K_QPRC(_n) … #define FM10K_QPRDC(_n) … #define FM10K_QBRC_L(_n) … #define FM10K_QBRC_H(_n) … /* Rx GLORT register */ #define FM10K_RX_SGLORT(_n) … /* Tx ring registers */ #define FM10K_TDBAL(_n) … #define FM10K_TDBAH(_n) … #define FM10K_TDLEN(_n) … /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR) * scale which is based on the PCIe speed but the speed information in the PCI * configuration space may not be accurate. The PF already knows the ITR scale * but there is no defined method to pass that information from the PF to the * VF. This is accomplished during VF initialization by temporarily co-opting * the yet-to-be-used TDLEN register to have the PF store the ITR shift for * the VF to retrieve before the VF needs to use the TDLEN register for its * intended purpose, i.e. before the Tx resources are allocated. */ #define FM10K_TDLEN_ITR_SCALE_SHIFT … #define FM10K_TDLEN_ITR_SCALE_MASK … #define FM10K_TDLEN_ITR_SCALE_GEN1 … #define FM10K_TDLEN_ITR_SCALE_GEN2 … #define FM10K_TDLEN_ITR_SCALE_GEN3 … #define FM10K_TPH_TXCTRL(_n) … #define FM10K_TPH_TXCTRL_DESC_TPHEN … #define FM10K_TPH_TXCTRL_DESC_RROEN … #define FM10K_TPH_TXCTRL_DESC_WROEN … #define FM10K_TPH_TXCTRL_DATA_RROEN … #define FM10K_TDH(_n) … #define FM10K_TDT(_n) … #define FM10K_TXDCTL(_n) … #define FM10K_TXDCTL_ENABLE … #define FM10K_TXDCTL_MAX_TIME_SHIFT … #define FM10K_TXQCTL(_n) … #define FM10K_TXQCTL_PF … #define FM10K_TXQCTL_VF … #define FM10K_TXQCTL_ID_MASK … #define FM10K_TXQCTL_PC_SHIFT … #define FM10K_TXQCTL_PC_MASK … #define FM10K_TXQCTL_TC_SHIFT … #define FM10K_TXQCTL_VID_SHIFT … #define FM10K_TXQCTL_VID_MASK … #define FM10K_TXQCTL_UNLIMITED_BW … #define FM10K_TXINT(_n) … /* Tx Statistics */ #define FM10K_QPTC(_n) … #define FM10K_QBTC_L(_n) … #define FM10K_QBTC_H(_n) … /* Tx Push registers */ #define FM10K_TQDLOC(_n) … #define FM10K_TQDLOC_BASE_32_DESC … #define FM10K_TQDLOC_SIZE_32_DESC … /* Tx GLORT registers */ #define FM10K_TX_SGLORT(_n) … #define FM10K_PFVTCTL(_n) … #define FM10K_PFVTCTL_FTAG_DESC_ENABLE … /* Interrupt moderation and control registers */ #define FM10K_INT_MAP(_n) … #define FM10K_INT_MAP_TIMER0 … #define FM10K_INT_MAP_TIMER1 … #define FM10K_INT_MAP_IMMEDIATE … #define FM10K_INT_MAP_DISABLE … #define FM10K_MSIX_VECTOR_MASK(_n) … #define FM10K_INT_CTRL … #define FM10K_INT_CTRL_ENABLEMODERATOR … #define FM10K_ITR(_n) … #define FM10K_ITR_INTERVAL1_SHIFT … #define FM10K_ITR_PENDING2 … #define FM10K_ITR_AUTOMASK … #define FM10K_ITR_MASK_SET … #define FM10K_ITR_MASK_CLEAR … #define FM10K_ITR2(_n) … #define FM10K_ITR_REG_COUNT … #define FM10K_ITR_REG_COUNT_PF … /* Switch manager interrupt registers */ #define FM10K_IP … #define FM10K_IP_NOTINRESET … /* VLAN registers */ #define FM10K_VLAN_TABLE(_n, _m) … #define FM10K_VLAN_TABLE_SIZE … /* VLAN specific message offsets */ #define FM10K_VLAN_TABLE_VID_MAX … #define FM10K_VLAN_TABLE_VSI_MAX … #define FM10K_VLAN_LENGTH_SHIFT … #define FM10K_VLAN_CLEAR … #define FM10K_VLAN_OVERRIDE … #define FM10K_VLAN_ALL … /* VF FLR event notification registers */ #define FM10K_PFVFLRE(_n) … #define FM10K_PFVFLREC(_n) … /* Defines for size of uncacheable memories */ #define FM10K_UC_ADDR_START … #define FM10K_UC_ADDR_END … #define FM10K_UC_ADDR_SIZE … /* Define timeouts for resets and disables */ #define FM10K_QUEUE_DISABLE_TIMEOUT … #define FM10K_RESET_TIMEOUT … /* Maximum supported combined inner and outer header length for encapsulation */ #define FM10K_TUNNEL_HEADER_LENGTH … /* VF registers */ #define FM10K_VFCTRL … #define FM10K_VFCTRL_RST … #define FM10K_VFINT_MAP … #define FM10K_VFSYSTIME … #define FM10K_VFITR(_n) … enum fm10k_int_source { … }; /* PCIe bus speeds */ enum fm10k_bus_speed { … }; /* PCIe bus widths */ enum fm10k_bus_width { … }; /* PCIe payload sizes */ enum fm10k_bus_payload { … }; /* Bus parameters */ struct fm10k_bus_info { … }; /* Statistics related declarations */ struct fm10k_hw_stat { … }; struct fm10k_hw_stats_q { … }; struct fm10k_hw_stats { … }; /* Establish DGLORT feature priority */ enum fm10k_dglortdec_idx { … }; struct fm10k_dglort_cfg { … }; enum fm10k_pca_fault { … }; enum fm10k_thi_fault { … }; enum fm10k_fum_fault { … }; struct fm10k_fault { … }; struct fm10k_mac_ops { … }; enum fm10k_mac_type { … }; struct fm10k_mac_info { … }; struct fm10k_swapi_table_info { … }; struct fm10k_swapi_info { … }; enum fm10k_xcast_modes { … }; #define FM10K_VF_TC_MAX … #define FM10K_VF_TC_MIN … struct fm10k_vf_info { … }; #define FM10K_VF_FLAG_ALLMULTI_CAPABLE … #define FM10K_VF_FLAG_MULTI_CAPABLE … #define FM10K_VF_FLAG_PROMISC_CAPABLE … #define FM10K_VF_FLAG_NONE_CAPABLE … #define FM10K_VF_FLAG_CAPABLE(vf_info) … #define FM10K_VF_FLAG_ENABLED(vf_info) … #define FM10K_VF_FLAG_SET_MODE(mode) … #define FM10K_VF_FLAG_SET_MODE_NONE … #define FM10K_VF_FLAG_MULTI_ENABLED … struct fm10k_iov_ops { … }; struct fm10k_iov_info { … }; enum fm10k_devices { … }; struct fm10k_info { … }; struct fm10k_hw { … }; /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE … #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE … /* Transmit Descriptor */ struct fm10k_tx_desc { … }; /* Transmit Descriptor Cache Structure */ struct fm10k_tx_desc_cache { … }; #define FM10K_TXD_FLAG_INT … #define FM10K_TXD_FLAG_TIME … #define FM10K_TXD_FLAG_CSUM … #define FM10K_TXD_FLAG_FTAG … #define FM10K_TXD_FLAG_RS … #define FM10K_TXD_FLAG_LAST … #define FM10K_TXD_FLAG_DONE … /* These macros are meant to enable optimal placement of the RS and INT * bits. It will point us to the last descriptor in the cache for either the * start of the packet, or the end of the packet. If the index is actually * at the start of the FIFO it will point to the offset for the last index * in the FIFO to prevent an unnecessary write. */ #define FM10K_TXD_WB_FIFO_SIZE … /* Receive Descriptor - 32B */ fm10k_rx_desc; #define FM10K_RXD_RSSTYPE_MASK … enum fm10k_rdesc_rss_type { … }; #define FM10K_RXD_HDR_INFO_XC_MASK … enum fm10k_rxdesc_xc { … }; #define FM10K_RXD_STATUS_DD … #define FM10K_RXD_STATUS_EOP … #define FM10K_RXD_STATUS_L4CS … #define FM10K_RXD_STATUS_L4CS2 … #define FM10K_RXD_STATUS_L4E2 … #define FM10K_RXD_STATUS_IPE2 … #define FM10K_RXD_STATUS_RXE … #define FM10K_RXD_STATUS_L4E … #define FM10K_RXD_STATUS_IPE … #define FM10K_RXD_ERR_SWITCH_ERROR … #define FM10K_RXD_ERR_NO_DESCRIPTOR … #define FM10K_RXD_ERR_PP_ERROR … #define FM10K_RXD_ERR_SWITCH_READY … #define FM10K_RXD_ERR_TOO_BIG … struct fm10k_ftag { … }; #endif /* _FM10K_TYPE_H */
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