/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018, Intel Corporation. */ #ifndef _ICE_LAN_TX_RX_H_ #define _ICE_LAN_TX_RX_H_ ice_32byte_rx_desc; struct ice_fltr_desc { … }; #define ICE_FXD_FLTR_QW0_QINDEX_S … #define ICE_FXD_FLTR_QW0_QINDEX_M … #define ICE_FXD_FLTR_QW0_COMP_Q_S … #define ICE_FXD_FLTR_QW0_COMP_Q_M … #define ICE_FXD_FLTR_QW0_COMP_Q_ZERO … #define ICE_FXD_FLTR_QW0_COMP_REPORT_S … #define ICE_FXD_FLTR_QW0_COMP_REPORT_M … #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL … #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW … #define ICE_FXD_FLTR_QW0_FD_SPACE_S … #define ICE_FXD_FLTR_QW0_FD_SPACE_M … #define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST … #define ICE_FXD_FLTR_QW0_STAT_CNT_S … #define ICE_FXD_FLTR_QW0_STAT_CNT_M … #define ICE_FXD_FLTR_QW0_STAT_ENA_S … #define ICE_FXD_FLTR_QW0_STAT_ENA_M … #define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS … #define ICE_FXD_FLTR_QW0_EVICT_ENA_S … #define ICE_FXD_FLTR_QW0_EVICT_ENA_M … #define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE … #define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE … #define ICE_FXD_FLTR_QW0_TO_Q_S … #define ICE_FXD_FLTR_QW0_TO_Q_M … #define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX … #define ICE_FXD_FLTR_QW0_TO_Q_PRI_S … #define ICE_FXD_FLTR_QW0_TO_Q_PRI_M … #define ICE_FXD_FLTR_QW0_TO_Q_PRIO1 … #define ICE_FXD_FLTR_QW0_DPU_RECIPE_S … #define ICE_FXD_FLTR_QW0_DPU_RECIPE_M … #define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT … #define ICE_FXD_FLTR_QW0_DROP_S … #define ICE_FXD_FLTR_QW0_DROP_M … #define ICE_FXD_FLTR_QW0_DROP_NO … #define ICE_FXD_FLTR_QW0_DROP_YES … #define ICE_FXD_FLTR_QW0_FLEX_PRI_S … #define ICE_FXD_FLTR_QW0_FLEX_PRI_M … #define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE … #define ICE_FXD_FLTR_QW0_FLEX_MDID_S … #define ICE_FXD_FLTR_QW0_FLEX_MDID_M … #define ICE_FXD_FLTR_QW0_FLEX_MDID0 … #define ICE_FXD_FLTR_QW0_FLEX_VAL_S … #define ICE_FXD_FLTR_QW0_FLEX_VAL_M … #define ICE_FXD_FLTR_QW0_FLEX_VAL0 … #define ICE_FXD_FLTR_QW1_DTYPE_S … #define ICE_FXD_FLTR_QW1_DTYPE_M … #define ICE_FXD_FLTR_QW1_PCMD_S … #define ICE_FXD_FLTR_QW1_PCMD_M … #define ICE_FXD_FLTR_QW1_PCMD_ADD … #define ICE_FXD_FLTR_QW1_PCMD_REMOVE … #define ICE_FXD_FLTR_QW1_PROF_PRI_S … #define ICE_FXD_FLTR_QW1_PROF_PRI_M … #define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO … #define ICE_FXD_FLTR_QW1_PROF_S … #define ICE_FXD_FLTR_QW1_PROF_M … #define ICE_FXD_FLTR_QW1_PROF_ZERO … #define ICE_FXD_FLTR_QW1_FD_VSI_S … #define ICE_FXD_FLTR_QW1_FD_VSI_M … #define ICE_FXD_FLTR_QW1_SWAP_S … #define ICE_FXD_FLTR_QW1_SWAP_M … #define ICE_FXD_FLTR_QW1_SWAP_NOT_SET … #define ICE_FXD_FLTR_QW1_SWAP_SET … #define ICE_FXD_FLTR_QW1_FDID_PRI_S … #define ICE_FXD_FLTR_QW1_FDID_PRI_M … #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE … #define ICE_FXD_FLTR_QW1_FDID_PRI_THREE … #define ICE_FXD_FLTR_QW1_FDID_MDID_S … #define ICE_FXD_FLTR_QW1_FDID_MDID_M … #define ICE_FXD_FLTR_QW1_FDID_MDID_FD … #define ICE_FXD_FLTR_QW1_FDID_S … #define ICE_FXD_FLTR_QW1_FDID_M … #define ICE_FXD_FLTR_QW1_FDID_ZERO … /* definition for FD filter programming status descriptor WB format */ #define ICE_FXD_FLTR_WB_QW1_DD_S … #define ICE_FXD_FLTR_WB_QW1_DD_M … #define ICE_FXD_FLTR_WB_QW1_DD_YES … #define ICE_FXD_FLTR_WB_QW1_PROG_ID_S … #define ICE_FXD_FLTR_WB_QW1_PROG_ID_M … #define ICE_FXD_FLTR_WB_QW1_PROG_ADD … #define ICE_FXD_FLTR_WB_QW1_PROG_DEL … #define ICE_FXD_FLTR_WB_QW1_FAIL_S … #define ICE_FXD_FLTR_WB_QW1_FAIL_M … #define ICE_FXD_FLTR_WB_QW1_FAIL_YES … #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S … #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M … #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES … /* Rx Flex Descriptor * This descriptor is used instead of the legacy version descriptor when * ice_rlan_ctx.adv_desc is set */ ice_32b_rx_flex_desc; /* Rx Flex Descriptor NIC Profile * This descriptor corresponds to RxDID 2 which contains * metadata fields for RSS, flow ID and timestamp info */ struct ice_32b_rx_flex_desc_nic { … }; /* Rx Flex Descriptor NIC Profile * RxDID Profile ID 6 * Flex-field 0: RSS hash lower 16-bits * Flex-field 1: RSS hash upper 16-bits * Flex-field 2: Flow ID lower 16-bits * Flex-field 3: Source VSI * Flex-field 4: reserved, VLAN ID taken from L2Tag */ struct ice_32b_rx_flex_desc_nic_2 { … }; /* Receive Flex Descriptor profile IDs: There are a total * of 64 profiles where profile IDs 0/1 are for legacy; and * profiles 2-63 are flex profiles that can be programmed * with a specific metadata (profile 7 reserved for HW) */ enum ice_rxdid { … }; /* Receive Flex Descriptor Rx opcode values */ #define ICE_RX_OPC_MDID … /* Receive Descriptor MDID values that access packet flags */ enum ice_flex_mdid_pkt_flags { … }; /* Receive Descriptor MDID values */ enum ice_flex_rx_mdid { … }; /* Rx/Tx Flag64 packet flag bits */ enum ice_flg64_bits { … }; /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */ #define ICE_RX_FLEX_DESC_PTYPE_M … /* for ice_32byte_rx_flex_desc.pkt_length member */ #define ICE_RX_FLX_DESC_PKT_LEN_M … enum ice_rx_flex_desc_status_error_0_bits { … }; enum ice_rx_flex_desc_status_error_1_bits { … }; #define ICE_RXQ_CTX_SIZE_DWORDS … #define ICE_RXQ_CTX_SZ … #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS … #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS … #define GLTCLAN_CQ_CNTX(i, CQ) … /* RLAN Rx queue context data * * The sizes of the variables may be larger than needed due to crossing byte * boundaries. If we do not have the width of the variable set to the correct * size then we could end up shifting bits off the top of the variable when the * variable is at the top of a byte and crosses over into the next byte. */ struct ice_rlan_ctx { … }; struct ice_ctx_ele { … }; #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) … /* for hsplit_0 field of Rx RLAN context */ enum ice_rlan_ctx_rx_hsplit_0 { … }; /* for hsplit_1 field of Rx RLAN context */ enum ice_rlan_ctx_rx_hsplit_1 { … }; /* Tx Descriptor */ struct ice_tx_desc { … }; enum ice_tx_desc_dtype_value { … }; #define ICE_TXD_QW1_CMD_S … #define ICE_TXD_QW1_CMD_M … enum ice_tx_desc_cmd_bits { … }; #define ICE_TXD_QW1_OFFSET_S … #define ICE_TXD_QW1_OFFSET_M … enum ice_tx_desc_len_fields { … }; #define ICE_TXD_QW1_MACLEN_M … #define ICE_TXD_QW1_IPLEN_M … #define ICE_TXD_QW1_L4LEN_M … /* Tx descriptor field limits in bytes */ #define ICE_TXD_MACLEN_MAX … #define ICE_TXD_IPLEN_MAX … #define ICE_TXD_L4LEN_MAX … #define ICE_TXD_QW1_TX_BUF_SZ_S … #define ICE_TXD_QW1_L2TAG1_S … /* Context descriptors */ struct ice_tx_ctx_desc { … }; #define ICE_TXD_CTX_QW1_CMD_S … #define ICE_TXD_CTX_QW1_CMD_M … #define ICE_TXD_CTX_QW1_TSO_LEN_S … #define ICE_TXD_CTX_QW1_TSO_LEN_M … #define ICE_TXD_CTX_QW1_MSS_S … #define ICE_TXD_CTX_MIN_MSS … #define ICE_TXD_CTX_QW1_VSI_S … #define ICE_TXD_CTX_QW1_VSI_M … enum ice_tx_ctx_desc_cmd_bits { … }; enum ice_tx_ctx_desc_eipt_offload { … }; #define ICE_TXD_CTX_QW0_EIPLEN_S … #define ICE_TXD_CTX_QW0_L4TUNT_S … #define ICE_TXD_CTX_UDP_TUNNELING … #define ICE_TXD_CTX_GRE_TUNNELING … #define ICE_TXD_CTX_QW0_NATLEN_S … #define ICE_TXD_CTX_QW0_L4T_CS_S … #define ICE_TXD_CTX_QW0_L4T_CS_M … #define ICE_LAN_TXQ_MAX_QGRPS … #define ICE_LAN_TXQ_MAX_QDIS … /* Tx queue context data * * The sizes of the variables may be larger than needed due to crossing byte * boundaries. If we do not have the width of the variable set to the correct * size then we could end up shifting bits off the top of the variable when the * variable is at the top of a byte and crosses over into the next byte. */ struct ice_tlan_ctx { … }; #endif /* _ICE_LAN_TX_RX_H_ */
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