/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (C) 2021, Intel Corporation. */ #ifndef _ICE_PTP_HW_H_ #define _ICE_PTP_HW_H_ #include <linux/dpll.h> enum ice_ptp_tmr_cmd { … }; enum ice_ptp_serdes { … }; enum ice_ptp_link_spd { … }; enum ice_ptp_fec_mode { … }; enum eth56g_res_type { … }; enum ice_eth56g_link_spd { … }; /** * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters * @base: base address for each PHY block * @step: step between PHY lanes * * Characteristic information for the various PHY register parameters in the * ETH56G devices */ struct ice_phy_reg_info_eth56g { … }; /** * struct ice_time_ref_info_e82x * @pll_freq: Frequency of PLL that drives timer ticks in Hz * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L * @pps_delay: propagation delay of the PPS output signal * * Characteristic information for the various TIME_REF sources possible in the * E822 devices */ struct ice_time_ref_info_e82x { … }; /** * struct ice_vernier_info_e82x * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds * * Table of constants used during as part of the Vernier calibration of the Tx * and Rx timestamps. This includes frequency values used to compute TUs per * PAR/PCS clock cycle, and static delay values measured during hardware * design. * * Note that some values are not used for all link speeds, and the * P_REG_DESK_PAR* registers may represent different clock markers at * different link speeds, either the deskew marker for multi-lane link speeds * or the Reed Solomon gearbox marker for RS-FEC. */ struct ice_vernier_info_e82x { … }; #define ICE_ETH56G_MAC_CFG_RX_OFFSET_INT … #define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC … #define ICE_ETH56G_MAC_CFG_FRAC_W … /** * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers * @tx_mode: Tx timestamp compensation mode * @tx_mk_dly: Tx timestamp marker start strobe delay * @tx_cw_dly: Tx timestamp codeword start strobe delay * @rx_mode: Rx timestamp compensation mode * @rx_mk_dly: Rx timestamp marker start strobe delay * @rx_cw_dly: Rx timestamp codeword start strobe delay * @blks_per_clk: number of blocks transferred per clock cycle * @blktime: block time, fixed point * @mktime: marker time, fixed point * @tx_offset: total Tx offset, fixed point * @rx_offset: total Rx offset, contains value for bitslip/deskew, fixed point * * All fixed point registers except Rx offset are 23 bit unsigned ints with * a 9 bit fractional. * Rx offset is 11 bit unsigned int with a 9 bit fractional. */ struct ice_eth56g_mac_reg_cfg { … }; extern const struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD]; /** * struct ice_cgu_pll_params_e82x - E82X CGU parameters * @refclk_pre_div: Reference clock pre-divisor * @feedback_div: Feedback divisor * @frac_n_div: Fractional divisor * @post_pll_div: Post PLL divisor * * Clock Generation Unit parameters used to program the PLL based on the * selected TIME_REF frequency. */ struct ice_cgu_pll_params_e82x { … }; #define E810C_QSFP_C827_0_HANDLE … #define E810C_QSFP_C827_1_HANDLE … enum ice_e810_c827_idx { … }; enum ice_phy_rclk_pins { … }; #define ICE_E810_RCLK_PINS_NUM … #define ICE_E82X_RCLK_PINS_NUM … #define E810T_CGU_INPUT_C827(_phy, _pin) … enum ice_zl_cgu_in_pins { … }; enum ice_zl_cgu_out_pins { … }; enum ice_si_cgu_in_pins { … }; enum ice_si_cgu_out_pins { … }; struct ice_cgu_pin_desc { … }; extern const struct ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ]; /** * struct ice_cgu_pll_params_e825c - E825C CGU parameters * @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection * @tspll_ndivratio: ndiv ratio that goes directly to the pll * @tspll_fbdiv_intgr: TS PLL integer feedback divide * @tspll_fbdiv_frac: TS PLL fractional feedback divide * @ref1588_ck_div: clock divider for tspll ref * * Clock Generation Unit parameters used to program the PLL based on the * selected TIME_REF/TCXO frequency. */ struct ice_cgu_pll_params_e825c { … }; extern const struct ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ]; #define E810C_QSFP_C827_0_HANDLE … #define E810C_QSFP_C827_1_HANDLE … /* Table of constants related to possible ETH56G PHY resources */ extern const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES]; /* Table of constants related to possible TIME_REF sources */ extern const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ]; /* Table of constants for Vernier calibration on E822 */ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD]; /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for * the E810 devices. Based off of a PLL with an 812.5 MHz frequency. */ #define ICE_E810_PLL_FREQ … #define ICE_PTP_NOMINAL_INCVAL_E810 … #define E810_OUT_PROP_DELAY_NS … /* Device agnostic functions */ u8 ice_get_ptp_src_clock_index(struct ice_hw *hw); bool ice_ptp_lock(struct ice_hw *hw); void ice_ptp_unlock(struct ice_hw *hw); void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd); int ice_ptp_init_time(struct ice_hw *hw, u64 time); int ice_ptp_write_incval(struct ice_hw *hw, u64 incval); int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval); int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj); int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw); int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx); void ice_ptp_reset_ts_memory(struct ice_hw *hw); int ice_ptp_init_phc(struct ice_hw *hw); void ice_ptp_init_hw(struct ice_hw *hw); int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready); int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, enum ice_ptp_tmr_cmd configured_cmd); /* E822 family functions */ int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val); int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val); void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad); /** * ice_e82x_time_ref - Get the current TIME_REF from capabilities * @hw: pointer to the HW structure * * Returns the current TIME_REF from the capabilities structure. */ static inline enum ice_time_ref_freq ice_e82x_time_ref(struct ice_hw *hw) { … } /** * ice_set_e82x_time_ref - Set new TIME_REF * @hw: pointer to the HW structure * @time_ref: new TIME_REF to set * * Update the TIME_REF in the capabilities structure in response to some * change, such as an update to the CGU registers. */ static inline void ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref) { … } static inline u64 ice_e82x_pll_freq(enum ice_time_ref_freq time_ref) { … } static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref) { … } static inline u64 ice_e82x_pps_delay(enum ice_time_ref_freq time_ref) { … } /* E822 Vernier calibration functions */ int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset); int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port); int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port); int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port); int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold); /* E810 family functions */ int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data); int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data); int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data); bool ice_is_pca9575_present(struct ice_hw *hw); int ice_cgu_get_num_pins(struct ice_hw *hw, bool input); enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input); struct dpll_pin_frequency * ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num); const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input); int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, enum dpll_lock_status last_dpll_state, u8 *pin, u8 *ref_state, u8 *eec_mode, s64 *phase_offset, enum dpll_lock_status *dpll_state); int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num); int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, unsigned long *caps); /* ETH56G family functions */ int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status); int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset); int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port); int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port); int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port); int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold); int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port); #define ICE_ETH56G_NOMINAL_INCVAL … #define ICE_ETH56G_NOMINAL_PCS_REF_TUS … #define ICE_ETH56G_NOMINAL_PCS_REF_INC … #define ICE_ETH56G_NOMINAL_THRESH4 … #define ICE_ETH56G_NOMINAL_TX_THRESH … /** * ice_get_base_incval - Get base clock increment value * @hw: pointer to the HW struct * * Return: base clock increment value for supported PHYs, 0 otherwise */ static inline u64 ice_get_base_incval(struct ice_hw *hw) { … } #define PFTSYN_SEM_BYTES … #define ICE_PTP_CLOCK_INDEX_0 … #define ICE_PTP_CLOCK_INDEX_1 … /* PHY timer commands */ #define SEL_CPK_SRC … #define SEL_PHY_SRC … /* Time Sync command Definitions */ #define GLTSYN_CMD_INIT_TIME … #define GLTSYN_CMD_INIT_INCVAL … #define GLTSYN_CMD_INIT_TIME_INCVAL … #define GLTSYN_CMD_ADJ_TIME … #define GLTSYN_CMD_ADJ_INIT_TIME … #define GLTSYN_CMD_READ_TIME … /* PHY port Time Sync command definitions */ #define PHY_CMD_INIT_TIME … #define PHY_CMD_INIT_INCVAL … #define PHY_CMD_ADJ_TIME … #define PHY_CMD_ADJ_TIME_AT_TIME … #define PHY_CMD_READ_TIME … #define TS_CMD_MASK_E810 … #define TS_CMD_MASK … #define SYNC_EXEC_CMD … #define TS_CMD_RX_TYPE … /* Macros to derive port low and high addresses on both quads */ #define P_Q0_L(a, p) … #define P_Q0_H(a, p) … #define P_Q1_L(a, p) … #define P_Q1_H(a, p) … /* PHY QUAD register base addresses */ #define Q_0_BASE … #define Q_1_BASE … /* Timestamp memory reset registers */ #define Q_REG_TS_CTRL … #define Q_REG_TS_CTRL_S … #define Q_REG_TS_CTRL_M … /* Timestamp availability status registers */ #define Q_REG_TX_MEMORY_STATUS_L … #define Q_REG_TX_MEMORY_STATUS_U … /* Tx FIFO status registers */ #define Q_REG_FIFO23_STATUS … #define Q_REG_FIFO01_STATUS … #define Q_REG_FIFO02_S … #define Q_REG_FIFO02_M … #define Q_REG_FIFO13_S … #define Q_REG_FIFO13_M … /* Interrupt control Config registers */ #define Q_REG_TX_MEM_GBL_CFG … #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S … #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M … #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M … #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M … #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M … /* Tx Timestamp data registers */ #define Q_REG_TX_MEMORY_BANK_START … /* PHY port register base addresses */ #define P_0_BASE … #define P_4_BASE … /* Timestamp init registers */ #define P_REG_RX_TIMER_INC_PRE_L … #define P_REG_RX_TIMER_INC_PRE_U … #define P_REG_TX_TIMER_INC_PRE_L … #define P_REG_TX_TIMER_INC_PRE_U … /* Timestamp match and adjust target registers */ #define P_REG_RX_TIMER_CNT_ADJ_L … #define P_REG_RX_TIMER_CNT_ADJ_U … #define P_REG_TX_TIMER_CNT_ADJ_L … #define P_REG_TX_TIMER_CNT_ADJ_U … /* Timestamp capture registers */ #define P_REG_RX_CAPTURE_L … #define P_REG_RX_CAPTURE_U … #define P_REG_TX_CAPTURE_L … #define P_REG_TX_CAPTURE_U … /* Timestamp PHY incval registers */ #define P_REG_TIMETUS_L … #define P_REG_TIMETUS_U … #define P_REG_40B_LOW_M … #define P_REG_40B_HIGH_S … /* PHY window length registers */ #define P_REG_WL … #define PTP_VERNIER_WL … /* PHY start registers */ #define P_REG_PS … #define P_REG_PS_START_S … #define P_REG_PS_START_M … #define P_REG_PS_BYPASS_MODE_S … #define P_REG_PS_BYPASS_MODE_M … #define P_REG_PS_ENA_CLK_S … #define P_REG_PS_ENA_CLK_M … #define P_REG_PS_LOAD_OFFSET_S … #define P_REG_PS_LOAD_OFFSET_M … #define P_REG_PS_SFT_RESET_S … #define P_REG_PS_SFT_RESET_M … /* PHY offset valid registers */ #define P_REG_TX_OV_STATUS … #define P_REG_TX_OV_STATUS_OV_S … #define P_REG_TX_OV_STATUS_OV_M … #define P_REG_RX_OV_STATUS … #define P_REG_RX_OV_STATUS_OV_S … #define P_REG_RX_OV_STATUS_OV_M … /* PHY offset ready registers */ #define P_REG_TX_OR … #define P_REG_RX_OR … /* PHY total offset registers */ #define P_REG_TOTAL_RX_OFFSET_L … #define P_REG_TOTAL_RX_OFFSET_U … #define P_REG_TOTAL_TX_OFFSET_L … #define P_REG_TOTAL_TX_OFFSET_U … /* Timestamp PAR/PCS registers */ #define P_REG_UIX66_10G_40G_L … #define P_REG_UIX66_10G_40G_U … #define P_REG_UIX66_25G_100G_L … #define P_REG_UIX66_25G_100G_U … #define P_REG_DESK_PAR_RX_TUS_L … #define P_REG_DESK_PAR_RX_TUS_U … #define P_REG_DESK_PAR_TX_TUS_L … #define P_REG_DESK_PAR_TX_TUS_U … #define P_REG_DESK_PCS_RX_TUS_L … #define P_REG_DESK_PCS_RX_TUS_U … #define P_REG_DESK_PCS_TX_TUS_L … #define P_REG_DESK_PCS_TX_TUS_U … #define P_REG_PAR_RX_TUS_L … #define P_REG_PAR_RX_TUS_U … #define P_REG_PAR_TX_TUS_L … #define P_REG_PAR_TX_TUS_U … #define P_REG_PCS_RX_TUS_L … #define P_REG_PCS_RX_TUS_U … #define P_REG_PCS_TX_TUS_L … #define P_REG_PCS_TX_TUS_U … #define P_REG_PAR_RX_TIME_L … #define P_REG_PAR_RX_TIME_U … #define P_REG_PAR_TX_TIME_L … #define P_REG_PAR_TX_TIME_U … #define P_REG_PAR_PCS_RX_OFFSET_L … #define P_REG_PAR_PCS_RX_OFFSET_U … #define P_REG_PAR_PCS_TX_OFFSET_L … #define P_REG_PAR_PCS_TX_OFFSET_U … #define P_REG_LINK_SPEED … #define P_REG_LINK_SPEED_SERDES_S … #define P_REG_LINK_SPEED_SERDES_M … #define P_REG_LINK_SPEED_FEC_MODE_S … #define P_REG_LINK_SPEED_FEC_MODE_M … #define P_REG_LINK_SPEED_FEC_MODE(reg) … /* PHY timestamp related registers */ #define P_REG_PMD_ALIGNMENT … #define P_REG_RX_80_TO_160_CNT … #define P_REG_RX_80_TO_160_CNT_RXCYC_S … #define P_REG_RX_80_TO_160_CNT_RXCYC_M … #define P_REG_RX_40_TO_160_CNT … #define P_REG_RX_40_TO_160_CNT_RXCYC_S … #define P_REG_RX_40_TO_160_CNT_RXCYC_M … /* Rx FIFO status registers */ #define P_REG_RX_OV_FS … #define P_REG_RX_OV_FS_FIFO_STATUS_S … #define P_REG_RX_OV_FS_FIFO_STATUS_M … /* Timestamp command registers */ #define P_REG_TX_TMR_CMD … #define P_REG_RX_TMR_CMD … /* E810 timesync enable register */ #define ETH_GLTSYN_ENA(_i) … /* E810 shadow init time registers */ #define ETH_GLTSYN_SHTIME_0(i) … #define ETH_GLTSYN_SHTIME_L(i) … /* E810 shadow time adjust registers */ #define ETH_GLTSYN_SHADJ_L(_i) … #define ETH_GLTSYN_SHADJ_H(_i) … /* E810 timer command register */ #define E810_ETH_GLTSYN_CMD … /* Source timer incval macros */ #define INCVAL_HIGH_M … /* Timestamp block macros */ #define TS_VALID … #define TS_LOW_M … #define TS_HIGH_M … #define TS_HIGH_S … #define TS_PHY_LOW_M … #define TS_PHY_HIGH_M … #define TS_PHY_HIGH_S … #define BYTES_PER_IDX_ADDR_L_U … #define BYTES_PER_IDX_ADDR_L … /* Tx timestamp low latency read definitions */ #define TS_LL_READ_RETRIES … #define TS_LL_READ_TS_HIGH … #define TS_LL_READ_TS_IDX … #define TS_LL_READ_TS_INTR … #define TS_LL_READ_TS … /* Internal PHY timestamp address */ #define TS_L(a, idx) … #define TS_H(a, idx) … /* External PHY timestamp address */ #define TS_EXT(a, port, idx) … #define LOW_TX_MEMORY_BANK_START … #define HIGH_TX_MEMORY_BANK_START … /* E810T SMA controller pin control */ #define ICE_SMA1_DIR_EN_E810T … #define ICE_SMA1_TX_EN_E810T … #define ICE_SMA2_UFL2_RX_DIS_E810T … #define ICE_SMA2_DIR_EN_E810T … #define ICE_SMA2_TX_EN_E810T … #define ICE_SMA1_MASK_E810T … #define ICE_SMA2_MASK_E810T … #define ICE_ALL_SMA_MASK_E810T … #define ICE_SMA_MIN_BIT_E810T … #define ICE_SMA_MAX_BIT_E810T … #define ICE_PCA9575_P1_OFFSET … /* E810T PCA9575 IO controller registers */ #define ICE_PCA9575_P0_IN … /* E810T PCA9575 IO controller pin control */ #define ICE_E810T_P0_GNSS_PRSNT_N … /* ETH56G PHY register addresses */ /* Timestamp PHY incval registers */ #define PHY_REG_TIMETUS_L … #define PHY_REG_TIMETUS_U … /* Timestamp PCS registers */ #define PHY_PCS_REF_TUS_L … #define PHY_PCS_REF_TUS_U … /* Timestamp PCS ref incval registers */ #define PHY_PCS_REF_INC_L … #define PHY_PCS_REF_INC_U … /* Timestamp init registers */ #define PHY_REG_RX_TIMER_INC_PRE_L … #define PHY_REG_RX_TIMER_INC_PRE_U … #define PHY_REG_TX_TIMER_INC_PRE_L … #define PHY_REG_TX_TIMER_INC_PRE_U … /* Timestamp match and adjust target registers */ #define PHY_REG_RX_TIMER_CNT_ADJ_L … #define PHY_REG_RX_TIMER_CNT_ADJ_U … #define PHY_REG_TX_TIMER_CNT_ADJ_L … #define PHY_REG_TX_TIMER_CNT_ADJ_U … /* Timestamp command registers */ #define PHY_REG_TX_TMR_CMD … #define PHY_REG_RX_TMR_CMD … /* Phy offset ready registers */ #define PHY_REG_TX_OFFSET_READY … #define PHY_REG_RX_OFFSET_READY … /* Phy total offset registers */ #define PHY_REG_TOTAL_TX_OFFSET_L … #define PHY_REG_TOTAL_TX_OFFSET_U … #define PHY_REG_TOTAL_RX_OFFSET_L … #define PHY_REG_TOTAL_RX_OFFSET_U … /* Timestamp capture registers */ #define PHY_REG_TX_CAPTURE_L … #define PHY_REG_TX_CAPTURE_U … #define PHY_REG_RX_CAPTURE_L … #define PHY_REG_RX_CAPTURE_U … /* Memory status registers */ #define PHY_REG_TX_MEMORY_STATUS_L … #define PHY_REG_TX_MEMORY_STATUS_U … /* Interrupt config register */ #define PHY_REG_TS_INT_CONFIG … /* XIF mode config register */ #define PHY_MAC_XIF_MODE … #define PHY_MAC_XIF_1STEP_ENA_M … #define PHY_MAC_XIF_TS_BIN_MODE_M … #define PHY_MAC_XIF_TS_SFD_ENA_M … #define PHY_MAC_XIF_GMII_TS_SEL_M … /* GPCS config register */ #define PHY_GPCS_CONFIG_REG0 … #define PHY_GPCS_CONFIG_REG0_TX_THR_M … #define PHY_GPCS_BITSLIP … #define PHY_TS_INT_CONFIG_THRESHOLD_M … #define PHY_TS_INT_CONFIG_ENA_M … /* 1-step PTP config */ #define PHY_PTP_1STEP_CONFIG … #define PHY_PTP_1STEP_T1S_UP64_M … #define PHY_PTP_1STEP_T1S_DELTA_M … #define PHY_PTP_1STEP_PEER_DELAY(_port) … #define PHY_PTP_1STEP_PD_ADD_PD_M … #define PHY_PTP_1STEP_PD_DELAY_M … #define PHY_PTP_1STEP_PD_DLY_V_M … /* Macros to derive offsets for TimeStampLow and TimeStampHigh */ #define PHY_TSTAMP_L(x) … #define PHY_TSTAMP_U(x) … #define PHY_REG_REVISION … #define PHY_REG_DESKEW_0 … #define PHY_REG_DESKEW_0_RLEVEL … #define PHY_REG_DESKEW_0_RLEVEL_FRAC … #define PHY_REG_DESKEW_0_RLEVEL_FRAC_W … #define PHY_REG_DESKEW_0_VALID … #define PHY_REG_GPCS_BITSLIP … #define PHY_REG_SD_BIT_SLIP(_port_offset) … #define PHY_REVISION_ETH56G … #define PHY_VENDOR_TXLANE_THRESH … #define PHY_MAC_TSU_CONFIG … #define PHY_MAC_TSU_CFG_RX_MODE_M … #define PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M … #define PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M … #define PHY_MAC_TSU_CFG_TX_MODE_M … #define PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M … #define PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M … #define PHY_MAC_TSU_CFG_BLKS_PER_CLK_M … #define PHY_MAC_RX_MODULO … #define PHY_MAC_RX_OFFSET … #define PHY_MAC_RX_OFFSET_M … #define PHY_MAC_TX_MODULO … #define PHY_MAC_BLOCKTIME … #define PHY_MAC_MARKERTIME … #define PHY_MAC_TX_OFFSET … #define PHY_PTP_INT_STATUS … #endif /* _ICE_PTP_HW_H_ */
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