// SPDX-License-Identifier: GPL-2.0 /* Copyright (C) 2021, Intel Corporation. */ #include <linux/delay.h> #include <linux/iopoll.h> #include "ice_common.h" #include "ice_ptp_hw.h" #include "ice_ptp_consts.h" #include "ice_cgu_regs.h" static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = …; static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = …; static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = …; static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = …; static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = …; static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = …; static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = …; static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = …; static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = …; static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = …; static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = …; /* Low level functions for interacting with and managing the device clock used * for the Precision Time Protocol. * * The ice hardware represents the current time using three registers: * * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R * +---------------+ +---------------+ +---------------+ * | 32 bits | | 32 bits | | 32 bits | * +---------------+ +---------------+ +---------------+ * * The registers are incremented every clock tick using a 40bit increment * value defined over two registers: * * GLTSYN_INCVAL_H GLTSYN_INCVAL_L * +---------------+ +---------------+ * | 8 bit s | | 32 bits | * +---------------+ +---------------+ * * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L * registers every clock source tick. Depending on the specific device * configuration, the clock source frequency could be one of a number of * values. * * For E810 devices, the increment frequency is 812.5 MHz * * For E822 devices the clock can be derived from different sources, and the * increment has an effective frequency of one of the following: * - 823.4375 MHz * - 783.36 MHz * - 796.875 MHz * - 816 MHz * - 830.078125 MHz * - 783.36 MHz * * The hardware captures timestamps in the PHY for incoming packets, and for * outgoing packets on request. To support this, the PHY maintains a timer * that matches the lower 64 bits of the global source timer. * * In order to ensure that the PHY timers and the source timer are equivalent, * shadow registers are used to prepare the desired initial values. A special * sync command is issued to trigger copying from the shadow registers into * the appropriate source and PHY registers simultaneously. * * The driver supports devices which have different PHYs with subtly different * mechanisms to program and control the timers. We divide the devices into * families named after the first major device, E810 and similar devices, and * E822 and similar devices. * * - E822 based devices have additional support for fine grained Vernier * calibration which requires significant setup * - The layout of timestamp data in the PHY register blocks is different * - The way timer synchronization commands are issued is different. * * To support this, very low level functions have an e810 or e822 suffix * indicating what type of device they work on. Higher level abstractions for * tasks that can be done on both devices do not have the suffix and will * correctly look up the appropriate low level function when running. * * Functions which only make sense on a single device family may not have * a suitable generic implementation */ /** * ice_get_ptp_src_clock_index - determine source clock index * @hw: pointer to HW struct * * Determine the source clock index currently in use, based on device * capabilities reported during initialization. */ u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) { … } /** * ice_ptp_read_src_incval - Read source timer increment value * @hw: pointer to HW struct * * Read the increment value of the source timer and return it. */ static u64 ice_ptp_read_src_incval(struct ice_hw *hw) { … } /** * ice_read_cgu_reg_e82x - Read a CGU register * @hw: pointer to the HW struct * @addr: Register address to read * @val: storage for register value read * * Read the contents of a register of the Clock Generation Unit. Only * applicable to E822 devices. * * Return: 0 on success, other error codes when failed to read from CGU */ static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val) { … } /** * ice_write_cgu_reg_e82x - Write a CGU register * @hw: pointer to the HW struct * @addr: Register address to write * @val: value to write into the register * * Write the specified value to a register of the Clock Generation Unit. Only * applicable to E822 devices. * * Return: 0 on success, other error codes when failed to write to CGU */ static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val) { … } /** * ice_clk_freq_str - Convert time_ref_freq to string * @clk_freq: Clock frequency * * Return: specified TIME_REF clock frequency converted to a string */ static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq) { … } /** * ice_clk_src_str - Convert time_ref_src to string * @clk_src: Clock source * * Return: specified clock source converted to its string name */ static const char *ice_clk_src_str(enum ice_clk_src clk_src) { … } /** * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit * @hw: pointer to the HW struct * @clk_freq: Clock frequency to program * @clk_src: Clock source to select (TIME_REF, or TCXO) * * Configure the Clock Generation Unit with the desired clock frequency and * time reference, enabling the PLL which drives the PTP hardware clock. * * Return: * * %0 - success * * %-EINVAL - input parameters are incorrect * * %-EBUSY - failed to lock TS PLL * * %other - CGU read/write failure */ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, enum ice_clk_src clk_src) { … } /** * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C * @hw: pointer to the HW struct * @clk_freq: Clock frequency to program * @clk_src: Clock source to select (TIME_REF, or TCXO) * * Configure the Clock Generation Unit with the desired clock frequency and * time reference, enabling the PLL which drives the PTP hardware clock. * * Return: * * %0 - success * * %-EINVAL - input parameters are incorrect * * %-EBUSY - failed to lock TS PLL * * %other - CGU read/write failure */ static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, enum ice_clk_src clk_src) { … } /** * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits * @hw: pointer to the HW struct * * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on * losing TS PLL lock, but always show current state. * * Return: 0 on success, other error codes when failed to read/write CGU */ static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw) { … } /** * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C * @hw: pointer to the HW struct * * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on * losing TS PLL lock, but always show current state. * * Return: 0 on success, other error codes when failed to read/write CGU */ static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw) { … } /** * ice_init_cgu_e82x - Initialize CGU with settings from firmware * @hw: pointer to the HW structure * * Initialize the Clock Generation Unit of the E822 device. * * Return: 0 on success, other error codes when failed to read/write/cfg CGU */ static int ice_init_cgu_e82x(struct ice_hw *hw) { … } /** * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value * @hw: pointer to HW struct * @cmd: Timer command * * Return: the source timer command register value for the given PTP timer * command. */ static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) { … } /** * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value * @hw: pointer to HW struct * @cmd: Timer command * * Note that some hardware families use a different command register value for * the PHY ports, while other hardware families use the same register values * as the source timer. * * Return: the PHY port timer command register value for the given PTP timer * command. */ static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) { … } /** * ice_ptp_src_cmd - Prepare source timer for a timer command * @hw: pointer to HW structure * @cmd: Timer command * * Prepare the source timer for an upcoming timer sync command. */ void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) { … } /** * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands * @hw: pointer to HW struct * * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the * write immediately. This triggers the hardware to begin executing all of the * source and PHY timer commands synchronously. */ static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) { … } /* 56G PHY device functions * * The following functions operate on devices with the ETH 56G PHY. */ /** * ice_write_phy_eth56g - Write a PHY port register * @hw: pointer to the HW struct * @phy_idx: PHY index * @addr: PHY register address * @val: Value to write * * Return: 0 on success, other error codes when failed to write to PHY */ static int ice_write_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr, u32 val) { … } /** * ice_read_phy_eth56g - Read a PHY port register * @hw: pointer to the HW struct * @phy_idx: PHY index * @addr: PHY register address * @val: Value to write * * Return: 0 on success, other error codes when failed to read from PHY */ static int ice_read_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr, u32 *val) { … } /** * ice_phy_res_address_eth56g - Calculate a PHY port register address * @port: Port number to be written * @res_type: resource type (register/memory) * @offset: Offset from PHY port register base * @addr: The result address * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type */ static int ice_phy_res_address_eth56g(u8 port, enum eth56g_res_type res_type, u32 offset, u32 *addr) { … } /** * ice_write_port_eth56g - Write a PHY port register * @hw: pointer to the HW struct * @offset: PHY register offset * @port: Port number * @val: Value to write * @res_type: resource type (register/memory) * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type * * %other - failed to write to PHY */ static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, u32 val, enum eth56g_res_type res_type) { … } /** * ice_read_port_eth56g - Read a PHY port register * @hw: pointer to the HW struct * @offset: PHY register offset * @port: Port number * @val: Value to write * @res_type: resource type (register/memory) * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type * * %other - failed to read from PHY */ static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, u32 *val, enum eth56g_res_type res_type) { … } /** * ice_write_ptp_reg_eth56g - Write a PHY port register * @hw: pointer to the HW struct * @port: Port number to be written * @offset: Offset from PHY port register base * @val: Value to write * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type * * %other - failed to write to PHY */ static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val) { … } /** * ice_write_mac_reg_eth56g - Write a MAC PHY port register * parameter * @hw: pointer to the HW struct * @port: Port number to be written * @offset: Offset from PHY port register base * @val: Value to write * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type * * %other - failed to write to PHY */ static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, u32 val) { … } /** * ice_write_xpcs_reg_eth56g - Write a PHY port register * @hw: pointer to the HW struct * @port: Port number to be written * @offset: Offset from PHY port register base * @val: Value to write * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type * * %other - failed to write to PHY */ static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, u32 val) { … } /** * ice_read_ptp_reg_eth56g - Read a PHY port register * @hw: pointer to the HW struct * @port: Port number to be read * @offset: Offset from PHY port register base * @val: Pointer to the value to read (out param) * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type * * %other - failed to read from PHY */ static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val) { … } /** * ice_read_mac_reg_eth56g - Read a PHY port register * @hw: pointer to the HW struct * @port: Port number to be read * @offset: Offset from PHY port register base * @val: Pointer to the value to read (out param) * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type * * %other - failed to read from PHY */ static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val) { … } /** * ice_read_gpcs_reg_eth56g - Read a PHY port register * @hw: pointer to the HW struct * @port: Port number to be read * @offset: Offset from PHY port register base * @val: Pointer to the value to read (out param) * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type * * %other - failed to read from PHY */ static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val) { … } /** * ice_read_port_mem_eth56g - Read a PHY port memory location * @hw: pointer to the HW struct * @port: Port number to be read * @offset: Offset from PHY port register base * @val: Pointer to the value to read (out param) * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type * * %other - failed to read from PHY */ static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val) { … } /** * ice_write_port_mem_eth56g - Write a PHY port memory location * @hw: pointer to the HW struct * @port: Port number to be read * @offset: Offset from PHY port register base * @val: Pointer to the value to read (out param) * * Return: * * %0 - success * * %EINVAL - invalid port number or resource type * * %other - failed to write to PHY */ static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val) { … } /** * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register * @low_addr: the low address to check * @high_addr: on return, contains the high address of the 64bit register * * Write the appropriate high register offset to use. * * Return: true if the provided low address is one of the known 64bit PHY values * represented as two 32bit registers, false otherwise. */ static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) { … } /** * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register * @low_addr: the low address to check * @high_addr: on return, contains the high address of the 40bit value * * Write the appropriate high register offset to use. * * Return: true if the provided low address is one of the known 40bit PHY * values split into two registers with the lower 8 bits in the low register and * the upper 32 bits in the high register, false otherwise. */ static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) { … } /** * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers * @hw: pointer to the HW struct * @port: PHY port to read from * @low_addr: offset of the lower register to read from * @val: on return, the contents of the 64bit value from the PHY registers * @res_type: resource type * * Check if the caller has specified a known 40 bit register offset and read * the two registers associated with a 40bit value and return it in the val * pointer. * * Return: * * %0 - success * * %EINVAL - not a 64 bit register * * %other - failed to read from PHY */ static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val, enum eth56g_res_type res_type) { … } /** * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers * @hw: pointer to the HW struct * @port: PHY port to read from * @low_addr: offset of the lower register to read from * @val: on return, the contents of the 64bit value from the PHY registers * * Check if the caller has specified a known 40 bit register offset and read * the two registers associated with a 40bit value and return it in the val * pointer. * * Return: * * %0 - success * * %EINVAL - not a 64 bit register * * %other - failed to read from PHY */ static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) { … } /** * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY * @hw: pointer to the HW struct * @port: port to write to * @low_addr: offset of the low register * @val: 40b value to write * @res_type: resource type * * Check if the caller has specified a known 40 bit register offset and write * provided 40b value to the two associated registers by splitting it up into * two chunks, the lower 8 bits and the upper 32 bits. * * Return: * * %0 - success * * %EINVAL - not a 40 bit register * * %other - failed to write to PHY */ static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val, enum eth56g_res_type res_type) { … } /** * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY * @hw: pointer to the HW struct * @port: port to write to * @low_addr: offset of the low register * @val: 40b value to write * * Check if the caller has specified a known 40 bit register offset and write * provided 40b value to the two associated registers by splitting it up into * two chunks, the lower 8 bits and the upper 32 bits. * * Return: * * %0 - success * * %EINVAL - not a 40 bit register * * %other - failed to write to PHY */ static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) { … } /** * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers * @hw: pointer to the HW struct * @port: PHY port to read from * @low_addr: offset of the lower register to read from * @val: the contents of the 64bit value to write to PHY * @res_type: resource type * * Check if the caller has specified a known 64 bit register offset and write * the 64bit value to the two associated 32bit PHY registers. * * Return: * * %0 - success * * %EINVAL - not a 64 bit register * * %other - failed to write to PHY */ static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val, enum eth56g_res_type res_type) { … } /** * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers * @hw: pointer to the HW struct * @port: PHY port to read from * @low_addr: offset of the lower register to read from * @val: the contents of the 64bit value to write to PHY * * Check if the caller has specified a known 64 bit register offset and write * the 64bit value to the two associated 32bit PHY registers. * * Return: * * %0 - success * * %EINVAL - not a 64 bit register * * %other - failed to write to PHY */ static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) { … } /** * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory * @hw: pointer to the HW struct * @port: the port to read from * @idx: the timestamp index to read * @tstamp: on return, the 40bit timestamp value * * Read a 40bit timestamp value out of the two associated entries in the * port memory block of the internal PHYs of the 56G devices. * * Return: * * %0 - success * * %other - failed to read from PHY */ static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, u64 *tstamp) { … } /** * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block * @hw: pointer to the HW struct * @port: the quad to read from * @idx: the timestamp index to reset * * Read and then forcibly clear the timestamp index to ensure the valid bit is * cleared and the timestamp status bit is reset in the PHY port memory of * internal PHYs of the 56G devices. * * To directly clear the contents of the timestamp block entirely, discarding * all timestamp data at once, software should instead use * ice_ptp_reset_ts_memory_quad_eth56g(). * * This function should only be called on an idx whose bit is set according to * ice_get_phy_tx_tstamp_ready(). * * Return: * * %0 - success * * %other - failed to write to PHY */ static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) { … } /** * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block * @hw: pointer to the HW struct */ static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) { … } /** * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time * @hw: pointer to the HW struct * @port: port number * @time: time to initialize the PHY port clocks to * * Write a new initial time value into registers of a specific PHY port. * * Return: * * %0 - success * * %other - failed to write to PHY */ static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port, u64 time) { … } /** * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time * @hw: pointer to the HW struct * @time: Time to initialize the PHY port clocks to * * Program the PHY port registers with a new initial time value. The port * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync * command. The time value is the upper 32 bits of the PHY timer, usually in * units of nominal nanoseconds. * * Return: * * %0 - success * * %other - failed to write to PHY */ static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) { … } /** * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust * @hw: pointer to HW struct * @port: Port number to be programmed * @time: time in cycles to adjust the port clocks * * Program the port for an atomic adjustment by writing the Tx and Rx timer * registers. The atomic adjustment won't be completed until the driver issues * an ICE_PTP_ADJ_TIME command. * * Note that time is not in units of nanoseconds. It is in clock time * including the lower sub-nanosecond portion of the port timer. * * Negative adjustments are supported using 2s complement arithmetic. * * Return: * * %0 - success * * %other - failed to write to PHY */ static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time) { … } /** * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment * @hw: pointer to HW struct * @adj: adjustment in nanoseconds * * Prepare the PHY ports for an atomic time adjustment by programming the PHY * Tx and Rx port registers. The actual adjustment is completed by issuing an * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. * * Return: * * %0 - success * * %other - failed to write to PHY */ static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj) { … } /** * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment * @hw: pointer to HW struct * @incval: new increment value to prepare * * Prepare each of the PHY ports for a new increment value by programming the * port's TIMETUS registers. The new increment value will be updated after * issuing an ICE_PTP_INIT_INCVAL command. * * Return: * * %0 - success * * %other - failed to write to PHY */ static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) { … } /** * ice_ptp_read_port_capture_eth56g - Read a port's local time capture * @hw: pointer to HW struct * @port: Port number to read * @tx_ts: on return, the Tx port time capture * @rx_ts: on return, the Rx port time capture * * Read the port's Tx and Rx local time capture values. * * Return: * * %0 - success * * %other - failed to read from PHY */ static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) { … } /** * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command * @hw: pointer to HW struct * @port: Port to which cmd has to be sent * @cmd: Command to be sent to the port * * Prepare the requested port for an upcoming timer sync command. * * Return: * * %0 - success * * %other - failed to write to PHY */ static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd) { … } /** * ice_phy_get_speed_eth56g - Get link speed based on PHY link type * @li: pointer to link information struct * * Return: simplified ETH56G PHY speed */ static enum ice_eth56g_link_spd ice_phy_get_speed_eth56g(struct ice_link_status *li) { … } /** * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle * @hw: pointer to the HW struct * @port: port to configure * * Configure the number of TUs for the PAR and PCS clocks used as part of the * timestamp calibration process. * * Return: * * %0 - success * * %other - PHY read/write failed */ static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port) { … } /** * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings * @hw: Pointer to the HW struct * @port: Port to configure * * Return: * * %0 - success * * %other - PHY read/write failed */ int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port) { … } /** * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values * @a: multiplier value * @b: multiplicand value * * Return: result of multiplication */ static u32 mul_u32_u32_fx_q9(u32 a, u32 b) { … } /** * add_u32_u32_fx - Add two u32 fixed point values and discard overflow * @a: first value * @b: second value * * Return: result of addition */ static u32 add_u32_u32_fx(u32 a, u32 b) { … } /** * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value * @hw: pointer to the HW struct * @port: port to configure * @bs: bitslip multiplier * @fc: FC-FEC enabled * @rs: RS-FEC enabled * @spd: link speed * * Return: calculated bitslip value */ static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs, bool fc, bool rs, enum ice_eth56g_link_spd spd) { … } /** * ice_ptp_calc_deskew_eth56g - Calculate deskew value * @hw: pointer to the HW struct * @port: port to configure * @ds: deskew multiplier * @rs: RS-FEC enabled * @spd: link speed * * Return: calculated deskew value */ static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, bool rs, enum ice_eth56g_link_spd spd) { … } /** * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values * @hw: pointer to the HW struct * @port: port to configure * @spd: link speed * @cfg: structure to store output values * @fc: FC-FEC enabled * @rs: RS-FEC enabled * * Return: * * %0 - success * * %other - failed to write to PHY */ static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, enum ice_eth56g_link_spd spd, const struct ice_eth56g_mac_reg_cfg *cfg, bool fc, bool rs) { … } /** * ice_phy_cfg_mac_eth56g - Configure MAC for PTP * @hw: Pointer to the HW struct * @port: Port to configure * * Return: * * %0 - success * * %other - failed to write to PHY */ static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port) { … } /** * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt * @hw: pointer to the HW struct * @port: the timestamp port * @ena: enable or disable interrupt * @threshold: interrupt threshold * * Configure TX timestamp interrupt for the specified port * * Return: * * %0 - success * * %other - PHY read/write failed */ int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold) { … } /** * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time * @hw: pointer to the HW struct * @port: the PHY port to read * @phy_time: on return, the 64bit PHY timer value * @phc_time: on return, the lower 64bits of PHC time * * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY * and PHC timer values. * * Return: * * %0 - success * * %other - PHY read/write failed */ static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, u64 *phy_time, u64 *phc_time) { … } /** * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer * @hw: pointer to the HW struct * @port: the PHY port to synchronize * * Perform an adjustment to ensure that the PHY and PHC timers are in sync. * This is done by issuing a ICE_PTP_READ_TIME command which triggers a * simultaneous read of the PHY timer and PHC timer. Then we use the * difference to calculate an appropriate 2s complement addition to add * to the PHY timer in order to ensure it reads the same value as the * primary PHC timer. * * Return: * * %0 - success * * %-EBUSY- failed to acquire PTP semaphore * * %other - PHY read/write failed */ static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port) { … } /** * ice_stop_phy_timer_eth56g - Stop the PHY clock timer * @hw: pointer to the HW struct * @port: the PHY port to stop * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS * * Stop the clock of a PHY port. This must be done as part of the flow to * re-calibrate Tx and Rx timestamping offsets whenever the clock time is * initialized or when link speed changes. * * Return: * * %0 - success * * %other - failed to write to PHY */ int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) { … } /** * ice_start_phy_timer_eth56g - Start the PHY clock timer * @hw: pointer to the HW struct * @port: the PHY port to start * * Start the clock of a PHY port. This must be done as part of the flow to * re-calibrate Tx and Rx timestamping offsets whenever the clock time is * initialized or when link speed changes. * * Return: * * %0 - success * * %other - PHY read/write failed */ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) { … } /** * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access * @hw: pointer to HW struct * @enable: Enable or disable access * * Enable sideband devices (PHY and others) access. */ static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) { … } /** * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization * @hw: pointer to HW struct * * Perform PHC initialization steps specific to E82X devices. * * Return: * * %0 - success * * %other - failed to initialize CGU */ static int ice_ptp_init_phc_eth56g(struct ice_hw *hw) { … } /** * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status * @hw: pointer to the HW struct * @ts_status: the timestamp mask pointer * * Read the PHY Tx timestamp status mask indicating which ports have Tx * timestamps available. * * Return: * * %0 - success * * %other - failed to read from PHY */ int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) { … } /** * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register * @hw: pointer to the HW struct * @port: the PHY port to read from * @tstamp_ready: contents of the Tx memory status register * * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in * the PHY are ready. A set bit means the corresponding timestamp is valid and * ready to be captured from the PHY timestamp block. * * Return: * * %0 - success * * %other - failed to read from PHY */ static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, u64 *tstamp_ready) { … } /** * ice_is_muxed_topo - detect breakout 2x50G topology for E825C * @hw: pointer to the HW struct * * Return: true if it's 2x50 breakout topology, false otherwise */ static bool ice_is_muxed_topo(struct ice_hw *hw) { … } /** * ice_ptp_init_phy_e825c - initialize PHY parameters * @hw: pointer to the HW struct */ static void ice_ptp_init_phy_e825c(struct ice_hw *hw) { … } /* E822 family functions * * The following functions operate on the E822 family of devices. */ /** * ice_fill_phy_msg_e82x - Fill message data for a PHY register access * @hw: pointer to the HW struct * @msg: the PHY message buffer to fill in * @port: the port to access * @offset: the register offset */ static void ice_fill_phy_msg_e82x(struct ice_hw *hw, struct ice_sbq_msg_input *msg, u8 port, u16 offset) { … } /** * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register * @low_addr: the low address to check * @high_addr: on return, contains the high address of the 64bit register * * Checks if the provided low address is one of the known 64bit PHY values * represented as two 32bit registers. If it is, return the appropriate high * register offset to use. */ static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr) { … } /** * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register * @low_addr: the low address to check * @high_addr: on return, contains the high address of the 40bit value * * Checks if the provided low address is one of the known 40bit PHY values * split into two registers with the lower 8 bits in the low register and the * upper 32 bits in the high register. If it is, return the appropriate high * register offset to use. */ static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr) { … } /** * ice_read_phy_reg_e82x - Read a PHY register * @hw: pointer to the HW struct * @port: PHY port to read from * @offset: PHY register offset to read * @val: on return, the contents read from the PHY * * Read a PHY register for the given port over the device sideband queue. */ static int ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val) { … } /** * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers * @hw: pointer to the HW struct * @port: PHY port to read from * @low_addr: offset of the lower register to read from * @val: on return, the contents of the 64bit value from the PHY registers * * Reads the two registers associated with a 64bit value and returns it in the * val pointer. The offset always specifies the lower register offset to use. * The high offset is looked up. This function only operates on registers * known to be two parts of a 64bit value. */ static int ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) { … } /** * ice_write_phy_reg_e82x - Write a PHY register * @hw: pointer to the HW struct * @port: PHY port to write to * @offset: PHY register offset to write * @val: The value to write to the register * * Write a PHY register for the given port over the device sideband queue. */ static int ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val) { … } /** * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY * @hw: pointer to the HW struct * @port: port to write to * @low_addr: offset of the low register * @val: 40b value to write * * Write the provided 40b value to the two associated registers by splitting * it up into two chunks, the lower 8 bits and the upper 32 bits. */ static int ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) { … } /** * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers * @hw: pointer to the HW struct * @port: PHY port to read from * @low_addr: offset of the lower register to read from * @val: the contents of the 64bit value to write to PHY * * Write the 64bit value to the two associated 32bit PHY registers. The offset * is always specified as the lower register, and the high address is looked * up. This function only operates on registers known to be two parts of * a 64bit value. */ static int ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) { … } /** * ice_fill_quad_msg_e82x - Fill message data for quad register access * @hw: pointer to the HW struct * @msg: the PHY message buffer to fill in * @quad: the quad to access * @offset: the register offset * * Fill a message buffer for accessing a register in a quad shared between * multiple PHYs. * * Return: * * %0 - OK * * %-EINVAL - invalid quad number */ static int ice_fill_quad_msg_e82x(struct ice_hw *hw, struct ice_sbq_msg_input *msg, u8 quad, u16 offset) { … } /** * ice_read_quad_reg_e82x - Read a PHY quad register * @hw: pointer to the HW struct * @quad: quad to read from * @offset: quad register offset to read * @val: on return, the contents read from the quad * * Read a quad register over the device sideband queue. Quad registers are * shared between multiple PHYs. */ int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) { … } /** * ice_write_quad_reg_e82x - Write a PHY quad register * @hw: pointer to the HW struct * @quad: quad to write to * @offset: quad register offset to write * @val: The value to write to the register * * Write a quad register over the device sideband queue. Quad registers are * shared between multiple PHYs. */ int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val) { … } /** * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block * @hw: pointer to the HW struct * @quad: the quad to read from * @idx: the timestamp index to read * @tstamp: on return, the 40bit timestamp value * * Read a 40bit timestamp value out of the two associated registers in the * quad memory block that is shared between the internal PHYs of the E822 * family of devices. */ static int ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) { … } /** * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block * @hw: pointer to the HW struct * @quad: the quad to read from * @idx: the timestamp index to reset * * Read the timestamp out of the quad to clear its timestamp status bit from * the PHY quad block that is shared between the internal PHYs of the E822 * devices. * * Note that unlike E810, software cannot directly write to the quad memory * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function * to determine which timestamps are valid. Reading a timestamp auto-clears * the valid bit. * * To directly clear the contents of the timestamp block entirely, discarding * all timestamp data at once, software should instead use * ice_ptp_reset_ts_memory_quad_e82x(). * * This function should only be called on an idx whose bit is set according to * ice_get_phy_tx_tstamp_ready(). */ static int ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx) { … } /** * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block * @hw: pointer to the HW struct * @quad: the quad to read from * * Clear all timestamps from the PHY quad block that is shared between the * internal PHYs on the E822 devices. */ void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad) { … } /** * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks * @hw: pointer to the HW struct */ static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw) { … } /** * ice_ptp_set_vernier_wl - Set the window length for vernier calibration * @hw: pointer to the HW struct * * Set the window length used for the vernier port calibration process. */ static int ice_ptp_set_vernier_wl(struct ice_hw *hw) { … } /** * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization * @hw: pointer to HW struct * * Perform PHC initialization steps specific to E822 devices. */ static int ice_ptp_init_phc_e82x(struct ice_hw *hw) { … } /** * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time * @hw: pointer to the HW struct * @time: Time to initialize the PHY port clocks to * * Program the PHY port registers with a new initial time value. The port * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync * command. The time value is the upper 32 bits of the PHY timer, usually in * units of nominal nanoseconds. */ static int ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time) { … } /** * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust * @hw: pointer to HW struct * @port: Port number to be programmed * @time: time in cycles to adjust the port Tx and Rx clocks * * Program the port for an atomic adjustment by writing the Tx and Rx timer * registers. The atomic adjustment won't be completed until the driver issues * an ICE_PTP_ADJ_TIME command. * * Note that time is not in units of nanoseconds. It is in clock time * including the lower sub-nanosecond portion of the port timer. * * Negative adjustments are supported using 2s complement arithmetic. */ static int ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time) { … } /** * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment * @hw: pointer to HW struct * @adj: adjustment in nanoseconds * * Prepare the PHY ports for an atomic time adjustment by programming the PHY * Tx and Rx port registers. The actual adjustment is completed by issuing an * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. */ static int ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj) { … } /** * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment * @hw: pointer to HW struct * @incval: new increment value to prepare * * Prepare each of the PHY ports for a new increment value by programming the * port's TIMETUS registers. The new increment value will be updated after * issuing an ICE_PTP_INIT_INCVAL command. */ static int ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval) { … } /** * ice_ptp_read_port_capture - Read a port's local time capture * @hw: pointer to HW struct * @port: Port number to read * @tx_ts: on return, the Tx port time capture * @rx_ts: on return, the Rx port time capture * * Read the port's Tx and Rx local time capture values. * * Note this has no equivalent for the E810 devices. */ static int ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) { … } /** * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command * @hw: pointer to HW struct * @port: Port to which cmd has to be sent * @cmd: Command to be sent to the port * * Prepare the requested port for an upcoming timer sync command. * * Note there is no equivalent of this operation on E810, as that device * always handles all external PHYs internally. * * Return: * * %0 - success * * %other - failed to write to PHY */ static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd) { … } /* E822 Vernier calibration functions * * The following functions are used as part of the vernier calibration of * a port. This calibration increases the precision of the timestamps on the * port. */ /** * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode * @hw: pointer to HW struct * @port: the port to read from * @link_out: if non-NULL, holds link speed on success * @fec_out: if non-NULL, holds FEC algorithm on success * * Read the serdes data for the PHY port and extract the link speed and FEC * algorithm. */ static int ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port, enum ice_ptp_link_spd *link_out, enum ice_ptp_fec_mode *fec_out) { … } /** * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp * @hw: pointer to HW struct * @port: to configure the quad for */ static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port) { … } /** * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822 * @hw: pointer to the HW structure * @port: the port to configure * * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC * hardware clock time units (TUs). That is, determine the number of TUs per * serdes unit interval, and program the UIX registers with this conversion. * * This conversion is used as part of the calibration process when determining * the additional error of a timestamp vs the real time of transmission or * receipt of the packet. * * Hardware uses the number of TUs per 66 UIs, written to the UIX registers * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. * * To calculate the conversion ratio, we use the following facts: * * a) the clock frequency in Hz (cycles per second) * b) the number of TUs per cycle (the increment value of the clock) * c) 1 second per 1 billion nanoseconds * d) the duration of 66 UIs in nanoseconds * * Given these facts, we can use the following table to work out what ratios * to multiply in order to get the number of TUs per 66 UIs: * * cycles | 1 second | incval (TUs) | nanoseconds * -------+--------------+--------------+------------- * second | 1 billion ns | cycle | 66 UIs * * To perform the multiplication using integers without too much loss of * precision, we can take use the following equation: * * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) * * We scale up to using 6600 UI instead of 66 in order to avoid fractional * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) * * The increment value has a maximum expected range of about 34 bits, while * the frequency value is about 29 bits. Multiplying these values shouldn't * overflow the 64 bits. However, we must then further multiply them again by * the Serdes unit interval duration. To avoid overflow here, we split the * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and * a divide by 390,625,000. This does lose some precision, but avoids * miscalculation due to arithmetic overflow. */ static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port) { … } /** * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle * @hw: pointer to the HW struct * @port: port to configure * * Configure the number of TUs for the PAR and PCS clocks used as part of the * timestamp calibration process. This depends on the link speed, as the PHY * uses different markers depending on the speed. * * 1Gb/10Gb/25Gb: * - Tx/Rx PAR/PCS markers * * 25Gb RS: * - Tx/Rx Reed Solomon gearbox PAR/PCS markers * * 40Gb/50Gb: * - Tx/Rx PAR/PCS markers * - Rx Deskew PAR/PCS markers * * 50G RS and 100GB RS: * - Tx/Rx Reed Solomon gearbox PAR/PCS markers * - Rx Deskew PAR/PCS markers * - Tx PAR/PCS markers * * To calculate the conversion, we use the PHC clock frequency (cycles per * second), the increment value (TUs per cycle), and the related PHY clock * frequency to calculate the TUs per unit of the PHY link clock. The * following table shows how the units convert: * * cycles | TUs | second * -------+-------+-------- * second | cycle | cycles * * For each conversion register, look up the appropriate frequency from the * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program * this to the appropriate register, preparing hardware to perform timestamp * calibration to calculate the total Tx or Rx offset to adjust the timestamp * in order to calibrate for the internal PHY delays. * * Note that the increment value ranges up to ~34 bits, and the clock * frequency is ~29 bits, so multiplying them together should fit within the * 64 bit arithmetic. */ static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port) { … } /** * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port * @hw: pointer to the HW struct * @link_spd: the Link speed to calculate for * * Calculate the fixed offset due to known static latency data. */ static u64 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) { … } /** * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset * @hw: pointer to the HW struct * @port: the PHY port to configure * * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to * adjust Tx timestamps by. This is calculated by combining some known static * latency along with the Vernier offset computations done by hardware. * * This function will not return successfully until the Tx offset calculations * have been completed, which requires waiting until at least one packet has * been transmitted by the device. It is safe to call this function * periodically until calibration succeeds, as it will only program the offset * once. * * To avoid overflow, when calculating the offset based on the known static * latency values, we use measurements in 1/100th of a nanosecond, and divide * the TUs per second up front. This avoids overflow while allowing * calculation of the adjustment using integer arithmetic. * * Returns zero on success, -EBUSY if the hardware vernier offset * calibration has not completed, or another error code on failure. */ int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port) { … } /** * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx * @hw: pointer to the HW struct * @port: the PHY port to adjust for * @link_spd: the current link speed of the PHY * @fec_mode: the current FEC mode of the PHY * @pmd_adj: on return, the amount to adjust the Rx total offset by * * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY. * This varies by link speed and FEC mode. The value calculated accounts for * various delays caused when receiving a packet. */ static int ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port, enum ice_ptp_link_spd link_spd, enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) { … } /** * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port * @hw: pointer to HW struct * @link_spd: The Link speed to calculate for * * Determine the fixed Rx latency for a given link speed. */ static u64 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) { … } /** * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset * @hw: pointer to the HW struct * @port: the PHY port to configure * * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to * adjust Rx timestamps by. This combines calculations from the Vernier offset * measurements taken in hardware with some data about known fixed delay as * well as adjusting for multi-lane alignment delay. * * This function will not return successfully until the Rx offset calculations * have been completed, which requires waiting until at least one packet has * been received by the device. It is safe to call this function periodically * until calibration succeeds, as it will only program the offset once. * * This function must be called only after the offset registers are valid, * i.e. after the Vernier calibration wait has passed, to ensure that the PHY * has measured the offset. * * To avoid overflow, when calculating the offset based on the known static * latency values, we use measurements in 1/100th of a nanosecond, and divide * the TUs per second up front. This avoids overflow while allowing * calculation of the adjustment using integer arithmetic. * * Returns zero on success, -EBUSY if the hardware vernier offset * calibration has not completed, or another error code on failure. */ int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port) { … } /** * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers * @hw: pointer to the HW struct * * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted * and received timestamps as invalid. * * Return: 0 on success, other error codes when failed to write to PHY */ int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw) { … } /** * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time * @hw: pointer to the HW struct * @port: the PHY port to read * @phy_time: on return, the 64bit PHY timer value * @phc_time: on return, the lower 64bits of PHC time * * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY * and PHC timer values. */ static int ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time, u64 *phc_time) { … } /** * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer * @hw: pointer to the HW struct * @port: the PHY port to synchronize * * Perform an adjustment to ensure that the PHY and PHC timers are in sync. * This is done by issuing a ICE_PTP_READ_TIME command which triggers a * simultaneous read of the PHY timer and PHC timer. Then we use the * difference to calculate an appropriate 2s complement addition to add * to the PHY timer in order to ensure it reads the same value as the * primary PHC timer. */ static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port) { … } /** * ice_stop_phy_timer_e82x - Stop the PHY clock timer * @hw: pointer to the HW struct * @port: the PHY port to stop * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS * * Stop the clock of a PHY port. This must be done as part of the flow to * re-calibrate Tx and Rx timestamping offsets whenever the clock time is * initialized or when link speed changes. */ int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset) { … } /** * ice_start_phy_timer_e82x - Start the PHY clock timer * @hw: pointer to the HW struct * @port: the PHY port to start * * Start the clock of a PHY port. This must be done as part of the flow to * re-calibrate Tx and Rx timestamping offsets whenever the clock time is * initialized or when link speed changes. * * Hardware will take Vernier measurements on Tx or Rx of packets. */ int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port) { … } /** * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register * @hw: pointer to the HW struct * @quad: the timestamp quad to read from * @tstamp_ready: contents of the Tx memory status register * * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in * the PHY are ready. A set bit means the corresponding timestamp is valid and * ready to be captured from the PHY timestamp block. */ static int ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) { … } /** * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt * @hw: pointer to the HW struct * @quad: the timestamp quad * @ena: enable or disable interrupt * @threshold: interrupt threshold * * Configure TX timestamp interrupt for the specified quad * * Return: 0 on success, other error codes when failed to read/write quad */ int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) { … } /** * ice_ptp_init_phy_e82x - initialize PHY parameters * @ptp: pointer to the PTP HW struct */ static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp) { … } /* E810 functions * * The following functions operate on the E810 series devices which use * a separate external PHY. */ /** * ice_read_phy_reg_e810 - Read register from external PHY on E810 * @hw: pointer to the HW struct * @addr: the address to read from * @val: On return, the value read from the PHY * * Read a register from the external PHY on the E810 device. */ static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) { … } /** * ice_write_phy_reg_e810 - Write register on external PHY on E810 * @hw: pointer to the HW struct * @addr: the address to writem to * @val: the value to write to the PHY * * Write a value to a register of the external PHY on the E810 device. */ static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) { … } /** * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW * @hw: pointer to the HW struct * @idx: the timestamp index to read * @hi: 8 bit timestamp high value * @lo: 32 bit timestamp low value * * Read a 8bit timestamp high value and 32 bit timestamp low value out of the * timestamp block of the external PHY on the E810 device using the low latency * timestamp read. */ static int ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) { … } /** * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq * @hw: pointer to the HW struct * @lport: the lport to read from * @idx: the timestamp index to read * @hi: 8 bit timestamp high value * @lo: 32 bit timestamp low value * * Read a 8bit timestamp high value and 32 bit timestamp low value out of the * timestamp block of the external PHY on the E810 device using sideband queue. */ static int ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, u32 *lo) { … } /** * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY * @hw: pointer to the HW struct * @lport: the lport to read from * @idx: the timestamp index to read * @tstamp: on return, the 40bit timestamp value * * Read a 40bit timestamp value out of the timestamp block of the external PHY * on the E810 device. */ static int ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) { … } /** * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY * @hw: pointer to the HW struct * @lport: the lport to read from * @idx: the timestamp index to reset * * Read the timestamp and then forcibly overwrite its value to clear the valid * bit from the timestamp block of the external PHY on the E810 device. * * This function should only be called on an idx whose bit is set according to * ice_get_phy_tx_tstamp_ready(). */ static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) { … } /** * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization * @hw: pointer to HW struct * * Perform E810-specific PTP hardware clock initialization steps. * * Return: 0 on success, other error codes when failed to initialize TimeSync */ static int ice_ptp_init_phc_e810(struct ice_hw *hw) { … } /** * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time * @hw: Board private structure * @time: Time to initialize the PHY port clock to * * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the * initial clock time. The time will not actually be programmed until the * driver issues an ICE_PTP_INIT_TIME command. * * The time value is the upper 32 bits of the PHY timer, usually in units of * nominal nanoseconds. */ static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) { … } /** * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment * @hw: pointer to HW struct * @adj: adjustment value to program * * Prepare the PHY port for an atomic adjustment by programming the PHY * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment * is completed by issuing an ICE_PTP_ADJ_TIME sync command. * * The adjustment value only contains the portion used for the upper 32bits of * the PHY timer, usually in units of nominal nanoseconds. Negative * adjustments are supported using 2s complement arithmetic. */ static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) { … } /** * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change * @hw: pointer to HW struct * @incval: The new 40bit increment value to prepare * * Prepare the PHY port for a new increment value by programming the PHY * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is * completed by issuing an ICE_PTP_INIT_INCVAL command. */ static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) { … } /** * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command * @hw: pointer to HW struct * @cmd: Command to be sent to the port * * Prepare the external PHYs connected to this device for a timer sync * command. */ static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) { … } /** * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register * @hw: pointer to the HW struct * @port: the PHY port to read * @tstamp_ready: contents of the Tx memory status register * * E810 devices do not use a Tx memory status register. Instead simply * indicate that all timestamps are currently ready. */ static int ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) { … } /* E810T SMA functions * * The following functions operate specifically on E810T hardware and are used * to access the extended GPIOs available. */ /** * ice_get_pca9575_handle * @hw: pointer to the hw struct * @pca9575_handle: GPIO controller's handle * * Find and return the GPIO controller's handle in the netlist. * When found - the value will be cached in the hw structure and following calls * will return cached value */ static int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) { … } /** * ice_read_sma_ctrl_e810t * @hw: pointer to the hw struct * @data: pointer to data to be read from the GPIO controller * * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the * PCA9575 expander, so only bits 3-7 in data are valid. */ int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data) { … } /** * ice_write_sma_ctrl_e810t * @hw: pointer to the hw struct * @data: data to be written to the GPIO controller * * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 * of the PCA9575 expander, so only bits 3-7 in data are valid. */ int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data) { … } /** * ice_read_pca9575_reg_e810t * @hw: pointer to the hw struct * @offset: GPIO controller register offset * @data: pointer to data to be read from the GPIO controller * * Read the register from the GPIO controller */ int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data) { … } /** * ice_ptp_init_phy_e810 - initialize PHY parameters * @ptp: pointer to the PTP HW struct */ static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) { … } /* Device agnostic functions * * The following functions implement shared behavior common to both E822 and * E810 devices, possibly calling a device specific implementation where * necessary. */ /** * ice_ptp_lock - Acquire PTP global semaphore register lock * @hw: pointer to the HW struct * * Acquire the global PTP hardware semaphore lock. Returns true if the lock * was acquired, false otherwise. * * The PFTSYN_SEM register sets the busy bit on read, returning the previous * value. If software sees the busy bit cleared, this means that this function * acquired the lock (and the busy bit is now set). If software sees the busy * bit set, it means that another function acquired the lock. * * Software must clear the busy bit with a write to release the lock for other * functions when done. */ bool ice_ptp_lock(struct ice_hw *hw) { … } /** * ice_ptp_unlock - Release PTP global semaphore register lock * @hw: pointer to the HW struct * * Release the global PTP hardware semaphore lock. This is done by writing to * the PFTSYN_SEM register. */ void ice_ptp_unlock(struct ice_hw *hw) { … } /** * ice_ptp_init_hw - Initialize hw based on device type * @hw: pointer to the HW structure * * Determine the PHY model for the device, and initialize hw * for use by other functions. */ void ice_ptp_init_hw(struct ice_hw *hw) { … } /** * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command * @hw: pointer to HW struct * @port: Port to which cmd has to be sent * @cmd: Command to be sent to the port * * Prepare one port for the upcoming timer sync command. Do not use this for * programming only a single port, instead use ice_ptp_one_port_cmd() to * ensure non-modified ports get properly initialized to ICE_PTP_NOP. * * Return: * * %0 - success * %-EBUSY - PHY type not supported * * %other - failed to write port command */ static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd) { … } /** * ice_ptp_one_port_cmd - Program one PHY port for a timer command * @hw: pointer to HW struct * @configured_port: the port that should execute the command * @configured_cmd: the command to be executed on the configured port * * Prepare one port for executing a timer command, while preparing all other * ports to ICE_PTP_NOP. This allows executing a command on a single port * while ensuring all other ports do not execute stale commands. * * Return: * * %0 - success * * %other - failed to write port command */ int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, enum ice_ptp_tmr_cmd configured_cmd) { … } /** * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command * @hw: pointer to HW struct * @cmd: the timer command to setup * * Prepare all PHY ports on this device for the requested timer command. For * some families this can be done in one shot, but for other families each * port must be configured individually. * * Return: * * %0 - success * * %other - failed to write port command */ static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) { … } /** * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command * @hw: pointer to HW struct * @cmd: the command to issue * * Prepare the source timer and PHY timers and then trigger the requested * command. This causes the shadow registers previously written in preparation * for the command to be synchronously applied to both the source and PHY * timers. */ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) { … } /** * ice_ptp_init_time - Initialize device time to provided value * @hw: pointer to HW struct * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) * * Initialize the device to the specified time provided. This requires a three * step process: * * 1) write the new init time to the source timer shadow registers * 2) write the new init time to the PHY timer shadow registers * 3) issue an init_time timer command to synchronously switch both the source * and port timers to the new init time value at the next clock cycle. */ int ice_ptp_init_time(struct ice_hw *hw, u64 time) { … } /** * ice_ptp_write_incval - Program PHC with new increment value * @hw: pointer to HW struct * @incval: Source timer increment value per clock cycle * * Program the PHC with a new increment value. This requires a three-step * process: * * 1) Write the increment value to the source timer shadow registers * 2) Write the increment value to the PHY timer shadow registers * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both * the source and port timers to the new increment value at the next clock * cycle. */ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) { … } /** * ice_ptp_write_incval_locked - Program new incval while holding semaphore * @hw: pointer to HW struct * @incval: Source timer increment value per clock cycle * * Program a new PHC incval while holding the PTP semaphore. */ int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) { … } /** * ice_ptp_adj_clock - Adjust PHC clock time atomically * @hw: pointer to HW struct * @adj: Adjustment in nanoseconds * * Perform an atomic adjustment of the PHC time by the specified number of * nanoseconds. This requires a three-step process: * * 1) Write the adjustment to the source timer shadow registers * 2) Write the adjustment to the PHY timer shadow registers * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the * adjustment to both the source and port timers at the next clock cycle. */ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) { … } /** * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block * @hw: pointer to the HW struct * @block: the block to read from * @idx: the timestamp index to read * @tstamp: on return, the 40bit timestamp value * * Read a 40bit timestamp value out of the timestamp block. For E822 devices, * the block is the quad to read from. For E810 devices, the block is the * logical port to read from. */ int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) { … } /** * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block * @hw: pointer to the HW struct * @block: the block to read from * @idx: the timestamp index to reset * * Clear a timestamp from the timestamp block, discarding its value without * returning it. This resets the memory status bit for the timestamp index * allowing it to be reused for another timestamp in the future. * * For E822 devices, the block number is the PHY quad to clear from. For E810 * devices, the block number is the logical port to clear from. * * This function must only be called on a timestamp index whose valid bit is * set according to ice_get_phy_tx_tstamp_ready(). */ int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) { … } /** * ice_get_pf_c827_idx - find and return the C827 index for the current pf * @hw: pointer to the hw struct * @idx: index of the found C827 PHY * Return: * * 0 - success * * negative - failure */ static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx) { … } /** * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks * @hw: pointer to the HW struct */ void ice_ptp_reset_ts_memory(struct ice_hw *hw) { … } /** * ice_ptp_init_phc - Initialize PTP hardware clock * @hw: pointer to the HW struct * * Perform the steps required to initialize the PTP hardware clock. */ int ice_ptp_init_phc(struct ice_hw *hw) { … } /** * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication * @hw: pointer to the HW struct * @block: the timestamp block to check * @tstamp_ready: storage for the PHY Tx memory status information * * Check the PHY for Tx timestamp memory status. This reports a 64 bit value * which indicates which timestamps in the block may be captured. A set bit * means the timestamp can be read. An unset bit means the timestamp is not * ready and software should avoid reading the register. */ int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) { … } /** * ice_cgu_get_pin_desc_e823 - get pin description array * @hw: pointer to the hw struct * @input: if request is done against input or output pin * @size: number of inputs/outputs * * Return: pointer to pin description array associated to given hw. */ static const struct ice_cgu_pin_desc * ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size) { … } /** * ice_cgu_get_pin_desc - get pin description array * @hw: pointer to the hw struct * @input: if request is done against input or output pins * @size: size of array returned by function * * Return: pointer to pin description array associated to given hw. */ static const struct ice_cgu_pin_desc * ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size) { … } /** * ice_cgu_get_num_pins - get pin description array size * @hw: pointer to the hw struct * @input: if request is done against input or output pins * * Return: size of pin description array for given hw. */ int ice_cgu_get_num_pins(struct ice_hw *hw, bool input) { … } /** * ice_cgu_get_pin_type - get pin's type * @hw: pointer to the hw struct * @pin: pin index * @input: if request is done against input or output pin * * Return: type of a pin. */ enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input) { … } /** * ice_cgu_get_pin_freq_supp - get pin's supported frequency * @hw: pointer to the hw struct * @pin: pin index * @input: if request is done against input or output pin * @num: output number of supported frequencies * * Get frequency supported number and array of supported frequencies. * * Return: array of supported frequencies for given pin. */ struct dpll_pin_frequency * ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num) { … } /** * ice_cgu_get_pin_name - get pin's name * @hw: pointer to the hw struct * @pin: pin index * @input: if request is done against input or output pin * * Return: * * null terminated char array with name * * NULL in case of failure */ const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input) { … } /** * ice_get_cgu_state - get the state of the DPLL * @hw: pointer to the hw struct * @dpll_idx: Index of internal DPLL unit * @last_dpll_state: last known state of DPLL * @pin: pointer to a buffer for returning currently active pin * @ref_state: reference clock state * @eec_mode: eec mode of the DPLL * @phase_offset: pointer to a buffer for returning phase offset * @dpll_state: state of the DPLL (output) * * This function will read the state of the DPLL(dpll_idx). Non-null * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to * retrieve currently active pin, state, mode and phase_offset respectively. * * Return: state of the DPLL */ int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, enum dpll_lock_status last_dpll_state, u8 *pin, u8 *ref_state, u8 *eec_mode, s64 *phase_offset, enum dpll_lock_status *dpll_state) { … } /** * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins * @hw: pointer to the hw struct * @base_idx: returns index of first recovered clock pin on device * @pin_num: returns number of recovered clock pins available on device * * Based on hw provide caller info about recovery clock pins available on the * board. * * Return: * * 0 - success, information is valid * * negative - failure, information is not valid */ int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num) { … } /** * ice_cgu_get_output_pin_state_caps - get output pin state capabilities * @hw: pointer to the hw struct * @pin_id: id of a pin * @caps: capabilities to modify * * Return: * * 0 - success, state capabilities were modified * * negative - failure, capabilities were not modified */ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, unsigned long *caps) { … }
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