/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2023 Intel Corporation */ #ifndef _IDPF_LAN_PF_REGS_H_ #define _IDPF_LAN_PF_REGS_H_ /* Receive queues */ #define PF_QRX_BASE … #define PF_QRX_TAIL(_QRX) … #define PF_QRX_BUFFQ_BASE … #define PF_QRX_BUFFQ_TAIL(_QRX) … /* Transmit queues */ #define PF_QTX_BASE … #define PF_QTX_COMM_DBELL(_DBQM) … /* Control(PF Mailbox) Queue */ #define PF_FW_BASE … #define PF_FW_ARQBAL … #define PF_FW_ARQBAH … #define PF_FW_ARQLEN … #define PF_FW_ARQLEN_ARQLEN_S … #define PF_FW_ARQLEN_ARQLEN_M … #define PF_FW_ARQLEN_ARQVFE_S … #define PF_FW_ARQLEN_ARQVFE_M … #define PF_FW_ARQLEN_ARQOVFL_S … #define PF_FW_ARQLEN_ARQOVFL_M … #define PF_FW_ARQLEN_ARQCRIT_S … #define PF_FW_ARQLEN_ARQCRIT_M … #define PF_FW_ARQLEN_ARQENABLE_S … #define PF_FW_ARQLEN_ARQENABLE_M … #define PF_FW_ARQH … #define PF_FW_ARQH_ARQH_S … #define PF_FW_ARQH_ARQH_M … #define PF_FW_ARQT … #define PF_FW_ATQBAL … #define PF_FW_ATQBAH … #define PF_FW_ATQLEN … #define PF_FW_ATQLEN_ATQLEN_S … #define PF_FW_ATQLEN_ATQLEN_M … #define PF_FW_ATQLEN_ATQVFE_S … #define PF_FW_ATQLEN_ATQVFE_M … #define PF_FW_ATQLEN_ATQOVFL_S … #define PF_FW_ATQLEN_ATQOVFL_M … #define PF_FW_ATQLEN_ATQCRIT_S … #define PF_FW_ATQLEN_ATQCRIT_M … #define PF_FW_ATQLEN_ATQENABLE_S … #define PF_FW_ATQLEN_ATQENABLE_M … #define PF_FW_ATQH … #define PF_FW_ATQH_ATQH_S … #define PF_FW_ATQH_ATQH_M … #define PF_FW_ATQT … /* Interrupts */ #define PF_GLINT_BASE … #define PF_GLINT_DYN_CTL(_INT) … #define PF_GLINT_DYN_CTL_INTENA_S … #define PF_GLINT_DYN_CTL_INTENA_M … #define PF_GLINT_DYN_CTL_CLEARPBA_S … #define PF_GLINT_DYN_CTL_CLEARPBA_M … #define PF_GLINT_DYN_CTL_SWINT_TRIG_S … #define PF_GLINT_DYN_CTL_SWINT_TRIG_M … #define PF_GLINT_DYN_CTL_ITR_INDX_S … #define PF_GLINT_DYN_CTL_ITR_INDX_M … #define PF_GLINT_DYN_CTL_INTERVAL_S … #define PF_GLINT_DYN_CTL_INTERVAL_M … #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S … #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_M … #define PF_GLINT_DYN_CTL_SW_ITR_INDX_S … #define PF_GLINT_DYN_CTL_SW_ITR_INDX_M … #define PF_GLINT_DYN_CTL_WB_ON_ITR_S … #define PF_GLINT_DYN_CTL_WB_ON_ITR_M … #define PF_GLINT_DYN_CTL_INTENA_MSK_S … #define PF_GLINT_DYN_CTL_INTENA_MSK_M … /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is * spacing b/w itrn registers of the same vector. */ #define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) … /* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */ #define PF_GLINT_ITR(_ITR, _INT) … #define PF_GLINT_ITR_MAX_INDEX … #define PF_GLINT_ITR_INTERVAL_S … #define PF_GLINT_ITR_INTERVAL_M … /* Generic registers */ #define PF_INT_DIR_OICR_ENA … #define PF_INT_DIR_OICR_ENA_S … #define PF_INT_DIR_OICR_ENA_M … #define PF_INT_DIR_OICR … #define PF_INT_DIR_OICR_TSYN_EVNT … #define PF_INT_DIR_OICR_PHY_TS_0 … #define PF_INT_DIR_OICR_PHY_TS_1 … #define PF_INT_DIR_OICR_CAUSE … #define PF_INT_DIR_OICR_CAUSE_CAUSE_S … #define PF_INT_DIR_OICR_CAUSE_CAUSE_M … #define PF_INT_PBA_CLEAR … #define PF_FUNC_RID … #define PF_FUNC_RID_FUNCTION_NUMBER_S … #define PF_FUNC_RID_FUNCTION_NUMBER_M … #define PF_FUNC_RID_DEVICE_NUMBER_S … #define PF_FUNC_RID_DEVICE_NUMBER_M … #define PF_FUNC_RID_BUS_NUMBER_S … #define PF_FUNC_RID_BUS_NUMBER_M … /* Reset registers */ #define PFGEN_RTRIG … #define PFGEN_RTRIG_CORER_S … #define PFGEN_RTRIG_CORER_M … #define PFGEN_RTRIG_LINKR_S … #define PFGEN_RTRIG_LINKR_M … #define PFGEN_RTRIG_IMCR_S … #define PFGEN_RTRIG_IMCR_M … #define PFGEN_RSTAT … #define PFGEN_RSTAT_PFR_STATE_S … #define PFGEN_RSTAT_PFR_STATE_M … #define PFGEN_CTRL … #define PFGEN_CTRL_PFSWR … #endif
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