// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 1999 - 2010 Intel Corporation. * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. * * This code was derived from the Intel e1000e Linux driver. */ #include "pch_gbe.h" #include "pch_gbe_phy.h" #define PHY_MAX_REG_ADDRESS … /* PHY 1000 MII Register/Bit Definitions */ /* PHY Registers defined by IEEE */ #define PHY_CONTROL … #define PHY_STATUS … #define PHY_ID1 … #define PHY_ID2 … #define PHY_AUTONEG_ADV … #define PHY_LP_ABILITY … #define PHY_AUTONEG_EXP … #define PHY_NEXT_PAGE_TX … #define PHY_LP_NEXT_PAGE … #define PHY_1000T_CTRL … #define PHY_1000T_STATUS … #define PHY_EXT_STATUS … #define PHY_PHYSP_CONTROL … #define PHY_EXT_PHYSP_CONTROL … #define PHY_LED_CONTROL … #define PHY_EXT_PHYSP_STATUS … /* PHY Control Register */ #define MII_CR_SPEED_SELECT_MSB … #define MII_CR_COLL_TEST_ENABLE … #define MII_CR_FULL_DUPLEX … #define MII_CR_RESTART_AUTO_NEG … #define MII_CR_ISOLATE … #define MII_CR_POWER_DOWN … #define MII_CR_AUTO_NEG_EN … #define MII_CR_SPEED_SELECT_LSB … #define MII_CR_LOOPBACK … #define MII_CR_RESET … #define MII_CR_SPEED_1000 … #define MII_CR_SPEED_100 … #define MII_CR_SPEED_10 … /* PHY Status Register */ #define MII_SR_EXTENDED_CAPS … #define MII_SR_JABBER_DETECT … #define MII_SR_LINK_STATUS … #define MII_SR_AUTONEG_CAPS … #define MII_SR_REMOTE_FAULT … #define MII_SR_AUTONEG_COMPLETE … #define MII_SR_PREAMBLE_SUPPRESS … #define MII_SR_EXTENDED_STATUS … #define MII_SR_100T2_HD_CAPS … #define MII_SR_100T2_FD_CAPS … #define MII_SR_10T_HD_CAPS … #define MII_SR_10T_FD_CAPS … #define MII_SR_100X_HD_CAPS … #define MII_SR_100X_FD_CAPS … #define MII_SR_100T4_CAPS … /* AR8031 PHY Debug Registers */ #define PHY_AR803X_ID … #define PHY_AR8031_DBG_OFF … #define PHY_AR8031_DBG_DAT … #define PHY_AR8031_SERDES … #define PHY_AR8031_HIBERNATE … #define PHY_AR8031_SERDES_TX_CLK_DLY … #define PHY_AR8031_PS_HIB_EN … /* Phy Id Register (word 2) */ #define PHY_REVISION_MASK … /* PHY Specific Control Register */ #define PHYSP_CTRL_ASSERT_CRS_TX … /* Default value of PHY register */ #define PHY_CONTROL_DEFAULT … #define PHY_AUTONEG_ADV_DEFAULT … #define PHY_NEXT_PAGE_TX_DEFAULT … #define PHY_1000T_CTRL_DEFAULT … #define PHY_PHYSP_CONTROL_DEFAULT … /** * pch_gbe_phy_get_id - Retrieve the PHY ID and revision * @hw: Pointer to the HW structure * Returns * 0: Successful. * Negative value: Failed. */ s32 pch_gbe_phy_get_id(struct pch_gbe_hw *hw) { … } /** * pch_gbe_phy_read_reg_miic - Read MII control register * @hw: Pointer to the HW structure * @offset: Register offset to be read * @data: Pointer to the read data * Returns * 0: Successful. * -EINVAL: Invalid argument. */ s32 pch_gbe_phy_read_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 *data) { … } /** * pch_gbe_phy_write_reg_miic - Write MII control register * @hw: Pointer to the HW structure * @offset: Register offset to be read * @data: data to write to register at offset * Returns * 0: Successful. * -EINVAL: Invalid argument. */ s32 pch_gbe_phy_write_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 data) { … } /** * pch_gbe_phy_sw_reset - PHY software reset * @hw: Pointer to the HW structure */ static void pch_gbe_phy_sw_reset(struct pch_gbe_hw *hw) { … } /** * pch_gbe_phy_hw_reset - PHY hardware reset * @hw: Pointer to the HW structure */ void pch_gbe_phy_hw_reset(struct pch_gbe_hw *hw) { … } /** * pch_gbe_phy_power_up - restore link in case the phy was powered down * @hw: Pointer to the HW structure */ void pch_gbe_phy_power_up(struct pch_gbe_hw *hw) { … } /** * pch_gbe_phy_power_down - Power down PHY * @hw: Pointer to the HW structure */ void pch_gbe_phy_power_down(struct pch_gbe_hw *hw) { … } /** * pch_gbe_phy_set_rgmii - RGMII interface setting * @hw: Pointer to the HW structure */ void pch_gbe_phy_set_rgmii(struct pch_gbe_hw *hw) { … } /** * pch_gbe_phy_tx_clk_delay - Setup TX clock delay via the PHY * @hw: Pointer to the HW structure * Returns * 0: Successful. * -EINVAL: Invalid argument. */ static int pch_gbe_phy_tx_clk_delay(struct pch_gbe_hw *hw) { … } /** * pch_gbe_phy_init_setting - PHY initial setting * @hw: Pointer to the HW structure */ void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw) { … } /** * pch_gbe_phy_disable_hibernate - Disable the PHY low power state * @hw: Pointer to the HW structure * Returns * 0: Successful. * -EINVAL: Invalid argument. */ int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw) { … }
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