/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Copyright (C) 2004 - 2009 Ivo van Doorn <[email protected]> <http://rt2x00.serialmonkey.com> */ /* Module: rt2500pci Abstract: Data structures and registers for the rt2500pci module. Supported chipsets: RT2560. */ #ifndef RT2500PCI_H #define RT2500PCI_H /* * RF chip defines. */ #define RF2522 … #define RF2523 … #define RF2524 … #define RF2525 … #define RF2525E … #define RF5222 … /* * RT2560 version */ #define RT2560_VERSION_B … #define RT2560_VERSION_C … #define RT2560_VERSION_D … /* * Signal information. * Default offset is required for RSSI <-> dBm conversion. */ #define DEFAULT_RSSI_OFFSET … /* * Register layout information. */ #define CSR_REG_BASE … #define CSR_REG_SIZE … #define EEPROM_BASE … #define EEPROM_SIZE … #define BBP_BASE … #define BBP_SIZE … #define RF_BASE … #define RF_SIZE … /* * Number of TX queues. */ #define NUM_TX_QUEUES … /* * Control/Status Registers(CSR). * Some values are set in TU, whereas 1 TU == 1024 us. */ /* * CSR0: ASIC revision number. */ #define CSR0 … #define CSR0_REVISION … /* * CSR1: System control register. * SOFT_RESET: Software reset, 1: reset, 0: normal. * BBP_RESET: Hardware reset, 1: reset, 0, release. * HOST_READY: Host ready after initialization. */ #define CSR1 … #define CSR1_SOFT_RESET … #define CSR1_BBP_RESET … #define CSR1_HOST_READY … /* * CSR2: System admin status register (invalid). */ #define CSR2 … /* * CSR3: STA MAC address register 0. */ #define CSR3 … #define CSR3_BYTE0 … #define CSR3_BYTE1 … #define CSR3_BYTE2 … #define CSR3_BYTE3 … /* * CSR4: STA MAC address register 1. */ #define CSR4 … #define CSR4_BYTE4 … #define CSR4_BYTE5 … /* * CSR5: BSSID register 0. */ #define CSR5 … #define CSR5_BYTE0 … #define CSR5_BYTE1 … #define CSR5_BYTE2 … #define CSR5_BYTE3 … /* * CSR6: BSSID register 1. */ #define CSR6 … #define CSR6_BYTE4 … #define CSR6_BYTE5 … /* * CSR7: Interrupt source register. * Write 1 to clear. * TBCN_EXPIRE: Beacon timer expired interrupt. * TWAKE_EXPIRE: Wakeup timer expired interrupt. * TATIMW_EXPIRE: Timer of atim window expired interrupt. * TXDONE_TXRING: Tx ring transmit done interrupt. * TXDONE_ATIMRING: Atim ring transmit done interrupt. * TXDONE_PRIORING: Priority ring transmit done interrupt. * RXDONE: Receive done interrupt. * DECRYPTION_DONE: Decryption done interrupt. * ENCRYPTION_DONE: Encryption done interrupt. * UART1_TX_TRESHOLD: UART1 TX reaches threshold. * UART1_RX_TRESHOLD: UART1 RX reaches threshold. * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold. * UART1_TX_BUFF_ERROR: UART1 TX buffer error. * UART1_RX_BUFF_ERROR: UART1 RX buffer error. * UART2_TX_TRESHOLD: UART2 TX reaches threshold. * UART2_RX_TRESHOLD: UART2 RX reaches threshold. * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold. * UART2_TX_BUFF_ERROR: UART2 TX buffer error. * UART2_RX_BUFF_ERROR: UART2 RX buffer error. * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period). */ #define CSR7 … #define CSR7_TBCN_EXPIRE … #define CSR7_TWAKE_EXPIRE … #define CSR7_TATIMW_EXPIRE … #define CSR7_TXDONE_TXRING … #define CSR7_TXDONE_ATIMRING … #define CSR7_TXDONE_PRIORING … #define CSR7_RXDONE … #define CSR7_DECRYPTION_DONE … #define CSR7_ENCRYPTION_DONE … #define CSR7_UART1_TX_TRESHOLD … #define CSR7_UART1_RX_TRESHOLD … #define CSR7_UART1_IDLE_TRESHOLD … #define CSR7_UART1_TX_BUFF_ERROR … #define CSR7_UART1_RX_BUFF_ERROR … #define CSR7_UART2_TX_TRESHOLD … #define CSR7_UART2_RX_TRESHOLD … #define CSR7_UART2_IDLE_TRESHOLD … #define CSR7_UART2_TX_BUFF_ERROR … #define CSR7_UART2_RX_BUFF_ERROR … #define CSR7_TIMER_CSR3_EXPIRE … /* * CSR8: Interrupt mask register. * Write 1 to mask interrupt. * TBCN_EXPIRE: Beacon timer expired interrupt. * TWAKE_EXPIRE: Wakeup timer expired interrupt. * TATIMW_EXPIRE: Timer of atim window expired interrupt. * TXDONE_TXRING: Tx ring transmit done interrupt. * TXDONE_ATIMRING: Atim ring transmit done interrupt. * TXDONE_PRIORING: Priority ring transmit done interrupt. * RXDONE: Receive done interrupt. * DECRYPTION_DONE: Decryption done interrupt. * ENCRYPTION_DONE: Encryption done interrupt. * UART1_TX_TRESHOLD: UART1 TX reaches threshold. * UART1_RX_TRESHOLD: UART1 RX reaches threshold. * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold. * UART1_TX_BUFF_ERROR: UART1 TX buffer error. * UART1_RX_BUFF_ERROR: UART1 RX buffer error. * UART2_TX_TRESHOLD: UART2 TX reaches threshold. * UART2_RX_TRESHOLD: UART2 RX reaches threshold. * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold. * UART2_TX_BUFF_ERROR: UART2 TX buffer error. * UART2_RX_BUFF_ERROR: UART2 RX buffer error. * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period). */ #define CSR8 … #define CSR8_TBCN_EXPIRE … #define CSR8_TWAKE_EXPIRE … #define CSR8_TATIMW_EXPIRE … #define CSR8_TXDONE_TXRING … #define CSR8_TXDONE_ATIMRING … #define CSR8_TXDONE_PRIORING … #define CSR8_RXDONE … #define CSR8_DECRYPTION_DONE … #define CSR8_ENCRYPTION_DONE … #define CSR8_UART1_TX_TRESHOLD … #define CSR8_UART1_RX_TRESHOLD … #define CSR8_UART1_IDLE_TRESHOLD … #define CSR8_UART1_TX_BUFF_ERROR … #define CSR8_UART1_RX_BUFF_ERROR … #define CSR8_UART2_TX_TRESHOLD … #define CSR8_UART2_RX_TRESHOLD … #define CSR8_UART2_IDLE_TRESHOLD … #define CSR8_UART2_TX_BUFF_ERROR … #define CSR8_UART2_RX_BUFF_ERROR … #define CSR8_TIMER_CSR3_EXPIRE … /* * CSR9: Maximum frame length register. * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12. */ #define CSR9 … #define CSR9_MAX_FRAME_UNIT … /* * SECCSR0: WEP control register. * KICK_DECRYPT: Kick decryption engine, self-clear. * ONE_SHOT: 0: ring mode, 1: One shot only mode. * DESC_ADDRESS: Descriptor physical address of frame. */ #define SECCSR0 … #define SECCSR0_KICK_DECRYPT … #define SECCSR0_ONE_SHOT … #define SECCSR0_DESC_ADDRESS … /* * CSR11: Back-off control register. * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1). * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1). * SLOT_TIME: Slot time, default is 20us for 802.11b * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD. * LONG_RETRY: Long retry count. * SHORT_RETRY: Short retry count. */ #define CSR11 … #define CSR11_CWMIN … #define CSR11_CWMAX … #define CSR11_SLOT_TIME … #define CSR11_CW_SELECT … #define CSR11_LONG_RETRY … #define CSR11_SHORT_RETRY … /* * CSR12: Synchronization configuration register 0. * All units in 1/16 TU. * BEACON_INTERVAL: Beacon interval, default is 100 TU. * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU. */ #define CSR12 … #define CSR12_BEACON_INTERVAL … #define CSR12_CFP_MAX_DURATION … /* * CSR13: Synchronization configuration register 1. * All units in 1/16 TU. * ATIMW_DURATION: Atim window duration. * CFP_PERIOD: Cfp period, default is 0 TU. */ #define CSR13 … #define CSR13_ATIMW_DURATION … #define CSR13_CFP_PERIOD … /* * CSR14: Synchronization control register. * TSF_COUNT: Enable tsf auto counting. * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. * TBCN: Enable tbcn with reload value. * TCFP: Enable tcfp & cfp / cp switching. * TATIMW: Enable tatimw & atim window switching. * BEACON_GEN: Enable beacon generator. * CFP_COUNT_PRELOAD: Cfp count preload value. * TBCM_PRELOAD: Tbcn preload value in units of 64us. */ #define CSR14 … #define CSR14_TSF_COUNT … #define CSR14_TSF_SYNC … #define CSR14_TBCN … #define CSR14_TCFP … #define CSR14_TATIMW … #define CSR14_BEACON_GEN … #define CSR14_CFP_COUNT_PRELOAD … #define CSR14_TBCM_PRELOAD … /* * CSR15: Synchronization status register. * CFP: ASIC is in contention-free period. * ATIMW: ASIC is in ATIM window. * BEACON_SENT: Beacon is send. */ #define CSR15 … #define CSR15_CFP … #define CSR15_ATIMW … #define CSR15_BEACON_SENT … /* * CSR16: TSF timer register 0. */ #define CSR16 … #define CSR16_LOW_TSFTIMER … /* * CSR17: TSF timer register 1. */ #define CSR17 … #define CSR17_HIGH_TSFTIMER … /* * CSR18: IFS timer register 0. * SIFS: Sifs, default is 10 us. * PIFS: Pifs, default is 30 us. */ #define CSR18 … #define CSR18_SIFS … #define CSR18_PIFS … /* * CSR19: IFS timer register 1. * DIFS: Difs, default is 50 us. * EIFS: Eifs, default is 364 us. */ #define CSR19 … #define CSR19_DIFS … #define CSR19_EIFS … /* * CSR20: Wakeup timer register. * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU. * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup. * AUTOWAKE: Enable auto wakeup / sleep mechanism. */ #define CSR20 … #define CSR20_DELAY_AFTER_TBCN … #define CSR20_TBCN_BEFORE_WAKEUP … #define CSR20_AUTOWAKE … /* * CSR21: EEPROM control register. * RELOAD: Write 1 to reload eeprom content. * TYPE_93C46: 1: 93c46, 0:93c66. */ #define CSR21 … #define CSR21_RELOAD … #define CSR21_EEPROM_DATA_CLOCK … #define CSR21_EEPROM_CHIP_SELECT … #define CSR21_EEPROM_DATA_IN … #define CSR21_EEPROM_DATA_OUT … #define CSR21_TYPE_93C46 … /* * CSR22: CFP control register. * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU. * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain. */ #define CSR22 … #define CSR22_CFP_DURATION_REMAIN … #define CSR22_RELOAD_CFP_DURATION … /* * Transmit related CSRs. * Some values are set in TU, whereas 1 TU == 1024 us. */ /* * TXCSR0: TX Control Register. * KICK_TX: Kick tx ring. * KICK_ATIM: Kick atim ring. * KICK_PRIO: Kick priority ring. * ABORT: Abort all transmit related ring operation. */ #define TXCSR0 … #define TXCSR0_KICK_TX … #define TXCSR0_KICK_ATIM … #define TXCSR0_KICK_PRIO … #define TXCSR0_ABORT … /* * TXCSR1: TX Configuration Register. * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps. * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps. * TSF_OFFSET: Insert tsf offset. * AUTORESPONDER: Enable auto responder which include ack & cts. */ #define TXCSR1 … #define TXCSR1_ACK_TIMEOUT … #define TXCSR1_ACK_CONSUME_TIME … #define TXCSR1_TSF_OFFSET … #define TXCSR1_AUTORESPONDER … /* * TXCSR2: Tx descriptor configuration register. * TXD_SIZE: Tx descriptor size, default is 48. * NUM_TXD: Number of tx entries in ring. * NUM_ATIM: Number of atim entries in ring. * NUM_PRIO: Number of priority entries in ring. */ #define TXCSR2 … #define TXCSR2_TXD_SIZE … #define TXCSR2_NUM_TXD … #define TXCSR2_NUM_ATIM … #define TXCSR2_NUM_PRIO … /* * TXCSR3: TX Ring Base address register. */ #define TXCSR3 … #define TXCSR3_TX_RING_REGISTER … /* * TXCSR4: TX Atim Ring Base address register. */ #define TXCSR4 … #define TXCSR4_ATIM_RING_REGISTER … /* * TXCSR5: TX Prio Ring Base address register. */ #define TXCSR5 … #define TXCSR5_PRIO_RING_REGISTER … /* * TXCSR6: Beacon Base address register. */ #define TXCSR6 … #define TXCSR6_BEACON_RING_REGISTER … /* * TXCSR7: Auto responder control register. * AR_POWERMANAGEMENT: Auto responder power management bit. */ #define TXCSR7 … #define TXCSR7_AR_POWERMANAGEMENT … /* * TXCSR8: CCK Tx BBP register. */ #define TXCSR8 … #define TXCSR8_BBP_ID0 … #define TXCSR8_BBP_ID0_VALID … #define TXCSR8_BBP_ID1 … #define TXCSR8_BBP_ID1_VALID … #define TXCSR8_BBP_ID2 … #define TXCSR8_BBP_ID2_VALID … #define TXCSR8_BBP_ID3 … #define TXCSR8_BBP_ID3_VALID … /* * TXCSR9: OFDM TX BBP registers * OFDM_SIGNAL: BBP rate field address for OFDM. * OFDM_SERVICE: BBP service field address for OFDM. * OFDM_LENGTH_LOW: BBP length low byte address for OFDM. * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM. */ #define TXCSR9 … #define TXCSR9_OFDM_RATE … #define TXCSR9_OFDM_SERVICE … #define TXCSR9_OFDM_LENGTH_LOW … #define TXCSR9_OFDM_LENGTH_HIGH … /* * Receive related CSRs. * Some values are set in TU, whereas 1 TU == 1024 us. */ /* * RXCSR0: RX Control Register. * DISABLE_RX: Disable rx engine. * DROP_CRC: Drop crc error. * DROP_PHYSICAL: Drop physical error. * DROP_CONTROL: Drop control frame. * DROP_NOT_TO_ME: Drop not to me unicast frame. * DROP_TODS: Drop frame tods bit is true. * DROP_VERSION_ERROR: Drop version error frame. * PASS_CRC: Pass all packets with crc attached. * PASS_CRC: Pass all packets with crc attached. * PASS_PLCP: Pass all packets with 4 bytes PLCP attached. * DROP_MCAST: Drop multicast frames. * DROP_BCAST: Drop broadcast frames. * ENABLE_QOS: Accept QOS data frame and parse QOS field. */ #define RXCSR0 … #define RXCSR0_DISABLE_RX … #define RXCSR0_DROP_CRC … #define RXCSR0_DROP_PHYSICAL … #define RXCSR0_DROP_CONTROL … #define RXCSR0_DROP_NOT_TO_ME … #define RXCSR0_DROP_TODS … #define RXCSR0_DROP_VERSION_ERROR … #define RXCSR0_PASS_CRC … #define RXCSR0_PASS_PLCP … #define RXCSR0_DROP_MCAST … #define RXCSR0_DROP_BCAST … #define RXCSR0_ENABLE_QOS … /* * RXCSR1: RX descriptor configuration register. * RXD_SIZE: Rx descriptor size, default is 32b. * NUM_RXD: Number of rx entries in ring. */ #define RXCSR1 … #define RXCSR1_RXD_SIZE … #define RXCSR1_NUM_RXD … /* * RXCSR2: RX Ring base address register. */ #define RXCSR2 … #define RXCSR2_RX_RING_REGISTER … /* * RXCSR3: BBP ID register for Rx operation. * BBP_ID#: BBP register # id. * BBP_ID#_VALID: BBP register # id is valid or not. */ #define RXCSR3 … #define RXCSR3_BBP_ID0 … #define RXCSR3_BBP_ID0_VALID … #define RXCSR3_BBP_ID1 … #define RXCSR3_BBP_ID1_VALID … #define RXCSR3_BBP_ID2 … #define RXCSR3_BBP_ID2_VALID … #define RXCSR3_BBP_ID3 … #define RXCSR3_BBP_ID3_VALID … /* * ARCSR1: Auto Responder PLCP config register 1. * AR_BBP_DATA#: Auto responder BBP register # data. * AR_BBP_ID#: Auto responder BBP register # Id. */ #define ARCSR1 … #define ARCSR1_AR_BBP_DATA2 … #define ARCSR1_AR_BBP_ID2 … #define ARCSR1_AR_BBP_DATA3 … #define ARCSR1_AR_BBP_ID3 … /* * Miscellaneous Registers. * Some values are set in TU, whereas 1 TU == 1024 us. */ /* * PCICSR: PCI control register. * BIG_ENDIAN: 1: big endian, 0: little endian. * RX_TRESHOLD: Rx threshold in dw to start pci access * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw. * TX_TRESHOLD: Tx threshold in dw to start pci access * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward. * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw. * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational. * READ_MULTIPLE: Enable memory read multiple. * WRITE_INVALID: Enable memory write & invalid. */ #define PCICSR … #define PCICSR_BIG_ENDIAN … #define PCICSR_RX_TRESHOLD … #define PCICSR_TX_TRESHOLD … #define PCICSR_BURST_LENTH … #define PCICSR_ENABLE_CLK … #define PCICSR_READ_MULTIPLE … #define PCICSR_WRITE_INVALID … /* * CNT0: FCS error count. * FCS_ERROR: FCS error count, cleared when read. */ #define CNT0 … #define CNT0_FCS_ERROR … /* * Statistic Register. * CNT1: PLCP error count. * CNT2: Long error count. */ #define TIMECSR2 … #define CNT1 … #define CNT2 … #define TIMECSR3 … /* * CNT3: CCA false alarm count. */ #define CNT3 … #define CNT3_FALSE_CCA … /* * Statistic Register. * CNT4: Rx FIFO overflow count. * CNT5: Tx FIFO underrun count. */ #define CNT4 … #define CNT5 … /* * Baseband Control Register. */ /* * PWRCSR0: Power mode configuration register. */ #define PWRCSR0 … /* * Power state transition time registers. */ #define PSCSR0 … #define PSCSR1 … #define PSCSR2 … #define PSCSR3 … /* * PWRCSR1: Manual power control / status register. * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake. * SET_STATE: Set state. Write 1 to trigger, self cleared. * BBP_DESIRE_STATE: BBP desired state. * RF_DESIRE_STATE: RF desired state. * BBP_CURR_STATE: BBP current state. * RF_CURR_STATE: RF current state. * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared. */ #define PWRCSR1 … #define PWRCSR1_SET_STATE … #define PWRCSR1_BBP_DESIRE_STATE … #define PWRCSR1_RF_DESIRE_STATE … #define PWRCSR1_BBP_CURR_STATE … #define PWRCSR1_RF_CURR_STATE … #define PWRCSR1_PUT_TO_SLEEP … /* * TIMECSR: Timer control register. * US_COUNT: 1 us timer count in units of clock cycles. * US_64_COUNT: 64 us timer count in units of 1 us timer. * BEACON_EXPECT: Beacon expect window. */ #define TIMECSR … #define TIMECSR_US_COUNT … #define TIMECSR_US_64_COUNT … #define TIMECSR_BEACON_EXPECT … /* * MACCSR0: MAC configuration register 0. */ #define MACCSR0 … /* * MACCSR1: MAC configuration register 1. * KICK_RX: Kick one-shot rx in one-shot rx mode. * ONESHOT_RXMODE: Enable one-shot rx mode for debugging. * BBPRX_RESET_MODE: Ralink bbp rx reset mode. * AUTO_TXBBP: Auto tx logic access bbp control register. * AUTO_RXBBP: Auto rx logic access bbp control register. * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd. * INTERSIL_IF: Intersil if calibration pin. */ #define MACCSR1 … #define MACCSR1_KICK_RX … #define MACCSR1_ONESHOT_RXMODE … #define MACCSR1_BBPRX_RESET_MODE … #define MACCSR1_AUTO_TXBBP … #define MACCSR1_AUTO_RXBBP … #define MACCSR1_LOOPBACK … #define MACCSR1_INTERSIL_IF … /* * RALINKCSR: Ralink Rx auto-reset BBCR. * AR_BBP_DATA#: Auto reset BBP register # data. * AR_BBP_ID#: Auto reset BBP register # id. */ #define RALINKCSR … #define RALINKCSR_AR_BBP_DATA0 … #define RALINKCSR_AR_BBP_ID0 … #define RALINKCSR_AR_BBP_VALID0 … #define RALINKCSR_AR_BBP_DATA1 … #define RALINKCSR_AR_BBP_ID1 … #define RALINKCSR_AR_BBP_VALID1 … /* * BCNCSR: Beacon interval control register. * CHANGE: Write one to change beacon interval. * DELTATIME: The delta time value. * NUM_BEACON: Number of beacon according to mode. * MODE: Please refer to asic specs. * PLUS: Plus or minus delta time value. */ #define BCNCSR … #define BCNCSR_CHANGE … #define BCNCSR_DELTATIME … #define BCNCSR_NUM_BEACON … #define BCNCSR_MODE … #define BCNCSR_PLUS … /* * BBP / RF / IF Control Register. */ /* * BBPCSR: BBP serial control register. * VALUE: Register value to program into BBP. * REGNUM: Selected BBP register. * BUSY: 1: asic is busy execute BBP programming. * WRITE_CONTROL: 1: write BBP, 0: read BBP. */ #define BBPCSR … #define BBPCSR_VALUE … #define BBPCSR_REGNUM … #define BBPCSR_BUSY … #define BBPCSR_WRITE_CONTROL … /* * RFCSR: RF serial control register. * VALUE: Register value + id to program into rf/if. * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22). * IF_SELECT: Chip to program: 0: rf, 1: if. * PLL_LD: Rf pll_ld status. * BUSY: 1: asic is busy execute rf programming. */ #define RFCSR … #define RFCSR_VALUE … #define RFCSR_NUMBER_OF_BITS … #define RFCSR_IF_SELECT … #define RFCSR_PLL_LD … #define RFCSR_BUSY … /* * LEDCSR: LED control register. * ON_PERIOD: On period, default 70ms. * OFF_PERIOD: Off period, default 30ms. * LINK: 0: linkoff, 1: linkup. * ACTIVITY: 0: idle, 1: active. * LINK_POLARITY: 0: active low, 1: active high. * ACTIVITY_POLARITY: 0: active low, 1: active high. * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF. */ #define LEDCSR … #define LEDCSR_ON_PERIOD … #define LEDCSR_OFF_PERIOD … #define LEDCSR_LINK … #define LEDCSR_ACTIVITY … #define LEDCSR_LINK_POLARITY … #define LEDCSR_ACTIVITY_POLARITY … #define LEDCSR_LED_DEFAULT … /* * SECCSR3: AES control register. */ #define SECCSR3 … /* * ASIC pointer information. * RXPTR: Current RX ring address. * TXPTR: Current Tx ring address. * PRIPTR: Current Priority ring address. * ATIMPTR: Current ATIM ring address. */ #define RXPTR … #define TXPTR … #define PRIPTR … #define ATIMPTR … /* * TXACKCSR0: TX ACK timeout. */ #define TXACKCSR0 … /* * ACK timeout count registers. * ACKCNT0: TX ACK timeout count. * ACKCNT1: RX ACK timeout count. */ #define ACKCNT0 … #define ACKCNT1 … /* * GPIO and others. */ /* * GPIOCSR: GPIO control register. * GPIOCSR_VALx: GPIO value * GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input */ #define GPIOCSR … #define GPIOCSR_VAL0 … #define GPIOCSR_VAL1 … #define GPIOCSR_VAL2 … #define GPIOCSR_VAL3 … #define GPIOCSR_VAL4 … #define GPIOCSR_VAL5 … #define GPIOCSR_VAL6 … #define GPIOCSR_VAL7 … #define GPIOCSR_DIR0 … #define GPIOCSR_DIR1 … #define GPIOCSR_DIR2 … #define GPIOCSR_DIR3 … #define GPIOCSR_DIR4 … #define GPIOCSR_DIR5 … #define GPIOCSR_DIR6 … #define GPIOCSR_DIR7 … /* * FIFO pointer registers. * FIFOCSR0: TX FIFO pointer. * FIFOCSR1: RX FIFO pointer. */ #define FIFOCSR0 … #define FIFOCSR1 … /* * BCNCSR1: Tx BEACON offset time control register. * PRELOAD: Beacon timer offset in units of usec. * BEACON_CWMIN: 2^CwMin. */ #define BCNCSR1 … #define BCNCSR1_PRELOAD … #define BCNCSR1_BEACON_CWMIN … /* * MACCSR2: TX_PE to RX_PE turn-around time control register * DELAY: RX_PE low width, in units of pci clock cycle. */ #define MACCSR2 … #define MACCSR2_DELAY … /* * TESTCSR: TEST mode selection register. */ #define TESTCSR … /* * ARCSR2: 1 Mbps ACK/CTS PLCP. */ #define ARCSR2 … #define ARCSR2_SIGNAL … #define ARCSR2_SERVICE … #define ARCSR2_LENGTH … /* * ARCSR3: 2 Mbps ACK/CTS PLCP. */ #define ARCSR3 … #define ARCSR3_SIGNAL … #define ARCSR3_SERVICE … #define ARCSR3_LENGTH … /* * ARCSR4: 5.5 Mbps ACK/CTS PLCP. */ #define ARCSR4 … #define ARCSR4_SIGNAL … #define ARCSR4_SERVICE … #define ARCSR4_LENGTH … /* * ARCSR5: 11 Mbps ACK/CTS PLCP. */ #define ARCSR5 … #define ARCSR5_SIGNAL … #define ARCSR5_SERVICE … #define ARCSR5_LENGTH … /* * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps. */ #define ARTCSR0 … #define ARTCSR0_ACK_CTS_11MBS … #define ARTCSR0_ACK_CTS_5_5MBS … #define ARTCSR0_ACK_CTS_2MBS … #define ARTCSR0_ACK_CTS_1MBS … /* * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. */ #define ARTCSR1 … #define ARTCSR1_ACK_CTS_6MBS … #define ARTCSR1_ACK_CTS_9MBS … #define ARTCSR1_ACK_CTS_12MBS … #define ARTCSR1_ACK_CTS_18MBS … /* * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. */ #define ARTCSR2 … #define ARTCSR2_ACK_CTS_24MBS … #define ARTCSR2_ACK_CTS_36MBS … #define ARTCSR2_ACK_CTS_48MBS … #define ARTCSR2_ACK_CTS_54MBS … /* * SECCSR1: WEP control register. * KICK_ENCRYPT: Kick encryption engine, self-clear. * ONE_SHOT: 0: ring mode, 1: One shot only mode. * DESC_ADDRESS: Descriptor physical address of frame. */ #define SECCSR1 … #define SECCSR1_KICK_ENCRYPT … #define SECCSR1_ONE_SHOT … #define SECCSR1_DESC_ADDRESS … /* * BBPCSR1: BBP TX configuration. */ #define BBPCSR1 … #define BBPCSR1_CCK … #define BBPCSR1_CCK_FLIP … #define BBPCSR1_OFDM … #define BBPCSR1_OFDM_FLIP … /* * Dual band configuration registers. * DBANDCSR0: Dual band configuration register 0. * DBANDCSR1: Dual band configuration register 1. */ #define DBANDCSR0 … #define DBANDCSR1 … /* * BBPPCSR: BBP Pin control register. */ #define BBPPCSR … /* * MAC special debug mode selection registers. * DBGSEL0: MAC special debug mode selection register 0. * DBGSEL1: MAC special debug mode selection register 1. */ #define DBGSEL0 … #define DBGSEL1 … /* * BISTCSR: BBP BIST register. */ #define BISTCSR … /* * Multicast filter registers. * MCAST0: Multicast filter register 0. * MCAST1: Multicast filter register 1. */ #define MCAST0 … #define MCAST1 … /* * UART registers. * UARTCSR0: UART1 TX register. * UARTCSR1: UART1 RX register. * UARTCSR3: UART1 frame control register. * UARTCSR4: UART1 buffer control register. * UART2CSR0: UART2 TX register. * UART2CSR1: UART2 RX register. * UART2CSR3: UART2 frame control register. * UART2CSR4: UART2 buffer control register. */ #define UARTCSR0 … #define UARTCSR1 … #define UARTCSR3 … #define UARTCSR4 … #define UART2CSR0 … #define UART2CSR1 … #define UART2CSR3 … #define UART2CSR4 … /* * BBP registers. * The wordsize of the BBP is 8 bits. */ /* * R2: TX antenna control */ #define BBP_R2_TX_ANTENNA … #define BBP_R2_TX_IQ_FLIP … /* * R14: RX antenna control */ #define BBP_R14_RX_ANTENNA … #define BBP_R14_RX_IQ_FLIP … /* * BBP_R70 */ #define BBP_R70_JAPAN_FILTER … /* * RF registers */ /* * RF 1 */ #define RF1_TUNER … /* * RF 3 */ #define RF3_TUNER … #define RF3_TXPOWER … /* * EEPROM content. * The wordsize of the EEPROM is 16 bits. */ /* * HW MAC address. */ #define EEPROM_MAC_ADDR_0 … #define EEPROM_MAC_ADDR_BYTE0 … #define EEPROM_MAC_ADDR_BYTE1 … #define EEPROM_MAC_ADDR1 … #define EEPROM_MAC_ADDR_BYTE2 … #define EEPROM_MAC_ADDR_BYTE3 … #define EEPROM_MAC_ADDR_2 … #define EEPROM_MAC_ADDR_BYTE4 … #define EEPROM_MAC_ADDR_BYTE5 … /* * EEPROM antenna. * ANTENNA_NUM: Number of antenna's. * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd. * DYN_TXAGC: Dynamic TX AGC control. * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. * RF_TYPE: Rf_type of this adapter. */ #define EEPROM_ANTENNA … #define EEPROM_ANTENNA_NUM … #define EEPROM_ANTENNA_TX_DEFAULT … #define EEPROM_ANTENNA_RX_DEFAULT … #define EEPROM_ANTENNA_LED_MODE … #define EEPROM_ANTENNA_DYN_TXAGC … #define EEPROM_ANTENNA_HARDWARE_RADIO … #define EEPROM_ANTENNA_RF_TYPE … /* * EEPROM NIC config. * CARDBUS_ACCEL: 0: enable, 1: disable. * DYN_BBP_TUNE: 0: enable, 1: disable. * CCK_TX_POWER: CCK TX power compensation. */ #define EEPROM_NIC … #define EEPROM_NIC_CARDBUS_ACCEL … #define EEPROM_NIC_DYN_BBP_TUNE … #define EEPROM_NIC_CCK_TX_POWER … /* * EEPROM geography. * GEO: Default geography setting for device. */ #define EEPROM_GEOGRAPHY … #define EEPROM_GEOGRAPHY_GEO … /* * EEPROM BBP. */ #define EEPROM_BBP_START … #define EEPROM_BBP_SIZE … #define EEPROM_BBP_VALUE … #define EEPROM_BBP_REG_ID … /* * EEPROM TXPOWER */ #define EEPROM_TXPOWER_START … #define EEPROM_TXPOWER_SIZE … #define EEPROM_TXPOWER_1 … #define EEPROM_TXPOWER_2 … /* * RSSI <-> dBm offset calibration */ #define EEPROM_CALIBRATE_OFFSET … #define EEPROM_CALIBRATE_OFFSET_RSSI … /* * DMA descriptor defines. */ #define TXD_DESC_SIZE … #define RXD_DESC_SIZE … /* * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. */ /* * Word0 */ #define TXD_W0_OWNER_NIC … #define TXD_W0_VALID … #define TXD_W0_RESULT … #define TXD_W0_RETRY_COUNT … #define TXD_W0_MORE_FRAG … #define TXD_W0_ACK … #define TXD_W0_TIMESTAMP … #define TXD_W0_OFDM … #define TXD_W0_CIPHER_OWNER … #define TXD_W0_IFS … #define TXD_W0_RETRY_MODE … #define TXD_W0_DATABYTE_COUNT … #define TXD_W0_CIPHER_ALG … /* * Word1 */ #define TXD_W1_BUFFER_ADDRESS … /* * Word2 */ #define TXD_W2_IV_OFFSET … #define TXD_W2_AIFS … #define TXD_W2_CWMIN … #define TXD_W2_CWMAX … /* * Word3: PLCP information */ #define TXD_W3_PLCP_SIGNAL … #define TXD_W3_PLCP_SERVICE … #define TXD_W3_PLCP_LENGTH_LOW … #define TXD_W3_PLCP_LENGTH_HIGH … /* * Word4 */ #define TXD_W4_IV … /* * Word5 */ #define TXD_W5_EIV … /* * Word6-9: Key */ #define TXD_W6_KEY … #define TXD_W7_KEY … #define TXD_W8_KEY … #define TXD_W9_KEY … /* * Word10 */ #define TXD_W10_RTS … #define TXD_W10_TX_RATE … /* * RX descriptor format for RX Ring. */ /* * Word0 */ #define RXD_W0_OWNER_NIC … #define RXD_W0_UNICAST_TO_ME … #define RXD_W0_MULTICAST … #define RXD_W0_BROADCAST … #define RXD_W0_MY_BSS … #define RXD_W0_CRC_ERROR … #define RXD_W0_OFDM … #define RXD_W0_PHYSICAL_ERROR … #define RXD_W0_CIPHER_OWNER … #define RXD_W0_ICV_ERROR … #define RXD_W0_IV_OFFSET … #define RXD_W0_DATABYTE_COUNT … #define RXD_W0_CIPHER_ALG … /* * Word1 */ #define RXD_W1_BUFFER_ADDRESS … /* * Word2 */ #define RXD_W2_SIGNAL … #define RXD_W2_RSSI … #define RXD_W2_TA … /* * Word3 */ #define RXD_W3_TA … /* * Word4 */ #define RXD_W4_IV … /* * Word5 */ #define RXD_W5_EIV … /* * Word6-9: Key */ #define RXD_W6_KEY … #define RXD_W7_KEY … #define RXD_W8_KEY … #define RXD_W9_KEY … /* * Word10 */ #define RXD_W10_DROP … /* * Macros for converting txpower from EEPROM to mac80211 value * and from mac80211 value to register value. */ #define MIN_TXPOWER … #define MAX_TXPOWER … #define DEFAULT_TXPOWER … #define TXPOWER_FROM_DEV(__txpower) … #define TXPOWER_TO_DEV(__txpower) … #endif /* RT2500PCI_H */
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