/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Copyright (C) 2004 - 2009 Ivo van Doorn <[email protected]> <http://rt2x00.serialmonkey.com> */ /* Module: rt61pci Abstract: Data structures and registers for the rt61pci module. Supported chipsets: RT2561, RT2561s, RT2661. */ #ifndef RT61PCI_H #define RT61PCI_H /* * RT chip PCI IDs. */ #define RT2561s_PCI_ID … #define RT2561_PCI_ID … #define RT2661_PCI_ID … /* * RF chip defines. */ #define RF5225 … #define RF5325 … #define RF2527 … #define RF2529 … /* * Signal information. * Default offset is required for RSSI <-> dBm conversion. */ #define DEFAULT_RSSI_OFFSET … /* * Register layout information. */ #define CSR_REG_BASE … #define CSR_REG_SIZE … #define EEPROM_BASE … #define EEPROM_SIZE … #define BBP_BASE … #define BBP_SIZE … #define RF_BASE … #define RF_SIZE … /* * Number of TX queues. */ #define NUM_TX_QUEUES … /* * PCI registers. */ /* * HOST_CMD_CSR: For HOST to interrupt embedded processor */ #define HOST_CMD_CSR … #define HOST_CMD_CSR_HOST_COMMAND … #define HOST_CMD_CSR_INTERRUPT_MCU … /* * MCU_CNTL_CSR * SELECT_BANK: Select 8051 program bank. * RESET: Enable 8051 reset state. * READY: Ready state for 8051. */ #define MCU_CNTL_CSR … #define MCU_CNTL_CSR_SELECT_BANK … #define MCU_CNTL_CSR_RESET … #define MCU_CNTL_CSR_READY … /* * SOFT_RESET_CSR * FORCE_CLOCK_ON: Host force MAC clock ON */ #define SOFT_RESET_CSR … #define SOFT_RESET_CSR_FORCE_CLOCK_ON … /* * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register. */ #define MCU_INT_SOURCE_CSR … #define MCU_INT_SOURCE_CSR_0 … #define MCU_INT_SOURCE_CSR_1 … #define MCU_INT_SOURCE_CSR_2 … #define MCU_INT_SOURCE_CSR_3 … #define MCU_INT_SOURCE_CSR_4 … #define MCU_INT_SOURCE_CSR_5 … #define MCU_INT_SOURCE_CSR_6 … #define MCU_INT_SOURCE_CSR_7 … #define MCU_INT_SOURCE_CSR_TWAKEUP … #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE … /* * MCU_INT_MASK_CSR: MCU interrupt source/mask register. */ #define MCU_INT_MASK_CSR … #define MCU_INT_MASK_CSR_0 … #define MCU_INT_MASK_CSR_1 … #define MCU_INT_MASK_CSR_2 … #define MCU_INT_MASK_CSR_3 … #define MCU_INT_MASK_CSR_4 … #define MCU_INT_MASK_CSR_5 … #define MCU_INT_MASK_CSR_6 … #define MCU_INT_MASK_CSR_7 … #define MCU_INT_MASK_CSR_TWAKEUP … #define MCU_INT_MASK_CSR_TBTT_EXPIRE … /* * PCI_USEC_CSR */ #define PCI_USEC_CSR … /* * Security key table memory. * 16 entries 32-byte for shared key table * 64 entries 32-byte for pairwise key table * 64 entries 8-byte for pairwise ta key table */ #define SHARED_KEY_TABLE_BASE … #define PAIRWISE_KEY_TABLE_BASE … #define PAIRWISE_TA_TABLE_BASE … #define SHARED_KEY_ENTRY(__idx) … #define PAIRWISE_KEY_ENTRY(__idx) … #define PAIRWISE_TA_ENTRY(__idx) … struct hw_key_entry { … } __packed; struct hw_pairwise_ta_entry { … } __packed; /* * Other on-chip shared memory space. */ #define HW_CIS_BASE … #define HW_NULL_BASE … /* * Since NULL frame won't be that long (256 byte), * We steal 16 tail bytes to save debugging settings. */ #define HW_DEBUG_SETTING_BASE … /* * On-chip BEACON frame space. */ #define HW_BEACON_BASE0 … #define HW_BEACON_BASE1 … #define HW_BEACON_BASE2 … #define HW_BEACON_BASE3 … #define HW_BEACON_OFFSET(__index) … /* * HOST-MCU shared memory. */ /* * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. */ #define H2M_MAILBOX_CSR … #define H2M_MAILBOX_CSR_ARG0 … #define H2M_MAILBOX_CSR_ARG1 … #define H2M_MAILBOX_CSR_CMD_TOKEN … #define H2M_MAILBOX_CSR_OWNER … /* * MCU_LEDCS: LED control for MCU Mailbox. */ #define MCU_LEDCS_LED_MODE … #define MCU_LEDCS_RADIO_STATUS … #define MCU_LEDCS_LINK_BG_STATUS … #define MCU_LEDCS_LINK_A_STATUS … #define MCU_LEDCS_POLARITY_GPIO_0 … #define MCU_LEDCS_POLARITY_GPIO_1 … #define MCU_LEDCS_POLARITY_GPIO_2 … #define MCU_LEDCS_POLARITY_GPIO_3 … #define MCU_LEDCS_POLARITY_GPIO_4 … #define MCU_LEDCS_POLARITY_ACT … #define MCU_LEDCS_POLARITY_READY_BG … #define MCU_LEDCS_POLARITY_READY_A … /* * M2H_CMD_DONE_CSR. */ #define M2H_CMD_DONE_CSR … /* * MCU_TXOP_ARRAY_BASE. */ #define MCU_TXOP_ARRAY_BASE … /* * MAC Control/Status Registers(CSR). * Some values are set in TU, whereas 1 TU == 1024 us. */ /* * MAC_CSR0: ASIC revision number. */ #define MAC_CSR0 … #define MAC_CSR0_REVISION … #define MAC_CSR0_CHIPSET … /* * MAC_CSR1: System control register. * SOFT_RESET: Software reset bit, 1: reset, 0: normal. * BBP_RESET: Hardware reset BBP. * HOST_READY: Host is ready after initialization, 1: ready. */ #define MAC_CSR1 … #define MAC_CSR1_SOFT_RESET … #define MAC_CSR1_BBP_RESET … #define MAC_CSR1_HOST_READY … /* * MAC_CSR2: STA MAC register 0. */ #define MAC_CSR2 … #define MAC_CSR2_BYTE0 … #define MAC_CSR2_BYTE1 … #define MAC_CSR2_BYTE2 … #define MAC_CSR2_BYTE3 … /* * MAC_CSR3: STA MAC register 1. * UNICAST_TO_ME_MASK: * Used to mask off bits from byte 5 of the MAC address * to determine the UNICAST_TO_ME bit for RX frames. * The full mask is complemented by BSS_ID_MASK: * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK */ #define MAC_CSR3 … #define MAC_CSR3_BYTE4 … #define MAC_CSR3_BYTE5 … #define MAC_CSR3_UNICAST_TO_ME_MASK … /* * MAC_CSR4: BSSID register 0. */ #define MAC_CSR4 … #define MAC_CSR4_BYTE0 … #define MAC_CSR4_BYTE1 … #define MAC_CSR4_BYTE2 … #define MAC_CSR4_BYTE3 … /* * MAC_CSR5: BSSID register 1. * BSS_ID_MASK: * This mask is used to mask off bits 0 and 1 of byte 5 of the * BSSID. This will make sure that those bits will be ignored * when determining the MY_BSS of RX frames. * 0: 1-BSSID mode (BSS index = 0) * 1: 2-BSSID mode (BSS index: Byte5, bit 0) * 2: 2-BSSID mode (BSS index: byte5, bit 1) * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1) */ #define MAC_CSR5 … #define MAC_CSR5_BYTE4 … #define MAC_CSR5_BYTE5 … #define MAC_CSR5_BSS_ID_MASK … /* * MAC_CSR6: Maximum frame length register. */ #define MAC_CSR6 … #define MAC_CSR6_MAX_FRAME_UNIT … /* * MAC_CSR7: Reserved */ #define MAC_CSR7 … /* * MAC_CSR8: SIFS/EIFS register. * All units are in US. */ #define MAC_CSR8 … #define MAC_CSR8_SIFS … #define MAC_CSR8_SIFS_AFTER_RX_OFDM … #define MAC_CSR8_EIFS … /* * MAC_CSR9: Back-Off control register. * SLOT_TIME: Slot time, default is 20us for 802.11BG. * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1). * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1). * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD. */ #define MAC_CSR9 … #define MAC_CSR9_SLOT_TIME … #define MAC_CSR9_CWMIN … #define MAC_CSR9_CWMAX … #define MAC_CSR9_CW_SELECT … /* * MAC_CSR10: Power state configuration. */ #define MAC_CSR10 … /* * MAC_CSR11: Power saving transition time register. * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU. * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup. * WAKEUP_LATENCY: In unit of TU. */ #define MAC_CSR11 … #define MAC_CSR11_DELAY_AFTER_TBCN … #define MAC_CSR11_TBCN_BEFORE_WAKEUP … #define MAC_CSR11_AUTOWAKE … #define MAC_CSR11_WAKEUP_LATENCY … /* * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1). * CURRENT_STATE: 0:sleep, 1:awake. * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP. * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake. */ #define MAC_CSR12 … #define MAC_CSR12_CURRENT_STATE … #define MAC_CSR12_PUT_TO_SLEEP … #define MAC_CSR12_FORCE_WAKEUP … #define MAC_CSR12_BBP_CURRENT_STATE … /* * MAC_CSR13: GPIO. * MAC_CSR13_VALx: GPIO value * MAC_CSR13_DIRx: GPIO direction: 0 = output; 1 = input */ #define MAC_CSR13 … #define MAC_CSR13_VAL0 … #define MAC_CSR13_VAL1 … #define MAC_CSR13_VAL2 … #define MAC_CSR13_VAL3 … #define MAC_CSR13_VAL4 … #define MAC_CSR13_VAL5 … #define MAC_CSR13_DIR0 … #define MAC_CSR13_DIR1 … #define MAC_CSR13_DIR2 … #define MAC_CSR13_DIR3 … #define MAC_CSR13_DIR4 … #define MAC_CSR13_DIR5 … /* * MAC_CSR14: LED control register. * ON_PERIOD: On period, default 70ms. * OFF_PERIOD: Off period, default 30ms. * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON. * SW_LED: s/w LED, 1: ON, 0: OFF. * HW_LED_POLARITY: 0: active low, 1: active high. */ #define MAC_CSR14 … #define MAC_CSR14_ON_PERIOD … #define MAC_CSR14_OFF_PERIOD … #define MAC_CSR14_HW_LED … #define MAC_CSR14_SW_LED … #define MAC_CSR14_HW_LED_POLARITY … #define MAC_CSR14_SW_LED2 … /* * MAC_CSR15: NAV control. */ #define MAC_CSR15 … /* * TXRX control registers. * Some values are set in TU, whereas 1 TU == 1024 us. */ /* * TXRX_CSR0: TX/RX configuration register. * TSF_OFFSET: Default is 24. * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame. * DISABLE_RX: Disable Rx engine. * DROP_CRC: Drop CRC error. * DROP_PHYSICAL: Drop physical error. * DROP_CONTROL: Drop control frame. * DROP_NOT_TO_ME: Drop not to me unicast frame. * DROP_TO_DS: Drop fram ToDs bit is true. * DROP_VERSION_ERROR: Drop version error frame. * DROP_MULTICAST: Drop multicast frames. * DROP_BORADCAST: Drop broadcast frames. * DROP_ACK_CTS: Drop received ACK and CTS. */ #define TXRX_CSR0 … #define TXRX_CSR0_RX_ACK_TIMEOUT … #define TXRX_CSR0_TSF_OFFSET … #define TXRX_CSR0_AUTO_TX_SEQ … #define TXRX_CSR0_DISABLE_RX … #define TXRX_CSR0_DROP_CRC … #define TXRX_CSR0_DROP_PHYSICAL … #define TXRX_CSR0_DROP_CONTROL … #define TXRX_CSR0_DROP_NOT_TO_ME … #define TXRX_CSR0_DROP_TO_DS … #define TXRX_CSR0_DROP_VERSION_ERROR … #define TXRX_CSR0_DROP_MULTICAST … #define TXRX_CSR0_DROP_BROADCAST … #define TXRX_CSR0_DROP_ACK_CTS … #define TXRX_CSR0_TX_WITHOUT_WAITING … /* * TXRX_CSR1 */ #define TXRX_CSR1 … #define TXRX_CSR1_BBP_ID0 … #define TXRX_CSR1_BBP_ID0_VALID … #define TXRX_CSR1_BBP_ID1 … #define TXRX_CSR1_BBP_ID1_VALID … #define TXRX_CSR1_BBP_ID2 … #define TXRX_CSR1_BBP_ID2_VALID … #define TXRX_CSR1_BBP_ID3 … #define TXRX_CSR1_BBP_ID3_VALID … /* * TXRX_CSR2 */ #define TXRX_CSR2 … #define TXRX_CSR2_BBP_ID0 … #define TXRX_CSR2_BBP_ID0_VALID … #define TXRX_CSR2_BBP_ID1 … #define TXRX_CSR2_BBP_ID1_VALID … #define TXRX_CSR2_BBP_ID2 … #define TXRX_CSR2_BBP_ID2_VALID … #define TXRX_CSR2_BBP_ID3 … #define TXRX_CSR2_BBP_ID3_VALID … /* * TXRX_CSR3 */ #define TXRX_CSR3 … #define TXRX_CSR3_BBP_ID0 … #define TXRX_CSR3_BBP_ID0_VALID … #define TXRX_CSR3_BBP_ID1 … #define TXRX_CSR3_BBP_ID1_VALID … #define TXRX_CSR3_BBP_ID2 … #define TXRX_CSR3_BBP_ID2_VALID … #define TXRX_CSR3_BBP_ID3 … #define TXRX_CSR3_BBP_ID3_VALID … /* * TXRX_CSR4: Auto-Responder/Tx-retry register. * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble. * OFDM_TX_RATE_DOWN: 1:enable. * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step. * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M. */ #define TXRX_CSR4 … #define TXRX_CSR4_TX_ACK_TIMEOUT … #define TXRX_CSR4_CNTL_ACK_POLICY … #define TXRX_CSR4_ACK_CTS_PSM … #define TXRX_CSR4_AUTORESPOND_ENABLE … #define TXRX_CSR4_AUTORESPOND_PREAMBLE … #define TXRX_CSR4_OFDM_TX_RATE_DOWN … #define TXRX_CSR4_OFDM_TX_RATE_STEP … #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK … #define TXRX_CSR4_LONG_RETRY_LIMIT … #define TXRX_CSR4_SHORT_RETRY_LIMIT … /* * TXRX_CSR5 */ #define TXRX_CSR5 … /* * TXRX_CSR6: ACK/CTS payload consumed time */ #define TXRX_CSR6 … /* * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. */ #define TXRX_CSR7 … #define TXRX_CSR7_ACK_CTS_6MBS … #define TXRX_CSR7_ACK_CTS_9MBS … #define TXRX_CSR7_ACK_CTS_12MBS … #define TXRX_CSR7_ACK_CTS_18MBS … /* * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. */ #define TXRX_CSR8 … #define TXRX_CSR8_ACK_CTS_24MBS … #define TXRX_CSR8_ACK_CTS_36MBS … #define TXRX_CSR8_ACK_CTS_48MBS … #define TXRX_CSR8_ACK_CTS_54MBS … /* * TXRX_CSR9: Synchronization control register. * BEACON_INTERVAL: In unit of 1/16 TU. * TSF_TICKING: Enable TSF auto counting. * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. * BEACON_GEN: Enable beacon generator. */ #define TXRX_CSR9 … #define TXRX_CSR9_BEACON_INTERVAL … #define TXRX_CSR9_TSF_TICKING … #define TXRX_CSR9_TSF_SYNC … #define TXRX_CSR9_TBTT_ENABLE … #define TXRX_CSR9_BEACON_GEN … #define TXRX_CSR9_TIMESTAMP_COMPENSATE … /* * TXRX_CSR10: BEACON alignment. */ #define TXRX_CSR10 … /* * TXRX_CSR11: AES mask. */ #define TXRX_CSR11 … /* * TXRX_CSR12: TSF low 32. */ #define TXRX_CSR12 … #define TXRX_CSR12_LOW_TSFTIMER … /* * TXRX_CSR13: TSF high 32. */ #define TXRX_CSR13 … #define TXRX_CSR13_HIGH_TSFTIMER … /* * TXRX_CSR14: TBTT timer. */ #define TXRX_CSR14 … /* * TXRX_CSR15: TKIP MIC priority byte "AND" mask. */ #define TXRX_CSR15 … /* * PHY control registers. * Some values are set in TU, whereas 1 TU == 1024 us. */ /* * PHY_CSR0: RF/PS control. */ #define PHY_CSR0 … #define PHY_CSR0_PA_PE_BG … #define PHY_CSR0_PA_PE_A … /* * PHY_CSR1 */ #define PHY_CSR1 … /* * PHY_CSR2: Pre-TX BBP control. */ #define PHY_CSR2 … /* * PHY_CSR3: BBP serial control register. * VALUE: Register value to program into BBP. * REG_NUM: Selected BBP register. * READ_CONTROL: 0: Write BBP, 1: Read BBP. * BUSY: 1: ASIC is busy execute BBP programming. */ #define PHY_CSR3 … #define PHY_CSR3_VALUE … #define PHY_CSR3_REGNUM … #define PHY_CSR3_READ_CONTROL … #define PHY_CSR3_BUSY … /* * PHY_CSR4: RF serial control register * VALUE: Register value (include register id) serial out to RF/IF chip. * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22). * IF_SELECT: 1: select IF to program, 0: select RF to program. * PLL_LD: RF PLL_LD status. * BUSY: 1: ASIC is busy execute RF programming. */ #define PHY_CSR4 … #define PHY_CSR4_VALUE … #define PHY_CSR4_NUMBER_OF_BITS … #define PHY_CSR4_IF_SELECT … #define PHY_CSR4_PLL_LD … #define PHY_CSR4_BUSY … /* * PHY_CSR5: RX to TX signal switch timing control. */ #define PHY_CSR5 … #define PHY_CSR5_IQ_FLIP … /* * PHY_CSR6: TX to RX signal timing control. */ #define PHY_CSR6 … #define PHY_CSR6_IQ_FLIP … /* * PHY_CSR7: TX DAC switching timing control. */ #define PHY_CSR7 … /* * Security control register. */ /* * SEC_CSR0: Shared key table control. */ #define SEC_CSR0 … #define SEC_CSR0_BSS0_KEY0_VALID … #define SEC_CSR0_BSS0_KEY1_VALID … #define SEC_CSR0_BSS0_KEY2_VALID … #define SEC_CSR0_BSS0_KEY3_VALID … #define SEC_CSR0_BSS1_KEY0_VALID … #define SEC_CSR0_BSS1_KEY1_VALID … #define SEC_CSR0_BSS1_KEY2_VALID … #define SEC_CSR0_BSS1_KEY3_VALID … #define SEC_CSR0_BSS2_KEY0_VALID … #define SEC_CSR0_BSS2_KEY1_VALID … #define SEC_CSR0_BSS2_KEY2_VALID … #define SEC_CSR0_BSS2_KEY3_VALID … #define SEC_CSR0_BSS3_KEY0_VALID … #define SEC_CSR0_BSS3_KEY1_VALID … #define SEC_CSR0_BSS3_KEY2_VALID … #define SEC_CSR0_BSS3_KEY3_VALID … /* * SEC_CSR1: Shared key table security mode register. */ #define SEC_CSR1 … #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG … #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG … #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG … #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG … #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG … #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG … #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG … #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG … /* * Pairwise key table valid bitmap registers. * SEC_CSR2: pairwise key table valid bitmap 0. * SEC_CSR3: pairwise key table valid bitmap 1. */ #define SEC_CSR2 … #define SEC_CSR3 … /* * SEC_CSR4: Pairwise key table lookup control. */ #define SEC_CSR4 … #define SEC_CSR4_ENABLE_BSS0 … #define SEC_CSR4_ENABLE_BSS1 … #define SEC_CSR4_ENABLE_BSS2 … #define SEC_CSR4_ENABLE_BSS3 … /* * SEC_CSR5: shared key table security mode register. */ #define SEC_CSR5 … #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG … #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG … #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG … #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG … #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG … #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG … #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG … #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG … /* * STA control registers. */ /* * STA_CSR0: RX PLCP error count & RX FCS error count. */ #define STA_CSR0 … #define STA_CSR0_FCS_ERROR … #define STA_CSR0_PLCP_ERROR … /* * STA_CSR1: RX False CCA count & RX LONG frame count. */ #define STA_CSR1 … #define STA_CSR1_PHYSICAL_ERROR … #define STA_CSR1_FALSE_CCA_ERROR … /* * STA_CSR2: TX Beacon count and RX FIFO overflow count. */ #define STA_CSR2 … #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT … #define STA_CSR2_RX_OVERFLOW_COUNT … /* * STA_CSR3: TX Beacon count. */ #define STA_CSR3 … #define STA_CSR3_TX_BEACON_COUNT … /* * STA_CSR4: TX Result status register. * VALID: 1:This register contains a valid TX result. */ #define STA_CSR4 … #define STA_CSR4_VALID … #define STA_CSR4_TX_RESULT … #define STA_CSR4_RETRY_COUNT … #define STA_CSR4_PID_SUBTYPE … #define STA_CSR4_PID_TYPE … #define STA_CSR4_TXRATE … /* * QOS control registers. */ /* * QOS_CSR0: TXOP holder MAC address register. */ #define QOS_CSR0 … #define QOS_CSR0_BYTE0 … #define QOS_CSR0_BYTE1 … #define QOS_CSR0_BYTE2 … #define QOS_CSR0_BYTE3 … /* * QOS_CSR1: TXOP holder MAC address register. */ #define QOS_CSR1 … #define QOS_CSR1_BYTE4 … #define QOS_CSR1_BYTE5 … /* * QOS_CSR2: TXOP holder timeout register. */ #define QOS_CSR2 … /* * RX QOS-CFPOLL MAC address register. * QOS_CSR3: RX QOS-CFPOLL MAC address 0. * QOS_CSR4: RX QOS-CFPOLL MAC address 1. */ #define QOS_CSR3 … #define QOS_CSR4 … /* * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL. */ #define QOS_CSR5 … /* * Host DMA registers. */ /* * AC0_BASE_CSR: AC_VO base address. */ #define AC0_BASE_CSR … #define AC0_BASE_CSR_RING_REGISTER … /* * AC1_BASE_CSR: AC_VI base address. */ #define AC1_BASE_CSR … #define AC1_BASE_CSR_RING_REGISTER … /* * AC2_BASE_CSR: AC_BE base address. */ #define AC2_BASE_CSR … #define AC2_BASE_CSR_RING_REGISTER … /* * AC3_BASE_CSR: AC_BK base address. */ #define AC3_BASE_CSR … #define AC3_BASE_CSR_RING_REGISTER … /* * MGMT_BASE_CSR: MGMT ring base address. */ #define MGMT_BASE_CSR … #define MGMT_BASE_CSR_RING_REGISTER … /* * TX_RING_CSR0: TX Ring size for AC_VO, AC_VI, AC_BE, AC_BK. */ #define TX_RING_CSR0 … #define TX_RING_CSR0_AC0_RING_SIZE … #define TX_RING_CSR0_AC1_RING_SIZE … #define TX_RING_CSR0_AC2_RING_SIZE … #define TX_RING_CSR0_AC3_RING_SIZE … /* * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring * TXD_SIZE: In unit of 32-bit. */ #define TX_RING_CSR1 … #define TX_RING_CSR1_MGMT_RING_SIZE … #define TX_RING_CSR1_HCCA_RING_SIZE … #define TX_RING_CSR1_TXD_SIZE … /* * AIFSN_CSR: AIFSN for each EDCA AC. * AIFSN0: For AC_VO. * AIFSN1: For AC_VI. * AIFSN2: For AC_BE. * AIFSN3: For AC_BK. */ #define AIFSN_CSR … #define AIFSN_CSR_AIFSN0 … #define AIFSN_CSR_AIFSN1 … #define AIFSN_CSR_AIFSN2 … #define AIFSN_CSR_AIFSN3 … /* * CWMIN_CSR: CWmin for each EDCA AC. * CWMIN0: For AC_VO. * CWMIN1: For AC_VI. * CWMIN2: For AC_BE. * CWMIN3: For AC_BK. */ #define CWMIN_CSR … #define CWMIN_CSR_CWMIN0 … #define CWMIN_CSR_CWMIN1 … #define CWMIN_CSR_CWMIN2 … #define CWMIN_CSR_CWMIN3 … /* * CWMAX_CSR: CWmax for each EDCA AC. * CWMAX0: For AC_VO. * CWMAX1: For AC_VI. * CWMAX2: For AC_BE. * CWMAX3: For AC_BK. */ #define CWMAX_CSR … #define CWMAX_CSR_CWMAX0 … #define CWMAX_CSR_CWMAX1 … #define CWMAX_CSR_CWMAX2 … #define CWMAX_CSR_CWMAX3 … /* * TX_DMA_DST_CSR: TX DMA destination * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid */ #define TX_DMA_DST_CSR … #define TX_DMA_DST_CSR_DEST_AC0 … #define TX_DMA_DST_CSR_DEST_AC1 … #define TX_DMA_DST_CSR_DEST_AC2 … #define TX_DMA_DST_CSR_DEST_AC3 … #define TX_DMA_DST_CSR_DEST_MGMT … /* * TX_CNTL_CSR: KICK/Abort TX. * KICK_TX_AC0: For AC_VO. * KICK_TX_AC1: For AC_VI. * KICK_TX_AC2: For AC_BE. * KICK_TX_AC3: For AC_BK. * ABORT_TX_AC0: For AC_VO. * ABORT_TX_AC1: For AC_VI. * ABORT_TX_AC2: For AC_BE. * ABORT_TX_AC3: For AC_BK. */ #define TX_CNTL_CSR … #define TX_CNTL_CSR_KICK_TX_AC0 … #define TX_CNTL_CSR_KICK_TX_AC1 … #define TX_CNTL_CSR_KICK_TX_AC2 … #define TX_CNTL_CSR_KICK_TX_AC3 … #define TX_CNTL_CSR_KICK_TX_MGMT … #define TX_CNTL_CSR_ABORT_TX_AC0 … #define TX_CNTL_CSR_ABORT_TX_AC1 … #define TX_CNTL_CSR_ABORT_TX_AC2 … #define TX_CNTL_CSR_ABORT_TX_AC3 … #define TX_CNTL_CSR_ABORT_TX_MGMT … /* * LOAD_TX_RING_CSR: Load RX desriptor */ #define LOAD_TX_RING_CSR … #define LOAD_TX_RING_CSR_LOAD_TXD_AC0 … #define LOAD_TX_RING_CSR_LOAD_TXD_AC1 … #define LOAD_TX_RING_CSR_LOAD_TXD_AC2 … #define LOAD_TX_RING_CSR_LOAD_TXD_AC3 … #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT … /* * Several read-only registers, for debugging. */ #define AC0_TXPTR_CSR … #define AC1_TXPTR_CSR … #define AC2_TXPTR_CSR … #define AC3_TXPTR_CSR … #define MGMT_TXPTR_CSR … /* * RX_BASE_CSR */ #define RX_BASE_CSR … #define RX_BASE_CSR_RING_REGISTER … /* * RX_RING_CSR. * RXD_SIZE: In unit of 32-bit. */ #define RX_RING_CSR … #define RX_RING_CSR_RING_SIZE … #define RX_RING_CSR_RXD_SIZE … #define RX_RING_CSR_RXD_WRITEBACK_SIZE … /* * RX_CNTL_CSR */ #define RX_CNTL_CSR … #define RX_CNTL_CSR_ENABLE_RX_DMA … #define RX_CNTL_CSR_LOAD_RXD … /* * RXPTR_CSR: Read-only, for debugging. */ #define RXPTR_CSR … /* * PCI_CFG_CSR */ #define PCI_CFG_CSR … /* * BUF_FORMAT_CSR */ #define BUF_FORMAT_CSR … /* * INT_SOURCE_CSR: Interrupt source register. * Write one to clear corresponding bit. */ #define INT_SOURCE_CSR … #define INT_SOURCE_CSR_TXDONE … #define INT_SOURCE_CSR_RXDONE … #define INT_SOURCE_CSR_BEACON_DONE … #define INT_SOURCE_CSR_TX_ABORT_DONE … #define INT_SOURCE_CSR_AC0_DMA_DONE … #define INT_SOURCE_CSR_AC1_DMA_DONE … #define INT_SOURCE_CSR_AC2_DMA_DONE … #define INT_SOURCE_CSR_AC3_DMA_DONE … #define INT_SOURCE_CSR_MGMT_DMA_DONE … #define INT_SOURCE_CSR_HCCA_DMA_DONE … /* * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock. */ #define INT_MASK_CSR … #define INT_MASK_CSR_TXDONE … #define INT_MASK_CSR_RXDONE … #define INT_MASK_CSR_BEACON_DONE … #define INT_MASK_CSR_TX_ABORT_DONE … #define INT_MASK_CSR_ENABLE_MITIGATION … #define INT_MASK_CSR_MITIGATION_PERIOD … #define INT_MASK_CSR_AC0_DMA_DONE … #define INT_MASK_CSR_AC1_DMA_DONE … #define INT_MASK_CSR_AC2_DMA_DONE … #define INT_MASK_CSR_AC3_DMA_DONE … #define INT_MASK_CSR_MGMT_DMA_DONE … #define INT_MASK_CSR_HCCA_DMA_DONE … /* * E2PROM_CSR: EEPROM control register. * RELOAD: Write 1 to reload eeprom content. * TYPE_93C46: 1: 93c46, 0:93c66. * LOAD_STATUS: 1:loading, 0:done. */ #define E2PROM_CSR … #define E2PROM_CSR_RELOAD … #define E2PROM_CSR_DATA_CLOCK … #define E2PROM_CSR_CHIP_SELECT … #define E2PROM_CSR_DATA_IN … #define E2PROM_CSR_DATA_OUT … #define E2PROM_CSR_TYPE_93C46 … #define E2PROM_CSR_LOAD_STATUS … /* * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register. * AC0_TX_OP: For AC_VO, in unit of 32us. * AC1_TX_OP: For AC_VI, in unit of 32us. */ #define AC_TXOP_CSR0 … #define AC_TXOP_CSR0_AC0_TX_OP … #define AC_TXOP_CSR0_AC1_TX_OP … /* * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register. * AC2_TX_OP: For AC_BE, in unit of 32us. * AC3_TX_OP: For AC_BK, in unit of 32us. */ #define AC_TXOP_CSR1 … #define AC_TXOP_CSR1_AC2_TX_OP … #define AC_TXOP_CSR1_AC3_TX_OP … /* * DMA_STATUS_CSR */ #define DMA_STATUS_CSR … /* * TEST_MODE_CSR */ #define TEST_MODE_CSR … /* * UART0_TX_CSR */ #define UART0_TX_CSR … /* * UART0_RX_CSR */ #define UART0_RX_CSR … /* * UART0_FRAME_CSR */ #define UART0_FRAME_CSR … /* * UART0_BUFFER_CSR */ #define UART0_BUFFER_CSR … /* * IO_CNTL_CSR * RF_PS: Set RF interface value to power save */ #define IO_CNTL_CSR … #define IO_CNTL_CSR_RF_PS … /* * UART_INT_SOURCE_CSR */ #define UART_INT_SOURCE_CSR … /* * UART_INT_MASK_CSR */ #define UART_INT_MASK_CSR … /* * PBF_QUEUE_CSR */ #define PBF_QUEUE_CSR … /* * Firmware DMA registers. * Firmware DMA registers are dedicated for MCU usage * and should not be touched by host driver. * Therefore we skip the definition of these registers. */ #define FW_TX_BASE_CSR … #define FW_TX_START_CSR … #define FW_TX_LAST_CSR … #define FW_MODE_CNTL_CSR … #define FW_TXPTR_CSR … /* * 8051 firmware image. */ #define FIRMWARE_RT2561 … #define FIRMWARE_RT2561s … #define FIRMWARE_RT2661 … #define FIRMWARE_IMAGE_BASE … /* * BBP registers. * The wordsize of the BBP is 8 bits. */ /* * R2 */ #define BBP_R2_BG_MODE … /* * R3 */ #define BBP_R3_SMART_MODE … /* * R4: RX antenna control * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529) */ /* * ANTENNA_CONTROL semantics (guessed): * 0x1: Software controlled antenna switching (fixed or SW diversity) * 0x2: Hardware diversity. */ #define BBP_R4_RX_ANTENNA_CONTROL … #define BBP_R4_RX_FRAME_END … /* * R77 */ #define BBP_R77_RX_ANTENNA … /* * RF registers */ /* * RF 3 */ #define RF3_TXPOWER … /* * RF 4 */ #define RF4_FREQ_OFFSET … /* * EEPROM content. * The wordsize of the EEPROM is 16 bits. */ /* * HW MAC address. */ #define EEPROM_MAC_ADDR_0 … #define EEPROM_MAC_ADDR_BYTE0 … #define EEPROM_MAC_ADDR_BYTE1 … #define EEPROM_MAC_ADDR1 … #define EEPROM_MAC_ADDR_BYTE2 … #define EEPROM_MAC_ADDR_BYTE3 … #define EEPROM_MAC_ADDR_2 … #define EEPROM_MAC_ADDR_BYTE4 … #define EEPROM_MAC_ADDR_BYTE5 … /* * EEPROM antenna. * ANTENNA_NUM: Number of antenna's. * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only. * DYN_TXAGC: Dynamic TX AGC control. * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. * RF_TYPE: Rf_type of this adapter. */ #define EEPROM_ANTENNA … #define EEPROM_ANTENNA_NUM … #define EEPROM_ANTENNA_TX_DEFAULT … #define EEPROM_ANTENNA_RX_DEFAULT … #define EEPROM_ANTENNA_FRAME_TYPE … #define EEPROM_ANTENNA_DYN_TXAGC … #define EEPROM_ANTENNA_HARDWARE_RADIO … #define EEPROM_ANTENNA_RF_TYPE … /* * EEPROM NIC config. * ENABLE_DIVERSITY: 1:enable, 0:disable. * EXTERNAL_LNA_BG: External LNA enable for 2.4G. * CARDBUS_ACCEL: 0:enable, 1:disable. * EXTERNAL_LNA_A: External LNA enable for 5G. */ #define EEPROM_NIC … #define EEPROM_NIC_ENABLE_DIVERSITY … #define EEPROM_NIC_TX_DIVERSITY … #define EEPROM_NIC_RX_FIXED … #define EEPROM_NIC_TX_FIXED … #define EEPROM_NIC_EXTERNAL_LNA_BG … #define EEPROM_NIC_CARDBUS_ACCEL … #define EEPROM_NIC_EXTERNAL_LNA_A … /* * EEPROM geography. * GEO_A: Default geographical setting for 5GHz band * GEO: Default geographical setting. */ #define EEPROM_GEOGRAPHY … #define EEPROM_GEOGRAPHY_GEO_A … #define EEPROM_GEOGRAPHY_GEO … /* * EEPROM BBP. */ #define EEPROM_BBP_START … #define EEPROM_BBP_SIZE … #define EEPROM_BBP_VALUE … #define EEPROM_BBP_REG_ID … /* * EEPROM TXPOWER 802.11G */ #define EEPROM_TXPOWER_G_START … #define EEPROM_TXPOWER_G_SIZE … #define EEPROM_TXPOWER_G_1 … #define EEPROM_TXPOWER_G_2 … /* * EEPROM Frequency */ #define EEPROM_FREQ … #define EEPROM_FREQ_OFFSET … #define EEPROM_FREQ_SEQ_MASK … #define EEPROM_FREQ_SEQ … /* * EEPROM LED. * POLARITY_RDY_G: Polarity RDY_G setting. * POLARITY_RDY_A: Polarity RDY_A setting. * POLARITY_ACT: Polarity ACT setting. * POLARITY_GPIO_0: Polarity GPIO0 setting. * POLARITY_GPIO_1: Polarity GPIO1 setting. * POLARITY_GPIO_2: Polarity GPIO2 setting. * POLARITY_GPIO_3: Polarity GPIO3 setting. * POLARITY_GPIO_4: Polarity GPIO4 setting. * LED_MODE: Led mode. */ #define EEPROM_LED … #define EEPROM_LED_POLARITY_RDY_G … #define EEPROM_LED_POLARITY_RDY_A … #define EEPROM_LED_POLARITY_ACT … #define EEPROM_LED_POLARITY_GPIO_0 … #define EEPROM_LED_POLARITY_GPIO_1 … #define EEPROM_LED_POLARITY_GPIO_2 … #define EEPROM_LED_POLARITY_GPIO_3 … #define EEPROM_LED_POLARITY_GPIO_4 … #define EEPROM_LED_LED_MODE … /* * EEPROM TXPOWER 802.11A */ #define EEPROM_TXPOWER_A_START … #define EEPROM_TXPOWER_A_SIZE … #define EEPROM_TXPOWER_A_1 … #define EEPROM_TXPOWER_A_2 … /* * EEPROM RSSI offset 802.11BG */ #define EEPROM_RSSI_OFFSET_BG … #define EEPROM_RSSI_OFFSET_BG_1 … #define EEPROM_RSSI_OFFSET_BG_2 … /* * EEPROM RSSI offset 802.11A */ #define EEPROM_RSSI_OFFSET_A … #define EEPROM_RSSI_OFFSET_A_1 … #define EEPROM_RSSI_OFFSET_A_2 … /* * MCU mailbox commands. */ #define MCU_SLEEP … #define MCU_WAKEUP … #define MCU_LED … #define MCU_LED_STRENGTH … /* * DMA descriptor defines. */ #define TXD_DESC_SIZE … #define TXINFO_SIZE … #define RXD_DESC_SIZE … /* * TX descriptor format for TX, PRIO and Beacon Ring. */ /* * Word0 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used. * KEY_TABLE: Use per-client pairwise KEY table. * KEY_INDEX: * Key index (0~31) to the pairwise KEY table. * 0~3 to shared KEY table 0 (BSS0). * 4~7 to shared KEY table 1 (BSS1). * 8~11 to shared KEY table 2 (BSS2). * 12~15 to shared KEY table 3 (BSS3). * BURST: Next frame belongs to same "burst" event. */ #define TXD_W0_OWNER_NIC … #define TXD_W0_VALID … #define TXD_W0_MORE_FRAG … #define TXD_W0_ACK … #define TXD_W0_TIMESTAMP … #define TXD_W0_OFDM … #define TXD_W0_IFS … #define TXD_W0_RETRY_MODE … #define TXD_W0_TKIP_MIC … #define TXD_W0_KEY_TABLE … #define TXD_W0_KEY_INDEX … #define TXD_W0_DATABYTE_COUNT … #define TXD_W0_BURST … #define TXD_W0_CIPHER_ALG … /* * Word1 * HOST_Q_ID: EDCA/HCCA queue ID. * HW_SEQUENCE: MAC overwrites the frame sequence number. * BUFFER_COUNT: Number of buffers in this TXD. */ #define TXD_W1_HOST_Q_ID … #define TXD_W1_AIFSN … #define TXD_W1_CWMIN … #define TXD_W1_CWMAX … #define TXD_W1_IV_OFFSET … #define TXD_W1_PIGGY_BACK … #define TXD_W1_HW_SEQUENCE … #define TXD_W1_BUFFER_COUNT … /* * Word2: PLCP information */ #define TXD_W2_PLCP_SIGNAL … #define TXD_W2_PLCP_SERVICE … #define TXD_W2_PLCP_LENGTH_LOW … #define TXD_W2_PLCP_LENGTH_HIGH … /* * Word3 */ #define TXD_W3_IV … /* * Word4 */ #define TXD_W4_EIV … /* * Word5 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field). * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler. * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler. * WAITING_DMA_DONE_INT: TXD been filled with data * and waiting for TxDoneISR housekeeping. */ #define TXD_W5_FRAME_OFFSET … #define TXD_W5_PID_SUBTYPE … #define TXD_W5_PID_TYPE … #define TXD_W5_TX_POWER … #define TXD_W5_WAITING_DMA_DONE_INT … /* * the above 24-byte is called TXINFO and will be DMAed to MAC block * through TXFIFO. MAC block use this TXINFO to control the transmission * behavior of this frame. * The following fields are not used by MAC block. * They are used by DMA block and HOST driver only. * Once a frame has been DMA to ASIC, all the following fields are useless * to ASIC. */ /* * Word6-10: Buffer physical address */ #define TXD_W6_BUFFER_PHYSICAL_ADDRESS … #define TXD_W7_BUFFER_PHYSICAL_ADDRESS … #define TXD_W8_BUFFER_PHYSICAL_ADDRESS … #define TXD_W9_BUFFER_PHYSICAL_ADDRESS … #define TXD_W10_BUFFER_PHYSICAL_ADDRESS … /* * Word11-13: Buffer length */ #define TXD_W11_BUFFER_LENGTH0 … #define TXD_W11_BUFFER_LENGTH1 … #define TXD_W12_BUFFER_LENGTH2 … #define TXD_W12_BUFFER_LENGTH3 … #define TXD_W13_BUFFER_LENGTH4 … /* * Word14 */ #define TXD_W14_SK_BUFFER … /* * Word15 */ #define TXD_W15_NEXT_SK_BUFFER … /* * RX descriptor format for RX Ring. */ /* * Word0 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key. * KEY_INDEX: Decryption key actually used. */ #define RXD_W0_OWNER_NIC … #define RXD_W0_DROP … #define RXD_W0_UNICAST_TO_ME … #define RXD_W0_MULTICAST … #define RXD_W0_BROADCAST … #define RXD_W0_MY_BSS … #define RXD_W0_CRC_ERROR … #define RXD_W0_OFDM … #define RXD_W0_CIPHER_ERROR … #define RXD_W0_KEY_INDEX … #define RXD_W0_DATABYTE_COUNT … #define RXD_W0_CIPHER_ALG … /* * Word1 * SIGNAL: RX raw data rate reported by BBP. */ #define RXD_W1_SIGNAL … #define RXD_W1_RSSI_AGC … #define RXD_W1_RSSI_LNA … #define RXD_W1_FRAME_OFFSET … /* * Word2 * IV: Received IV of originally encrypted. */ #define RXD_W2_IV … /* * Word3 * EIV: Received EIV of originally encrypted. */ #define RXD_W3_EIV … /* * Word4 * ICV: Received ICV of originally encrypted. * NOTE: This is a guess, the official definition is "reserved" */ #define RXD_W4_ICV … /* * the above 20-byte is called RXINFO and will be DMAed to MAC RX block * and passed to the HOST driver. * The following fields are for DMA block and HOST usage only. * Can't be touched by ASIC MAC block. */ /* * Word5 */ #define RXD_W5_BUFFER_PHYSICAL_ADDRESS … /* * Word6-15: Reserved */ #define RXD_W6_RESERVED … #define RXD_W7_RESERVED … #define RXD_W8_RESERVED … #define RXD_W9_RESERVED … #define RXD_W10_RESERVED … #define RXD_W11_RESERVED … #define RXD_W12_RESERVED … #define RXD_W13_RESERVED … #define RXD_W14_RESERVED … #define RXD_W15_RESERVED … /* * Macros for converting txpower from EEPROM to mac80211 value * and from mac80211 value to register value. */ #define MIN_TXPOWER … #define MAX_TXPOWER … #define DEFAULT_TXPOWER … #define TXPOWER_FROM_DEV(__txpower) … #define TXPOWER_TO_DEV(__txpower) … #endif /* RT61PCI_H */
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