/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* Copyright(c) 2019-2020 Realtek Corporation */ #ifndef __RTW89_CORE_H__ #define __RTW89_CORE_H__ #include <linux/average.h> #include <linux/bitfield.h> #include <linux/dmi.h> #include <linux/firmware.h> #include <linux/iopoll.h> #include <linux/workqueue.h> #include <net/mac80211.h> struct rtw89_dev; struct rtw89_pci_info; struct rtw89_mac_gen_def; struct rtw89_phy_gen_def; struct rtw89_efuse_block_cfg; struct rtw89_h2c_rf_tssi; struct rtw89_fw_txpwr_track_cfg; struct rtw89_phy_rfk_log_fmt; struct rtw89_debugfs; extern const struct ieee80211_ops rtw89_ops; #define MASKBYTE0 … #define MASKBYTE1 … #define MASKBYTE2 … #define MASKBYTE3 … #define MASKBYTE4 … #define MASKHWORD … #define MASKLWORD … #define MASKDWORD … #define RFREG_MASK … #define INV_RF_DATA … #define BYPASS_CR_DATA … #define RTW89_TRACK_WORK_PERIOD … #define RTW89_FORBID_BA_TIMER … #define CFO_TRACK_MAX_USER … #define MAX_RSSI … #define RSSI_FACTOR … #define RTW89_RSSI_RAW_TO_DBM(rssi) … #define RTW89_TX_DIV_RSSI_RAW_TH … #define DELTA_SWINGIDX_SIZE … #define RTW89_RADIOTAP_ROOM_HE … #define RTW89_RADIOTAP_ROOM_EHT … #define RTW89_RADIOTAP_ROOM … #define RTW89_HTC_MASK_VARIANT … #define RTW89_HTC_VARIANT_HE … #define RTW89_HTC_MASK_CTL_ID … #define RTW89_HTC_VARIANT_HE_CID_OM … #define RTW89_HTC_VARIANT_HE_CID_CAS … #define RTW89_HTC_MASK_CTL_INFO … #define RTW89_HTC_MASK_HTC_OM_RX_NSS … enum htc_om_channel_width { … }; #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH … #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS … #define RTW89_HTC_MASK_HTC_OM_TX_NSTS … #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS … #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR … #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS … #define RTW89_TF_PAD … #define RTW89_TF_BASIC_USER_INFO_SZ … #define RTW89_GET_TF_USER_INFO_AID12(data) … #define RTW89_GET_TF_USER_INFO_RUA(data) … #define RTW89_GET_TF_USER_INFO_UL_MCS(data) … enum rtw89_subband { … }; enum rtw89_gain_offset { … }; enum rtw89_hci_type { … }; enum rtw89_core_chip_id { … }; enum rtw89_chip_gen { … }; enum rtw89_cv { … }; enum rtw89_bacam_ver { … }; enum rtw89_core_tx_type { … }; enum rtw89_core_rx_type { … }; enum rtw89_txq_flags { … }; enum rtw89_net_type { … }; enum rtw89_wifi_role { … }; enum rtw89_upd_mode { … }; enum rtw89_self_role { … }; enum rtw89_msk_sO_el { … }; enum rtw89_sch_tx_sel { … }; /* RTW89_ADDR_CAM_SEC_NONE : not enabled * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP */ enum rtw89_add_cam_sec_mode { … }; enum rtw89_sec_key_type { … }; enum rtw89_port { … }; enum rtw89_band { … }; enum rtw89_hw_rate { … }; /* 2G channels, * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ #define RTW89_2G_CH_NUM … /* 5G channels, * 36, 38, 40, 42, 44, 46, 48, 50, * 52, 54, 56, 58, 60, 62, 64, * 100, 102, 104, 106, 108, 110, 112, 114, * 116, 118, 120, 122, 124, 126, 128, 130, * 132, 134, 136, 138, 140, 142, 144, * 149, 151, 153, 155, 157, 159, 161, 163, * 165, 167, 169, 171, 173, 175, 177 */ #define RTW89_5G_CH_NUM … /* 6G channels, * 1, 3, 5, 7, 9, 11, 13, 15, * 17, 19, 21, 23, 25, 27, 29, 33, * 35, 37, 39, 41, 43, 45, 47, 49, * 51, 53, 55, 57, 59, 61, 65, 67, * 69, 71, 73, 75, 77, 79, 81, 83, * 85, 87, 89, 91, 93, 97, 99, 101, * 103, 105, 107, 109, 111, 113, 115, 117, * 119, 121, 123, 125, 129, 131, 133, 135, * 137, 139, 141, 143, 145, 147, 149, 151, * 153, 155, 157, 161, 163, 165, 167, 169, * 171, 173, 175, 177, 179, 181, 183, 185, * 187, 189, 193, 195, 197, 199, 201, 203, * 205, 207, 209, 211, 213, 215, 217, 219, * 221, 225, 227, 229, 231, 233, 235, 237, * 239, 241, 243, 245, 247, 249, 251, 253, */ #define RTW89_6G_CH_NUM … enum rtw89_rate_section { … }; enum rtw89_rate_offset_indexes { … }; enum rtw89_rate_num { … }; enum rtw89_nss { … }; enum rtw89_ntx { … }; enum rtw89_beamforming_type { … }; enum rtw89_ofdma_type { … }; enum rtw89_regulation_type { … }; enum rtw89_reg_6ghz_power { … }; #define RTW89_MIN_VALID_POWER_CONSTRAINT … /* calculate based on ieee80211 Transmit Power Envelope */ struct rtw89_reg_6ghz_tpe { … }; enum rtw89_fw_pkt_ofld_type { … }; struct rtw89_txpwr_byrate { … }; struct rtw89_rate_desc { … }; #define PHY_STS_HDR_LEN … #define RF_PATH_MAX … #define RTW89_MAX_PPDU_CNT … struct rtw89_rx_phy_ppdu { … }; enum rtw89_mac_idx { … }; enum rtw89_phy_idx { … }; enum rtw89_chanctx_idx { … }; enum rtw89_rf_path { … }; enum rtw89_rf_path_bit { … }; enum rtw89_bandwidth { … }; enum rtw89_ps_mode { … }; #define RTW89_2G_BW_NUM … #define RTW89_5G_BW_NUM … #define RTW89_6G_BW_NUM … #define RTW89_BYR_BW_NUM … #define RTW89_PPE_BW_NUM … enum rtw89_pe_duration { … }; enum rtw89_ru_bandwidth { … }; enum rtw89_sc_offset { … }; /* only mgd features can be added to the enum */ enum rtw89_wow_flags { … }; struct rtw89_chan { … }; struct rtw89_chan_rcd { … }; struct rtw89_channel_help_params { … }; struct rtw89_port_reg { … }; struct rtw89_txwd_body { … } __packed; struct rtw89_txwd_body_v1 { … } __packed; struct rtw89_txwd_body_v2 { … } __packed; struct rtw89_txwd_info { … } __packed; struct rtw89_txwd_info_v2 { … } __packed; struct rtw89_rx_desc_info { … }; struct rtw89_rxdesc_short { … } __packed; struct rtw89_rxdesc_short_v2 { … } __packed; struct rtw89_rxdesc_long { … } __packed; struct rtw89_rxdesc_long_v2 { … } __packed; struct rtw89_tx_desc_info { … }; struct rtw89_core_tx_request { … }; struct rtw89_txq { … }; struct rtw89_mac_ax_gnt { … } __packed; struct rtw89_mac_ax_wl_act { … }; #define RTW89_MAC_AX_COEX_GNT_NR … struct rtw89_mac_ax_coex_gnt { … }; enum rtw89_btc_ncnt { … }; enum rtw89_btc_btinfo { … }; enum rtw89_btc_dcnt { … }; enum rtw89_btc_wl_state_cnt { … }; enum rtw89_btc_bt_state_cnt { … }; enum rtw89_btc_bt_profile { … }; struct rtw89_btc_ant_info { … }; struct rtw89_btc_ant_info_v7 { … } __packed; enum rtw89_tfc_dir { … }; struct rtw89_btc_wl_smap { … }; enum rtw89_tfc_lv { … }; #define RTW89_TP_SHIFT … DECLARE_EWMA(tp, 10, 2); struct rtw89_traffic_stats { … }; struct rtw89_btc_chdef { … }; struct rtw89_btc_statistic { … }; #define BTC_WL_RSSI_THMAX … struct rtw89_btc_wl_link_info { … }; rtw89_btc_wl_state_map; struct rtw89_btc_bt_hfp_desc { … }; struct rtw89_btc_bt_hid_desc { … }; struct rtw89_btc_bt_a2dp_desc { … }; struct rtw89_btc_bt_pan_desc { … }; struct rtw89_btc_bt_rfk_info { … }; rtw89_btc_bt_rfk_info_map; struct rtw89_btc_bt_ver_info { … }; struct rtw89_btc_bool_sta_chg { … }; struct rtw89_btc_u8_sta_chg { … }; struct rtw89_btc_wl_scan_info { … }; struct rtw89_btc_wl_dbcc_info { … }; struct rtw89_btc_wl_active_role { … }; struct rtw89_btc_wl_active_role_v1 { … }; struct rtw89_btc_wl_active_role_v2 { … }; struct rtw89_btc_wl_active_role_v7 { … } __packed; struct rtw89_btc_wl_role_info_bpos { … }; struct rtw89_btc_wl_scc_ctrl { … }; rtw89_btc_wl_role_info_map; struct rtw89_btc_wl_role_info { … }; struct rtw89_btc_wl_role_info_v1 { … }; struct rtw89_btc_wl_role_info_v2 { … }; struct rtw89_btc_wl_rlink { … } __packed; #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER … struct rtw89_btc_wl_role_info_v7 { … } __packed; struct rtw89_btc_wl_role_info_v8 { … } __packed; struct rtw89_btc_wl_ver_info { … }; struct rtw89_btc_wl_afh_info { … } __packed; struct rtw89_btc_wl_rfk_info { … }; struct rtw89_btc_bt_smap { … }; rtw89_btc_bt_state_map; #define BTC_BT_RSSI_THMAX … #define BTC_BT_AFH_GROUP … #define BTC_BT_AFH_LE_GROUP … struct rtw89_btc_bt_link_info { … }; struct rtw89_btc_3rdcx_info { … }; struct rtw89_btc_dm_emap { … }; rtw89_btc_dm_error_map; struct rtw89_btc_rf_para { … }; struct rtw89_btc_wl_nhm { … }; struct rtw89_btc_wl_info { … }; struct rtw89_btc_module { … }; struct rtw89_btc_module_v7 { … } __packed; rtw89_btc_module_info; #define RTW89_BTC_DM_MAXSTEP … #define RTW89_BTC_DM_CNT_MAX … struct rtw89_btc_dm_step { … }; struct rtw89_btc_init_info { … }; struct rtw89_btc_init_info_v7 { … } __packed; rtw89_btc_init_info_u; struct rtw89_btc_wl_tx_limit_para { … }; enum rtw89_btc_bt_scan_type { … }; enum rtw89_btc_ble_scan_type { … }; #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE … #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE … struct rtw89_btc_bt_scan_info_v1 { … } __packed; struct rtw89_btc_bt_scan_info_v2 { … } __packed; struct rtw89_btc_fbtc_btscan_v1 { … } __packed; struct rtw89_btc_fbtc_btscan_v2 { … } __packed; struct rtw89_btc_fbtc_btscan_v7 { … } __packed; rtw89_btc_fbtc_btscan; struct rtw89_btc_bt_info { … }; struct rtw89_btc_cx { … }; struct rtw89_btc_fbtc_tdma { … } __packed; struct rtw89_btc_fbtc_tdma_v3 { … } __packed; rtw89_btc_fbtc_tdma_le32; #define CXMREG_MAX … #define CXMREG_MAX_V2 … #define FCXMAX_STEP … #define BTC_CYCLE_SLOT_MAX … enum rtw89_btc_bt_sta_counter { … }; enum rtw89_btc_bt_sta_counter_v105 { … }; struct rtw89_btc_fbtc_rpt_ctrl_v1 { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_info { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_v4 { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_v5 { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_v105 { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_v7 { … } __packed; struct rtw89_btc_fbtc_rpt_ctrl_v8 { … } __packed; rtw89_btc_fbtc_rpt_ctrl_ver_info; enum rtw89_fbtc_ext_ctrl_type { … }; rtw89_btc_fbtc_rxflct; enum rtw89_btc_cxst_state { … }; enum rtw89_btc_cxevnt { … }; enum { … }; enum btc_slot_type { … }; enum { … }; enum { … }; enum { … }; enum rtw89_btc_afh_map_type { … }; #define BTC_DBG_MAX1 … struct rtw89_btc_fbtc_gpio_dbg_v1 { … } __packed; struct rtw89_btc_fbtc_gpio_dbg_v7 { … } __packed; rtw89_btc_fbtc_gpio_dbg; struct rtw89_btc_fbtc_mreg_val_v1 { … } __packed; struct rtw89_btc_fbtc_mreg_val_v2 { … } __packed; struct rtw89_btc_fbtc_mreg_val_v7 { … } __packed; rtw89_btc_fbtc_mreg_val; #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) … struct rtw89_btc_fbtc_mreg { … } __packed; struct rtw89_btc_fbtc_slot { … } __packed; struct rtw89_btc_fbtc_slots { … } __packed; struct rtw89_btc_fbtc_slot_v7 { … } __packed; struct rtw89_btc_fbtc_slot_u16 { … } __packed; struct rtw89_btc_fbtc_1slot_v7 { … } __packed; struct rtw89_btc_fbtc_slots_v7 { … } __packed; rtw89_btc_fbtc_slots_info __packed; struct rtw89_btc_fbtc_step { … } __packed; struct rtw89_btc_fbtc_steps_v2 { … } __packed; struct rtw89_btc_fbtc_steps_v3 { … } __packed; rtw89_btc_fbtc_steps_info; struct rtw89_btc_fbtc_cysta_v2 { … } __packed; struct rtw89_btc_fbtc_fdd_try_info { … } __packed; struct rtw89_btc_fbtc_cycle_time_info { … } __packed; struct rtw89_btc_fbtc_cycle_time_info_v5 { … } __packed; struct rtw89_btc_fbtc_a2dp_trx_stat { … } __packed; struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { … } __packed; struct rtw89_btc_fbtc_cycle_a2dp_empty_info { … } __packed; struct rtw89_btc_fbtc_cycle_leak_info { … } __packed; struct rtw89_btc_fbtc_cycle_leak_info_v7 { … } __packed; #define RTW89_BTC_FDDT_PHASE_CYCLE … #define RTW89_BTC_FDDT_TRAIN_STEP … struct rtw89_btc_fbtc_cycle_fddt_info { … } __packed; #define RTW89_BTC_FDDT_CELL_TRAIN_STATE … #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE … struct rtw89_btc_fbtc_cycle_fddt_info_v5 { … } __packed; struct rtw89_btc_fbtc_fddt_cell_status { … } __packed; struct rtw89_btc_fbtc_cysta_v3 { … } __packed; #define FDD_TRAIN_WL_DIRECTION … #define FDD_TRAIN_WL_RSSI_LEVEL … #define FDD_TRAIN_BT_RSSI_LEVEL … struct rtw89_btc_fbtc_cysta_v4 { … } __packed; struct rtw89_btc_fbtc_cysta_v5 { … } __packed; struct rtw89_btc_fbtc_cysta_v7 { … } __packed; rtw89_btc_fbtc_cysta_info; struct rtw89_btc_fbtc_cynullsta_v1 { … } __packed; struct rtw89_btc_fbtc_cynullsta_v2 { … } __packed; struct rtw89_btc_fbtc_cynullsta_v7 { … } __packed; rtw89_btc_fbtc_cynullsta_info; struct rtw89_btc_fbtc_btver_v1 { … } __packed; struct rtw89_btc_fbtc_btver_v7 { … } __packed; rtw89_btc_fbtc_btver __packed; struct rtw89_btc_fbtc_btafh { … } __packed; struct rtw89_btc_fbtc_btafh_v2 { … } __packed; struct rtw89_btc_fbtc_btafh_v7 { … } __packed; struct rtw89_btc_fbtc_btdevinfo { … } __packed; #define RTW89_BTC_WL_DEF_TX_PWR … struct rtw89_btc_rf_trx_para { … }; struct rtw89_btc_trx_info { … }; rtw89_btc_fbtc_slot_u; struct rtw89_btc_dm { … }; struct rtw89_btc_ctrl { … }; struct rtw89_btc_ctrl_v7 { … } __packed; rtw89_btc_ctrl_list; struct rtw89_btc_dbg { … }; enum rtw89_btc_btf_fw_event { … }; enum btf_fw_event_report { … }; enum rtw_btc_btf_reg_type { … }; struct rtw89_btc_rpt_cmn_info { … } __packed; rtw89_btc_fbtc_btafh_info; struct rtw89_btc_report_ctrl_state { … }; struct rtw89_btc_rpt_fbtc_tdma { … }; struct rtw89_btc_rpt_fbtc_slots { … }; struct rtw89_btc_rpt_fbtc_cysta { … }; struct rtw89_btc_rpt_fbtc_step { … }; struct rtw89_btc_rpt_fbtc_nullsta { … }; struct rtw89_btc_rpt_fbtc_mreg { … }; struct rtw89_btc_rpt_fbtc_gpio_dbg { … }; struct rtw89_btc_rpt_fbtc_btver { … }; struct rtw89_btc_rpt_fbtc_btscan { … }; struct rtw89_btc_rpt_fbtc_btafh { … }; struct rtw89_btc_rpt_fbtc_btdev { … }; enum rtw89_btc_btfre_type { … }; struct rtw89_btc_btf_fwinfo { … }; struct rtw89_btc_ver { … }; #define RTW89_BTC_POLICY_MAXLEN … struct rtw89_btc { … }; enum rtw89_btc_hmsg { … }; enum rtw89_ra_mode { … }; enum rtw89_ra_report_mode { … }; enum rtw89_dig_noisy_level { … }; enum rtw89_gi_ltf { … }; enum rtw89_rx_frame_type { … }; enum rtw89_efuse_block { … }; struct rtw89_ra_info { … }; #define RTW89_PPDU_MAC_INFO_USR_SIZE … #define RTW89_PPDU_MAC_INFO_SIZE … #define RTW89_PPDU_MAC_RX_CNT_SIZE … #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 … #define RTW89_MAX_RX_AGG_NUM … #define RTW89_MAX_TX_AGG_NUM … struct rtw89_ampdu_params { … }; struct rtw89_ra_report { … }; DECLARE_EWMA(rssi, 10, 16); DECLARE_EWMA(evm, 10, 16); DECLARE_EWMA(snr, 10, 16); struct rtw89_ba_cam_entry { … }; #define RTW89_MAX_ADDR_CAM_NUM … #define RTW89_MAX_BSSID_CAM_NUM … #define RTW89_MAX_SEC_CAM_NUM … #define RTW89_MAX_BA_CAM_NUM … #define RTW89_SEC_CAM_IN_ADDR_CAM … struct rtw89_addr_cam_entry { … }; struct rtw89_bssid_cam_entry { … }; struct rtw89_sec_cam_entry { … }; struct rtw89_sta { … }; struct rtw89_efuse { … }; struct rtw89_phy_rate_pattern { … }; struct rtw89_tx_wait_info { … }; struct rtw89_tx_skb_data { … }; #define RTW89_ROC_IDLE_TIMEOUT … #define RTW89_ROC_TX_TIMEOUT … enum rtw89_roc_state { … }; struct rtw89_roc { … }; #define RTW89_P2P_MAX_NOA_NUM … struct rtw89_p2p_ie_head { … } __packed; struct rtw89_noa_attr_head { … } __packed; struct rtw89_p2p_noa_ie { … } __packed; struct rtw89_p2p_noa_setter { … }; struct rtw89_vif { … }; enum rtw89_lv1_rcvy_step { … }; struct rtw89_hci_ops { … }; struct rtw89_hci_info { … }; struct rtw89_chip_ops { … }; enum rtw89_dma_ch { … }; #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) … enum rtw89_mlo_dbcc_mode { … }; enum rtw89_scan_be_operation { … }; enum rtw89_scan_be_mode { … }; enum rtw89_scan_be_opmode { … }; struct rtw89_scan_option { … }; enum rtw89_qta_mode { … }; struct rtw89_hfc_ch_cfg { … }; struct rtw89_hfc_ch_info { … }; struct rtw89_hfc_pub_cfg { … }; struct rtw89_hfc_pub_info { … }; struct rtw89_hfc_prec_cfg { … }; struct rtw89_hfc_param { … }; struct rtw89_hfc_param_ini { … }; struct rtw89_dle_size { … }; struct rtw89_wde_quota { … }; struct rtw89_ple_quota { … }; struct rtw89_rsvd_quota { … }; struct rtw89_dle_rsvd_size { … }; struct rtw89_dle_mem { … }; struct rtw89_reg_def { … }; struct rtw89_reg2_def { … }; struct rtw89_reg3_def { … }; struct rtw89_reg5_def { … }; struct rtw89_reg_imr { … }; struct rtw89_phy_table { … }; struct rtw89_txpwr_table { … }; struct rtw89_txpwr_rule_2ghz { … }; struct rtw89_txpwr_rule_5ghz { … }; struct rtw89_txpwr_rule_6ghz { … }; struct rtw89_tx_shape { … }; struct rtw89_rfe_parms { … }; struct rtw89_rfe_parms_conf { … }; #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE … struct rtw89_txpwr_conf { … }; static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, const struct rtw89_txpwr_conf *conf) { … } #define rtw89_txpwr_conf_valid(conf) … #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) … struct rtw89_txpwr_byrate_data { … }; struct rtw89_txpwr_lmt_2ghz_data { … }; struct rtw89_txpwr_lmt_5ghz_data { … }; struct rtw89_txpwr_lmt_6ghz_data { … }; struct rtw89_txpwr_lmt_ru_2ghz_data { … }; struct rtw89_txpwr_lmt_ru_5ghz_data { … }; struct rtw89_txpwr_lmt_ru_6ghz_data { … }; struct rtw89_tx_shape_lmt_data { … }; struct rtw89_tx_shape_lmt_ru_data { … }; struct rtw89_rfe_data { … }; struct rtw89_page_regs { … }; struct rtw89_imr_info { … }; struct rtw89_imr_table { … }; struct rtw89_xtal_info { … }; struct rtw89_rrsr_cfgs { … }; struct rtw89_rfkill_regs { … }; struct rtw89_dig_regs { … }; struct rtw89_edcca_regs { … }; struct rtw89_phy_ul_tb_info { … }; struct rtw89_antdiv_stats { … }; struct rtw89_antdiv_info { … }; enum rtw89_chanctx_state { … }; enum rtw89_chanctx_callbacks { … }; struct rtw89_chanctx_listener { … }; struct rtw89_chip_info { … }; rtw89_bus_info; struct rtw89_driver_info { … }; enum rtw89_hcifc_mode { … }; struct rtw89_dle_info { … }; enum rtw89_host_rpr_mode { … }; #define RTW89_COMPLETION_BUF_SIZE … #define RTW89_WAIT_COND_IDLE … struct rtw89_completion_data { … }; struct rtw89_wait_info { … }; #define RTW89_WAIT_FOR_COND_TIMEOUT … static inline void rtw89_init_wait(struct rtw89_wait_info *wait) { … } struct rtw89_mac_info { … }; enum rtw89_fwdl_check_type { … }; enum rtw89_fw_type { … }; enum rtw89_fw_feature { … }; struct rtw89_fw_suit { … }; #define RTW89_FW_VER_CODE(major, minor, sub, idx) … #define RTW89_FW_SUIT_VER_CODE(s) … #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) … #define RTW89_FW_HDR_VER_CODE(fw_hdr) … struct rtw89_fw_req_info { … }; struct rtw89_fw_log { … }; struct rtw89_fw_elm_info { … }; enum rtw89_fw_mss_dev_type { … }; struct rtw89_fw_secure { … }; struct rtw89_fw_info { … }; #define RTW89_CHK_FW_FEATURE(_feat, _fw) … #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) … struct rtw89_cam_info { … }; enum rtw89_sar_sources { … }; enum rtw89_sar_subband { … }; struct rtw89_sar_cfg_common { … }; struct rtw89_sar_info { … }; enum rtw89_tas_state { … }; #define RTW89_TAS_MAX_WINDOW … struct rtw89_tas_info { … }; struct rtw89_chanctx_cfg { … }; enum rtw89_chanctx_changes { … }; enum rtw89_entity_mode { … }; struct rtw89_chanctx { … }; struct rtw89_edcca_bak { … }; enum rtw89_dm_type { … }; struct rtw89_hal { … }; #define RTW89_MAX_MAC_ID_NUM … #define RTW89_MAX_PKT_OFLD_NUM … enum rtw89_flags { … }; enum rtw89_quirks { … }; enum rtw89_pkt_drop_sel { … }; struct rtw89_pkt_drop_params { … }; struct rtw89_pkt_stat { … }; DECLARE_EWMA(thermal, 4, 4); struct rtw89_phy_stat { … }; enum rtw89_rfk_report_state { … }; struct rtw89_rfk_wait_info { … }; #define RTW89_DACK_PATH_NR … #define RTW89_DACK_IDX_NR … #define RTW89_DACK_MSBK_NR … struct rtw89_dack_info { … }; enum rtw89_rfk_chs_nrs { … }; struct rtw89_rfk_mcc_info { … }; #define RTW89_IQK_CHS_NR … #define RTW89_IQK_PATH_NR … struct rtw89_lck_info { … }; struct rtw89_rx_dck_info { … }; struct rtw89_iqk_info { … }; #define RTW89_DPK_RF_PATH … #define RTW89_DPK_AVG_THERMAL_NUM … #define RTW89_DPK_BKUP_NUM … struct rtw89_dpk_bkup_para { … }; struct rtw89_dpk_info { … }; struct rtw89_fem_info { … }; struct rtw89_phy_ch_info { … }; struct rtw89_agc_gaincode_set { … }; #define IGI_RSSI_TH_NUM … #define FA_TH_NUM … #define LNA_GAIN_NUM … #define TIA_GAIN_NUM … struct rtw89_dig_info { … }; enum rtw89_multi_cfo_mode { … }; enum rtw89_phy_cfo_status { … }; enum rtw89_phy_cfo_ul_ofdma_acc_mode { … }; struct rtw89_cfo_tracking_info { … }; enum rtw89_tssi_mode { … }; enum rtw89_tssi_alimk_band { … }; /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ #define TSSI_TRIM_CH_GROUP_NUM … #define TSSI_TRIM_CH_GROUP_NUM_6G … #define TSSI_CCK_CH_GROUP_NUM … #define TSSI_MCS_2G_CH_GROUP_NUM … #define TSSI_MCS_5G_CH_GROUP_NUM … #define TSSI_MCS_6G_CH_GROUP_NUM … #define TSSI_MCS_CH_GROUP_NUM … #define TSSI_MAX_CH_NUM … #define TSSI_ALIMK_VALUE_NUM … struct rtw89_tssi_info { … }; struct rtw89_power_trim_info { … }; struct rtw89_regd { … }; #define RTW89_REGD_MAX_COUNTRY_NUM … #define RTW89_5GHZ_UNII4_CHANNEL_NUM … #define RTW89_5GHZ_UNII4_START_INDEX … struct rtw89_regulatory_info { … }; enum rtw89_ifs_clm_application { … }; enum rtw89_env_racing_lv { … }; struct rtw89_ccx_para_info { … }; enum rtw89_ccx_edcca_opt_sc_idx { … }; enum rtw89_ccx_edcca_opt_bw_idx { … }; #define RTW89_NHM_TH_NUM … #define RTW89_FAHM_TH_NUM … #define RTW89_NHM_RPT_NUM … #define RTW89_FAHM_RPT_NUM … #define RTW89_IFS_CLM_NUM … struct rtw89_env_monitor_info { … }; enum rtw89_ser_rcvy_step { … }; struct rtw89_ser { … }; enum rtw89_mac_ax_ps_mode { … }; enum rtw89_last_rpwm_mode { … }; struct rtw89_lps_parm { … }; struct rtw89_ppdu_sts_info { … }; struct rtw89_early_h2c { … }; struct rtw89_hw_scan_info { … }; enum rtw89_phy_bb_gain_band { … }; enum rtw89_phy_gain_band_be { … }; enum rtw89_phy_bb_bw_be { … }; enum rtw89_bw20_sc { … }; enum rtw89_cmac_table_bw { … }; enum rtw89_phy_bb_rxsc_num { … }; struct rtw89_phy_bb_gain_info { … }; struct rtw89_phy_bb_gain_info_be { … }; struct rtw89_phy_efuse_gain { … }; #define RTW89_MAX_PATTERN_NUM … #define RTW89_MAX_PATTERN_MASK_SIZE … #define RTW89_MAX_PATTERN_SIZE … struct rtw89_wow_cam_info { … }; struct rtw89_wow_key_info { … } __packed; struct rtw89_wow_gtk_info { … } __packed; struct rtw89_wow_aoac_report { … }; struct rtw89_wow_param { … }; struct rtw89_mcc_limit { … }; struct rtw89_mcc_policy { … }; struct rtw89_mcc_role { … }; struct rtw89_mcc_bt_role { … }; struct rtw89_mcc_courtesy { … }; enum rtw89_mcc_plan { … }; struct rtw89_mcc_pattern { … }; struct rtw89_mcc_sync { … }; struct rtw89_mcc_config { … }; enum rtw89_mcc_mode { … }; struct rtw89_mcc_info { … }; struct rtw89_dev { … }; static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req) { … } static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) { … } static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) { … } static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) { … } static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) { … } static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) { … } static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) { … } static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) { … } static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) { … } static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) { … } static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) { … } static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, bool drop) { … } static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) { … } static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) { … } static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) { … } static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) { … } static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) { … } static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) { … } static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) { … } static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) { … } static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) { … } static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) { … } static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { … } static inline struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) { … } static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) { … } static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) { … } static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) { … } static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) { … } static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) { … } static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) { … } static inline void rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) { … } static inline void rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) { … } static inline void rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) { … } static inline void rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) { … } static inline void rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) { … } static inline void rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) { … } static inline u32 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) { … } static inline u16 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) { … } static inline u8 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) { … } static inline void rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) { … } static inline void rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) { … } static inline void rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) { … } static inline u32 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask) { … } static inline void rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask, u32 data) { … } static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) { … } static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, struct ieee80211_txq *txq) { … } static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) { … } static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) { … } static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) { … } static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) { … } static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) { … } static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) { … } static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) { … } static inline enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) { … } static inline enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) { … } static inline enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) { … } static inline enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) { … } static inline struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta) { … } static inline struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta) { … } static inline void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, struct rtw89_channel_help_params *p, const struct rtw89_chan *chan, enum rtw89_mac_idx mac_idx, enum rtw89_phy_idx phy_idx) { … } static inline void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, struct rtw89_channel_help_params *p, const struct rtw89_chan *chan, enum rtw89_mac_idx mac_idx, enum rtw89_phy_idx phy_idx) { … } static inline const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, enum rtw89_chanctx_idx idx) { … } static inline const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, enum rtw89_chanctx_idx idx) { … } static inline const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, enum rtw89_chanctx_idx idx) { … } static inline const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) { … } static inline void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) { … } static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan) { … } static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool start) { … } static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) { … } static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) { … } static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, struct rtw89_rx_phy_ppdu *phy_ppdu, struct ieee80211_rx_status *status) { … } static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, struct rtw89_rx_phy_ppdu *phy_ppdu) { … } static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, enum rtw89_phy_idx phy_idx) { … } static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) { … } static inline void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) { … } static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) { … } static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, const struct rtw89_txpwr_table *tbl) { … } static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) { … } static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, enum rtw89_phy_idx phy_idx) { … } static inline void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, struct rtw89_rx_desc_info *desc_info, u8 *data, u32 data_offset) { … } static inline void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, struct rtw89_tx_desc_info *desc_info, void *txdesc) { … } static inline void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, struct rtw89_tx_desc_info *desc_info, void *txdesc) { … } static inline void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex_gnt *gnt_cfg) { … } static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) { … } static inline int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 *tx_en, enum rtw89_sch_tx_sel sel) { … } static inline int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) { … } static inline int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta) { … } static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) { … } static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) { … } static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, enum rtw89_fw_type type) { … } static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, unsigned int length) { … } static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, struct rtw89_tx_skb_data *skb_data, bool tx_done) { … } static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) { … } static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) { … } int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); int rtw89_h2c_tx(struct rtw89_dev *rtwdev, struct sk_buff *skb, bool fwdl); void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, int qsel, unsigned int timeout); void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, struct rtw89_tx_desc_info *desc_info, void *txdesc); void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, struct rtw89_tx_desc_info *desc_info, void *txdesc); void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, struct rtw89_tx_desc_info *desc_info, void *txdesc); void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, struct rtw89_tx_desc_info *desc_info, void *txdesc); void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, struct rtw89_tx_desc_info *desc_info, void *txdesc); void rtw89_core_rx(struct rtw89_dev *rtwdev, struct rtw89_rx_desc_info *desc_info, struct sk_buff *skb); void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, struct rtw89_rx_desc_info *desc_info, u8 *data, u32 data_offset); void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, struct rtw89_rx_desc_info *desc_info, u8 *data, u32 data_offset); void rtw89_core_napi_start(struct rtw89_dev *rtwdev); void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); int rtw89_core_napi_init(struct rtw89_dev *rtwdev); void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); int rtw89_core_sta_add(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, struct cfg80211_tid_config *tid_config); void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); int rtw89_core_init(struct rtw89_dev *rtwdev); void rtw89_core_deinit(struct rtw89_dev *rtwdev); int rtw89_core_register(struct rtw89_dev *rtwdev); void rtw89_core_unregister(struct rtw89_dev *rtwdev); struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, u32 bus_data_size, const struct rtw89_chip_info *chip); void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, struct rtw89_chan *chan); int rtw89_set_channel(struct rtw89_dev *rtwdev); void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_chan *chan); u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); int rtw89_regd_setup(struct rtw89_dev *rtwdev); int rtw89_regd_init(struct rtw89_dev *rtwdev, void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, struct rtw89_traffic_stats *stats); int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, const struct rtw89_completion_data *data); int rtw89_core_start(struct rtw89_dev *rtwdev); void rtw89_core_stop(struct rtw89_dev *rtwdev); void rtw89_core_update_beacon_work(struct work_struct *work); void rtw89_roc_work(struct work_struct *work); void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, const u8 *mac_addr, bool hw_scan); void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, bool hw_scan); int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool active); void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); #endif
Codebase Browser
linux