linux/sound/soc/mediatek/mt8195/mt8195-afe-clk.c

// SPDX-License-Identifier: GPL-2.0
/*
 * mt8195-afe-clk.c  --  Mediatek 8195 afe clock ctrl
 *
 * Copyright (c) 2021 MediaTek Inc.
 * Author: Bicycle Tsai <[email protected]>
 *         Trevor Wu <[email protected]>
 */

#include <linux/clk.h>

#include "mt8195-afe-common.h"
#include "mt8195-afe-clk.h"
#include "mt8195-reg.h"
#include "mt8195-audsys-clk.h"

static const char *aud_clks[MT8195_CLK_NUM] = …;

struct mt8195_afe_tuner_cfg { … };

static struct mt8195_afe_tuner_cfg mt8195_afe_tuner_cfgs[MT8195_AUD_PLL_NUM] = …;

static struct mt8195_afe_tuner_cfg *mt8195_afe_found_apll_tuner(unsigned int id)
{ … }

static int mt8195_afe_init_apll_tuner(unsigned int id)
{ … }

static int mt8195_afe_setup_apll_tuner(struct mtk_base_afe *afe,
				       unsigned int id)
{ … }

static int mt8195_afe_enable_tuner_clk(struct mtk_base_afe *afe,
				       unsigned int id)
{ … }

static int mt8195_afe_disable_tuner_clk(struct mtk_base_afe *afe,
					unsigned int id)
{ … }

static int mt8195_afe_enable_apll_tuner(struct mtk_base_afe *afe,
					unsigned int id)
{ … }

static int mt8195_afe_disable_apll_tuner(struct mtk_base_afe *afe,
					 unsigned int id)
{ … }

int mt8195_afe_get_mclk_source_clk_id(int sel)
{ … }

int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
{ … }

int mt8195_afe_get_default_mclk_source_by_rate(int rate)
{ … }

int mt8195_afe_init_clock(struct mtk_base_afe *afe)
{ … }

int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
{ … }
EXPORT_SYMBOL_GPL(…);

void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
{ … }
EXPORT_SYMBOL_GPL(…);

int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk)
{ … }

void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk)
{ … }

int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
{ … }

void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
{ … }

int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
			    unsigned int rate)
{ … }

int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
			      struct clk *parent)
{ … }

static unsigned int get_top_cg_reg(unsigned int cg_type)
{ … }

static unsigned int get_top_cg_mask(unsigned int cg_type)
{ … }

static unsigned int get_top_cg_on_val(unsigned int cg_type)
{ … }

static unsigned int get_top_cg_off_val(unsigned int cg_type)
{ … }

static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
{ … }

static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
{ … }

int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
{ … }

int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
{ … }

static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe)
{ … }

static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe)
{ … }

static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe)
{ … }

static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe)
{ … }

int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe)
{ … }

int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe)
{ … }