/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) STMicroelectronics 2018 - All Rights Reserved * Author: Philippe Peurichard <[email protected]>, * Pascal Paillet <[email protected]> for STMicroelectronics. */ #ifndef __LINUX_MFD_STPMIC1_H #define __LINUX_MFD_STPMIC1_H #define TURN_ON_SR … #define TURN_OFF_SR … #define ICC_LDO_TURN_OFF_SR … #define ICC_BUCK_TURN_OFF_SR … #define RREQ_STATE_SR … #define VERSION_SR … #define MAIN_CR … #define PADS_PULL_CR … #define BUCKS_PD_CR … #define LDO14_PD_CR … #define LDO56_VREF_PD_CR … #define VBUS_DET_VIN_CR … #define PKEY_TURNOFF_CR … #define BUCKS_MASK_RANK_CR … #define BUCKS_MASK_RESET_CR … #define LDOS_MASK_RANK_CR … #define LDOS_MASK_RESET_CR … #define WCHDG_CR … #define WCHDG_TIMER_CR … #define BUCKS_ICCTO_CR … #define LDOS_ICCTO_CR … #define BUCK1_ACTIVE_CR … #define BUCK2_ACTIVE_CR … #define BUCK3_ACTIVE_CR … #define BUCK4_ACTIVE_CR … #define VREF_DDR_ACTIVE_CR … #define LDO1_ACTIVE_CR … #define LDO2_ACTIVE_CR … #define LDO3_ACTIVE_CR … #define LDO4_ACTIVE_CR … #define LDO5_ACTIVE_CR … #define LDO6_ACTIVE_CR … #define BUCK1_STDBY_CR … #define BUCK2_STDBY_CR … #define BUCK3_STDBY_CR … #define BUCK4_STDBY_CR … #define VREF_DDR_STDBY_CR … #define LDO1_STDBY_CR … #define LDO2_STDBY_CR … #define LDO3_STDBY_CR … #define LDO4_STDBY_CR … #define LDO5_STDBY_CR … #define LDO6_STDBY_CR … #define BST_SW_CR … #define INT_PENDING_R1 … #define INT_PENDING_R2 … #define INT_PENDING_R3 … #define INT_PENDING_R4 … #define INT_DBG_LATCH_R1 … #define INT_DBG_LATCH_R2 … #define INT_DBG_LATCH_R3 … #define INT_DBG_LATCH_R4 … #define INT_CLEAR_R1 … #define INT_CLEAR_R2 … #define INT_CLEAR_R3 … #define INT_CLEAR_R4 … #define INT_MASK_R1 … #define INT_MASK_R2 … #define INT_MASK_R3 … #define INT_MASK_R4 … #define INT_SET_MASK_R1 … #define INT_SET_MASK_R2 … #define INT_SET_MASK_R3 … #define INT_SET_MASK_R4 … #define INT_CLEAR_MASK_R1 … #define INT_CLEAR_MASK_R2 … #define INT_CLEAR_MASK_R3 … #define INT_CLEAR_MASK_R4 … #define INT_SRC_R1 … #define INT_SRC_R2 … #define INT_SRC_R3 … #define INT_SRC_R4 … #define PMIC_MAX_REGISTER_ADDRESS … #define STPMIC1_PMIC_NUM_IRQ_REGS … #define TURN_OFF_SR_ICC_EVENT … #define LDO_VOLTAGE_MASK … #define BUCK_VOLTAGE_MASK … #define LDO_BUCK_VOLTAGE_SHIFT … #define LDO_ENABLE_MASK … #define BUCK_ENABLE_MASK … #define BUCK_HPLP_ENABLE_MASK … #define BUCK_HPLP_SHIFT … #define STDBY_ENABLE_MASK … #define BUCKS_PD_CR_REG_MASK … #define BUCK_MASK_RANK_REGISTER_MASK … #define BUCK_MASK_RESET_REGISTER_MASK … #define LDO1234_PULL_DOWN_REGISTER_MASK … #define LDO56_VREF_PD_CR_REG_MASK … #define LDO_MASK_RANK_REGISTER_MASK … #define LDO_MASK_RESET_REGISTER_MASK … #define BUCK1_PULL_DOWN_REG … #define BUCK1_PULL_DOWN_MASK … #define BUCK2_PULL_DOWN_REG … #define BUCK2_PULL_DOWN_MASK … #define BUCK3_PULL_DOWN_REG … #define BUCK3_PULL_DOWN_MASK … #define BUCK4_PULL_DOWN_REG … #define BUCK4_PULL_DOWN_MASK … #define LDO1_PULL_DOWN_REG … #define LDO1_PULL_DOWN_MASK … #define LDO2_PULL_DOWN_REG … #define LDO2_PULL_DOWN_MASK … #define LDO3_PULL_DOWN_REG … #define LDO3_PULL_DOWN_MASK … #define LDO4_PULL_DOWN_REG … #define LDO4_PULL_DOWN_MASK … #define LDO5_PULL_DOWN_REG … #define LDO5_PULL_DOWN_MASK … #define LDO6_PULL_DOWN_REG … #define LDO6_PULL_DOWN_MASK … #define VREF_DDR_PULL_DOWN_REG … #define VREF_DDR_PULL_DOWN_MASK … #define BUCKS_ICCTO_CR_REG_MASK … #define LDOS_ICCTO_CR_REG_MASK … #define LDO_BYPASS_MASK … /* Main PMIC Control Register * MAIN_CR * Address : 0x10 */ #define OCP_OFF_DBG … #define PWRCTRL_POLARITY_HIGH … #define PWRCTRL_ENABLE … #define RESTART_REQUEST_ENABLE … #define SOFTWARE_SWITCH_OFF … /* Main PMIC PADS Control Register * PADS_PULL_CR * Address : 0x11 */ #define WAKEUP_DETECTOR_DISABLED … #define PWRCTRL_PD_ACTIVE … #define PWRCTRL_PU_ACTIVE … #define WAKEUP_PD_ACTIVE … #define PONKEY_PU_INACTIVE … /* Main PMIC VINLOW Control Register * VBUS_DET_VIN_CRC DMSC * Address : 0x15 */ #define SWIN_DETECTOR_ENABLED … #define SWOUT_DETECTOR_ENABLED … #define VINLOW_ENABLED … #define VINLOW_CTRL_REG_MASK … /* USB Control Register * Address : 0x40 */ #define BOOST_OVP_DISABLED … #define VBUS_OTG_DETECTION_DISABLED … #define SW_OUT_DISCHARGE … #define VBUS_OTG_DISCHARGE … #define OCP_LIMIT_HIGH … #define SWIN_SWOUT_ENABLED … #define USBSW_OTG_SWITCH_ENABLED … #define BOOST_ENABLED … /* PKEY_TURNOFF_CR * Address : 0x16 */ #define PONKEY_PWR_OFF … #define PONKEY_CC_FLAG_CLEAR … #define PONKEY_TURNOFF_TIMER_MASK … #define PONKEY_TURNOFF_MASK … /* * struct stpmic1 - stpmic1 master device for sub-drivers * @dev: master device of the chip (can be used to access platform data) * @irq: main IRQ number * @regmap_irq_chip_data: irq chip data */ struct stpmic1 { … }; #endif /* __LINUX_MFD_STPMIC1_H */
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