/* * SMU_7_1_1 Register documentation * * Copyright (C) 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef SMU_7_1_1_SH_MASK_H #define SMU_7_1_1_SH_MASK_H #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK … #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT … #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK … #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT … #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK … #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT … #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK … #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT … #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK … #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT … #define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK … #define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT … #define CG_DCLK_STATUS__DCLK_STATUS_MASK … #define CG_DCLK_STATUS__DCLK_STATUS__SHIFT … #define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK … #define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT … #define CG_VCLK_CNTL__VCLK_DIVIDER_MASK … #define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT … #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK … #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT … #define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK … #define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT … #define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK … #define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT … #define CG_VCLK_STATUS__VCLK_STATUS_MASK … #define CG_VCLK_STATUS__VCLK_STATUS__SHIFT … #define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK … #define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT … #define CG_ECLK_CNTL__ECLK_DIVIDER_MASK … #define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT … #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK … #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT … #define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK … #define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT … #define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK … #define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT … #define CG_ECLK_STATUS__ECLK_STATUS_MASK … #define CG_ECLK_STATUS__ECLK_STATUS__SHIFT … #define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK … #define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT … #define CG_ACLK_CNTL__ACLK_DIVIDER_MASK … #define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT … #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK … #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT … #define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK … #define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT … #define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK … #define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK … #define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT … #define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK … #define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT … #define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK … #define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT … #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK … #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT … #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK … #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT … #define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK … #define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT … #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK … #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT … #define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK … #define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT … #define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK … #define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT … #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK … #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT … #define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK … #define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT … #define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK … #define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT … #define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK … #define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT … #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK … #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT … #define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK … #define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT … #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK … #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT … #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK … #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT … #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK … #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT … #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK … #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT … #define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK … #define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT … #define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK … #define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT … #define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK … #define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT … #define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK … #define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT … #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK … #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT … #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK … #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT … #define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK … #define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT … #define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK … #define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT … #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK … #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT … #define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK … #define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT … #define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK … #define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT … #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK … #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT … #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK … #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT … #define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK … #define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT … #define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK … #define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT … #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK … #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT … #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK … #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT … #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK … #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT … #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK … #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT … #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK … #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT … #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK … #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT … #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK … #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT … #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK … #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT … #define SPLL_CNTL_MODE__SPLL_TEST_MASK … #define SPLL_CNTL_MODE__SPLL_TEST__SHIFT … #define SPLL_CNTL_MODE__SPLL_FASTEN_MASK … #define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT … #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK … #define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT … #define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK … #define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT … #define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK … #define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT … #define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK … #define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT … #define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK … #define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT … #define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK … #define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT … #define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK … #define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT … #define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK … #define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT … #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK … #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT … #define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK … #define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT … #define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK … #define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT … #define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK … #define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT … #define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK … #define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT … #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK … #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT … #define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK … #define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT … #define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK … #define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT … #define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK … #define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT … #define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK … #define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT … #define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK … #define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT … #define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK … #define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT … #define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK … #define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT … #define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK … #define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT … #define CG_CLKPIN_CNTL_2__CML_CTRL_MASK … #define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT … #define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK … #define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT … #define CG_CLKPIN_CNTL_DC__OSC_EN_MASK … #define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT … #define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK … #define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT … #define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN_MASK … #define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN__SHIFT … #define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK … #define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT … #define THM_CLK_CNTL__CMON_CLK_SEL_MASK … #define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT … #define THM_CLK_CNTL__TMON_CLK_SEL_MASK … #define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT … #define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK … #define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT … #define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK … #define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT … #define MISC_CLK_CTRL__ZCLK_SEL_MASK … #define MISC_CLK_CTRL__ZCLK_SEL__SHIFT … #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK … #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT … #define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK … #define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT … #define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK … #define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT … #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK … #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT … #define GCK_PLL_TEST_CNTL__TST_RESET_MASK … #define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT … #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK … #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT … #define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK … #define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT … #define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK … #define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT … #define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK … #define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT … #define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK … #define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT … #define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK … #define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT … #define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK … #define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT … #define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK … #define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT … #define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK … #define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT … #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK … #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT … #define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK … #define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT … #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK … #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT … #define SMC_IND_INDEX__SMC_IND_ADDR_MASK … #define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT … #define SMC_IND_DATA__SMC_IND_DATA_MASK … #define SMC_IND_DATA__SMC_IND_DATA__SHIFT … #define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK … #define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT … #define SMC_IND_DATA_0__SMC_IND_DATA_MASK … #define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT … #define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK … #define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT … #define SMC_IND_DATA_1__SMC_IND_DATA_MASK … #define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT … #define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK … #define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT … #define SMC_IND_DATA_2__SMC_IND_DATA_MASK … #define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT … #define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK … #define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT … #define SMC_IND_DATA_3__SMC_IND_DATA_MASK … #define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT … #define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK … #define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT … #define SMC_IND_DATA_4__SMC_IND_DATA_MASK … #define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT … #define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK … #define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT … #define SMC_IND_DATA_5__SMC_IND_DATA_MASK … #define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT … #define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK … #define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT … #define SMC_IND_DATA_6__SMC_IND_DATA_MASK … #define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT … #define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK … #define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT … #define SMC_IND_DATA_7__SMC_IND_DATA_MASK … #define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK … #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT … #define SMC_MESSAGE_0__SMC_MSG_MASK … #define SMC_MESSAGE_0__SMC_MSG__SHIFT … #define SMC_RESP_0__SMC_RESP_MASK … #define SMC_RESP_0__SMC_RESP__SHIFT … #define SMC_MESSAGE_1__SMC_MSG_MASK … #define SMC_MESSAGE_1__SMC_MSG__SHIFT … #define SMC_RESP_1__SMC_RESP_MASK … #define SMC_RESP_1__SMC_RESP__SHIFT … #define SMC_MESSAGE_2__SMC_MSG_MASK … #define SMC_MESSAGE_2__SMC_MSG__SHIFT … #define SMC_RESP_2__SMC_RESP_MASK … #define SMC_RESP_2__SMC_RESP__SHIFT … #define SMC_MESSAGE_3__SMC_MSG_MASK … #define SMC_MESSAGE_3__SMC_MSG__SHIFT … #define SMC_RESP_3__SMC_RESP_MASK … #define SMC_RESP_3__SMC_RESP__SHIFT … #define SMC_MESSAGE_4__SMC_MSG_MASK … #define SMC_MESSAGE_4__SMC_MSG__SHIFT … #define SMC_RESP_4__SMC_RESP_MASK … #define SMC_RESP_4__SMC_RESP__SHIFT … #define SMC_MESSAGE_5__SMC_MSG_MASK … #define SMC_MESSAGE_5__SMC_MSG__SHIFT … #define SMC_RESP_5__SMC_RESP_MASK … #define SMC_RESP_5__SMC_RESP__SHIFT … #define SMC_MESSAGE_6__SMC_MSG_MASK … #define SMC_MESSAGE_6__SMC_MSG__SHIFT … #define SMC_RESP_6__SMC_RESP_MASK … #define SMC_RESP_6__SMC_RESP__SHIFT … #define SMC_MESSAGE_7__SMC_MSG_MASK … #define SMC_MESSAGE_7__SMC_MSG__SHIFT … #define SMC_RESP_7__SMC_RESP_MASK … #define SMC_RESP_7__SMC_RESP__SHIFT … #define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT … #define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT … #define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT … #define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT … #define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT … #define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT … #define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT … #define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT … #define SMC_MESSAGE_8__SMC_MSG_MASK … #define SMC_MESSAGE_8__SMC_MSG__SHIFT … #define SMC_RESP_8__SMC_RESP_MASK … #define SMC_RESP_8__SMC_RESP__SHIFT … #define SMC_MESSAGE_9__SMC_MSG_MASK … #define SMC_MESSAGE_9__SMC_MSG__SHIFT … #define SMC_RESP_9__SMC_RESP_MASK … #define SMC_RESP_9__SMC_RESP__SHIFT … #define SMC_MESSAGE_10__SMC_MSG_MASK … #define SMC_MESSAGE_10__SMC_MSG__SHIFT … #define SMC_RESP_10__SMC_RESP_MASK … #define SMC_RESP_10__SMC_RESP__SHIFT … #define SMC_MESSAGE_11__SMC_MSG_MASK … #define SMC_MESSAGE_11__SMC_MSG__SHIFT … #define SMC_RESP_11__SMC_RESP_MASK … #define SMC_RESP_11__SMC_RESP__SHIFT … #define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT … #define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT … #define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT … #define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK … #define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT … #define SMC_SYSCON_RESET_CNTL__rst_reg_MASK … #define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT … #define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK … #define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT … #define SMC_SYSCON_RESET_CNTL__RegReset_MASK … #define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT … #define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK … #define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT … #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK … #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT … #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK … #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT … #define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK … #define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT … #define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK … #define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT … #define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK … #define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT … #define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK … #define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT … #define SMC_PC_C__smc_pc_c_MASK … #define SMC_PC_C__smc_pc_c__SHIFT … #define SMC_SCRATCH9__SCRATCH_VALUE_MASK … #define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT … #define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK … #define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT … #define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK … #define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT … #define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK … #define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT … #define GPIOPAD_MASK__GPIO_MASK_MASK … #define GPIOPAD_MASK__GPIO_MASK__SHIFT … #define GPIOPAD_A__GPIO_A_MASK … #define GPIOPAD_A__GPIO_A__SHIFT … #define GPIOPAD_EN__GPIO_EN_MASK … #define GPIOPAD_EN__GPIO_EN__SHIFT … #define GPIOPAD_Y__GPIO_Y_MASK … #define GPIOPAD_Y__GPIO_Y__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK … #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT … #define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK … #define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT … #define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK … #define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT … #define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK … #define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT … #define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK … #define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK … #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT … #define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK … #define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT … #define GPIOPAD_INT_EN__GPIO_INT_EN_MASK … #define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT … #define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK … #define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT … #define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK … #define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT … #define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK … #define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT … #define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK … #define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT … #define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK … #define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT … #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK … #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT … #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK … #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT … #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK … #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT … #define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK … #define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT … #define GPIOPAD_PU_EN__GPIO_PU_EN_MASK … #define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT … #define GPIOPAD_PD_EN__GPIO_PD_EN_MASK … #define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT … #define CG_FPS_CNT__FPS_CNT_MASK … #define CG_FPS_CNT__FPS_CNT__SHIFT … #define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK … #define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT … #define SMU_IND_DATA_0__SMC_IND_DATA_MASK … #define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT … #define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK … #define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT … #define SMU_IND_DATA_1__SMC_IND_DATA_MASK … #define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT … #define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK … #define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT … #define SMU_IND_DATA_2__SMC_IND_DATA_MASK … #define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT … #define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK … #define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT … #define SMU_IND_DATA_3__SMC_IND_DATA_MASK … #define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT … #define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK … #define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT … #define SMU_IND_DATA_4__SMC_IND_DATA_MASK … #define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT … #define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK … #define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT … #define SMU_IND_DATA_5__SMC_IND_DATA_MASK … #define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT … #define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK … #define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT … #define SMU_IND_DATA_6__SMC_IND_DATA_MASK … #define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT … #define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK … #define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT … #define SMU_IND_DATA_7__SMC_IND_DATA_MASK … #define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT … #define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK … #define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT … #define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK … #define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT … #define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK … #define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT … #define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK … #define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT … #define RCU_UC_EVENTS__drv_rst_mode_MASK … #define RCU_UC_EVENTS__drv_rst_mode__SHIFT … #define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK … #define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT … #define RCU_UC_EVENTS__TP_Tester_MASK … #define RCU_UC_EVENTS__TP_Tester__SHIFT … #define RCU_UC_EVENTS__boot_seq_done_MASK … #define RCU_UC_EVENTS__boot_seq_done__SHIFT … #define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK … #define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT … #define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK … #define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT … #define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK … #define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT … #define RCU_UC_EVENTS__FCH_HALT_MASK … #define RCU_UC_EVENTS__FCH_HALT__SHIFT … #define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK … #define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT … #define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK … #define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT … #define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK … #define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT … #define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK … #define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT … #define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK … #define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT … #define RCU_UC_EVENTS__irq31_sel_MASK … #define RCU_UC_EVENTS__irq31_sel__SHIFT … #define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK … #define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT … #define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK … #define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT … #define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK … #define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT … #define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK … #define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT … #define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK … #define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT … #define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK … #define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT … #define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK … #define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT … #define RCU_MISC_CTRL__SAMU_START_MASK … #define RCU_MISC_CTRL__SAMU_START__SHIFT … #define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK … #define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT … #define CC_RCU_FUSES__GPU_DIS_MASK … #define CC_RCU_FUSES__GPU_DIS__SHIFT … #define CC_RCU_FUSES__DEBUG_DISABLE_MASK … #define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT … #define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK … #define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT … #define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK … #define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT … #define CC_RCU_FUSES__DRV_RST_MODE_MASK … #define CC_RCU_FUSES__DRV_RST_MODE__SHIFT … #define CC_RCU_FUSES__ROM_DIS_MASK … #define CC_RCU_FUSES__ROM_DIS__SHIFT … #define CC_RCU_FUSES__JPC_REP_DISABLE_MASK … #define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT … #define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK … #define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT … #define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK … #define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT … #define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK … #define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT … #define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK … #define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT … #define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK … #define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT … #define CC_RCU_FUSES__XFIRE_DISABLE_MASK … #define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT … #define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK … #define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT … #define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK … #define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT … #define CC_RCU_FUSES__MEM_HARDREP_EN_MASK … #define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT … #define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK … #define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT … #define CC_RCU_FUSES__DSMU_DISABLE_MASK … #define CC_RCU_FUSES__DSMU_DISABLE__SHIFT … #define CC_RCU_FUSES__WRP_FUSE_VALID_MASK … #define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT … #define CC_RCU_FUSES__PHY_FUSE_VALID_MASK … #define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT … #define CC_RCU_FUSES__RCU_SPARE_MASK … #define CC_RCU_FUSES__RCU_SPARE__SHIFT … #define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK … #define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT … #define CC_SMU_MISC_FUSES__MinSClkDid_MASK … #define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT … #define CC_SMU_MISC_FUSES__MISC_SPARE_MASK … #define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT … #define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK … #define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT … #define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK … #define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT … #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK … #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT … #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK … #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT … #define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK … #define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT … #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK … #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT … #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK … #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT … #define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK … #define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT … #define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK … #define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT … #define CC_SMU_MISC_FUSES__GNB_SPARE_MASK … #define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT … #define CC_SCLK_VID_FUSES__SClkVid0_MASK … #define CC_SCLK_VID_FUSES__SClkVid0__SHIFT … #define CC_SCLK_VID_FUSES__SClkVid1_MASK … #define CC_SCLK_VID_FUSES__SClkVid1__SHIFT … #define CC_SCLK_VID_FUSES__SClkVid2_MASK … #define CC_SCLK_VID_FUSES__SClkVid2__SHIFT … #define CC_SCLK_VID_FUSES__SClkVid3_MASK … #define CC_SCLK_VID_FUSES__SClkVid3__SHIFT … #define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK … #define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT … #define CC_GIO_IOC_FUSES__IOC_FUSES_MASK … #define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK … #define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__RME_MASK … #define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK … #define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK … #define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK … #define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK … #define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK … #define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK … #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK … #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK … #define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK … #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK … #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK … #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK … #define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT … #define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK … #define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT … #define CC_TST_ID_STRAPS__DEVICE_ID_MASK … #define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT … #define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK … #define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT … #define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK … #define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT … #define CC_TST_ID_STRAPS__ATI_REV_ID_MASK … #define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT … #define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK … #define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT … #define CC_HARVEST_FUSES__VCE_DISABLE_MASK … #define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT … #define CC_HARVEST_FUSES__UVD_DISABLE_MASK … #define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT … #define CC_HARVEST_FUSES__ACP_EXISTS_MASK … #define CC_HARVEST_FUSES__ACP_EXISTS__SHIFT … #define CC_HARVEST_FUSES__DC_DISABLE_MASK … #define CC_HARVEST_FUSES__DC_DISABLE__SHIFT … #define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK … #define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT … #define SMU_STATUS__SMU_DONE_MASK … #define SMU_STATUS__SMU_DONE__SHIFT … #define SMU_STATUS__SMU_PASS_MASK … #define SMU_STATUS__SMU_PASS__SHIFT … #define SMU_FIRMWARE__SMU_IN_PROG_MASK … #define SMU_FIRMWARE__SMU_IN_PROG__SHIFT … #define SMU_FIRMWARE__SMU_RD_DONE_MASK … #define SMU_FIRMWARE__SMU_RD_DONE__SHIFT … #define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK … #define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT … #define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK … #define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT … #define SMU_FIRMWARE__SMU_counter_MASK … #define SMU_FIRMWARE__SMU_counter__SHIFT … #define SMU_FIRMWARE__SMU_MODE_MASK … #define SMU_FIRMWARE__SMU_MODE__SHIFT … #define SMU_FIRMWARE__SMU_SEL_MASK … #define SMU_FIRMWARE__SMU_SEL__SHIFT … #define SMU_INPUT_DATA__START_ADDR_MASK … #define SMU_INPUT_DATA__START_ADDR__SHIFT … #define SMU_INPUT_DATA__AUTO_START_MASK … #define SMU_INPUT_DATA__AUTO_START__SHIFT … #define SMU_EFUSE_0__EFUSE_DATA_MASK … #define SMU_EFUSE_0__EFUSE_DATA__SHIFT … #define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK … #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT … #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK … #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT … #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK … #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT … #define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK … #define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT … #define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK … #define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT … #define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK … #define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT …
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