// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include "imx95.dtsi"
/ {
model = "NXP i.MX95 19X19 board";
compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
};
bt_sco_codec: audio-codec-bt-sco {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
};
chosen {
stdout-path = &lpuart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
fan0: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>;
cooling-levels = <64 128 192 255>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux_cma: linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x7f000000>;
size = <0 0x3c000000>;
linux,cma-default;
reusable;
};
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SW";
};
reg_audio_pwr: regulator-audio-pwr {
compatible = "regulator-fixed";
regulator-name = "audio-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&i2c4_gpio_expander_21 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_audio_slot: regulator-audio-slot {
compatible = "regulator-fixed";
regulator-name = "audio-wm8962";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&i2c4_gpio_expander_21 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
status = "disabled";
};
reg_m2_pwr: regulator-m2-pwr {
compatible = "regulator-fixed";
regulator-name = "M.2-power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "PCIE_WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <®_m2_pwr>;
gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_slot_pwr: regulator-slot-pwr {
compatible = "regulator-fixed";
regulator-name = "PCIe slot-power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VDD_SD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <12000>;
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai1>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco_codec 1>;
};
};
sound-micfil {
compatible = "fsl,imx-audio-card";
model = "micfil-audio";
pri-dai-link {
link-name = "micfil hifi";
format = "i2s";
cpu {
sound-dai = <&micfil>;
};
};
};
sound-wm8962 {
compatible = "fsl,imx-audio-wm8962";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
audio-routing = "Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC",
"IN1R", "AMIC";
};
};
&flexspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1_reset>;
reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <200000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
};
};
&lpi2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c4>;
status = "okay";
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&scmi_clk IMX95_CLK_SAI3>;
DCVDD-supply = <®_audio_pwr>;
DBVDD-supply = <®_audio_pwr>;
AVDD-supply = <®_audio_pwr>;
CPVDD-supply = <®_audio_pwr>;
MICVDD-supply = <®_audio_pwr>;
PLLVDD-supply = <®_audio_pwr>;
SPKVDD1-supply = <®_audio_pwr>;
SPKVDD2-supply = <®_audio_pwr>;
gpio-cfg = < 0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
i2c4_gpio_expander_21: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio2>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_pcal6408>;
vcc-supply = <®_3p3v>;
};
};
&lpi2c7 {
clock-frequency = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c7>;
status = "okay";
i2c7_pcal6524: i2c7-gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_pcal6524>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio5>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
};
};
&lpuart1 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&micfil {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_PDM>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <49152000>;
status = "okay";
};
&mu7 {
status = "okay";
};
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcie0>;
status = "okay";
};
&pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";
reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_slot_pwr>;
status = "okay";
};
&sai1 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI1>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-3 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
};
&scmi_iomuxc {
pinctrl_flexspi1: flexspi1grp {
fsl,pins = <
IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe
IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe
IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe
IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe
IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe
IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe
IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe
IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe
IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe
IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe
IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe
>;
};
pinctrl_flexspi1_reset: flexspi1-reset-grp {
fsl,pins = <
IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe
>;
};
pinctrl_hp: hpgrp {
fsl,pins = <
IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e
>;
};
pinctrl_i2c4_pcal6408: i2c4pcal6498grp {
fsl,pins = <
IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x31e
>;
};
pinctrl_i2c7_pcal6524: i2c7pcal6524grp {
fsl,pins = <
IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e
>;
};
pinctrl_lpi2c4: lpi2c4grp {
fsl,pins = <
IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e
IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e
>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <
IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e
IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e
IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e
IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e
IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e
IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e
IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e
IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e
IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e
IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e
IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e
IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e
IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e
IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e
IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e
IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e
IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e
IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e
>;
};
pinctrl_tpm6: tpm6grp {
fsl,pins = <
IMX95_PAD_GPIO_IO19__TPM6_CH2 0x51e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};
&thermal_zones {
a55-thermal {
trips {
atrip2: trip2 {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
atrip3: trip3 {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
atrip4: trip4 {
temperature = <75000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&atrip2>;
cooling-device = <&fan0 0 1>;
};
map2 {
trip = <&atrip3>;
cooling-device = <&fan0 1 2>;
};
map3 {
trip = <&atrip4>;
cooling-device = <&fan0 2 3>;
};
};
};
};
&tpm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm6>;
status = "okay";
};
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