// SPDX-License-Identifier: MIT
//
// Copyright 2024 Advanced Micro Devices, Inc.
#ifndef _dcn_4_1_0_OFFSET_HEADER
#define _dcn_4_1_0_OFFSET_HEADER
// addressBlock: dcn_dcec_dccg_dccg_dfs_dispdec
// base address: 0x0
#define regDENTIST_DISPCLK_CNTL 0x0064
#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1
// addressBlock: dcn_dcec_dccg_dccg_dispdec
// base address: 0x0
#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regDP_DTO_DBUF_EN 0x0044
#define regDP_DTO_DBUF_EN_BASE_IDX 1
#define regDSCCLK3_DTO_PARAM 0x0045
#define regDSCCLK3_DTO_PARAM_BASE_IDX 1
#define regDSCCLK4_DTO_PARAM 0x0046
#define regDSCCLK4_DTO_PARAM_BASE_IDX 1
#define regDSCCLK5_DTO_PARAM 0x0047
#define regDSCCLK5_DTO_PARAM_BASE_IDX 1
#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regDCCG_GATE_DISABLE_CNTL4 0x0049
#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1
#define regDPSTREAMCLK_CNTL 0x004a
#define regDPSTREAMCLK_CNTL_BASE_IDX 1
#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b
#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1
#define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050
#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1
#define regSYMCLKG_CLOCK_ENABLE 0x0057
#define regSYMCLKG_CLOCK_ENABLE_BASE_IDX 1
#define regDPREFCLK_CNTL 0x0058
#define regDPREFCLK_CNTL_BASE_IDX 1
#define regAOMCLK0_CNTL 0x0059
#define regAOMCLK0_CNTL_BASE_IDX 1
#define regAOMCLK1_CNTL 0x005a
#define regAOMCLK1_CNTL_BASE_IDX 1
#define regAOMCLK2_CNTL 0x005b
#define regAOMCLK2_CNTL_BASE_IDX 1
#define regDCCG_AUDIO_DTO2_PHASE 0x005c
#define regDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1
#define regDCCG_AUDIO_DTO2_MODULO 0x005d
#define regDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1
#define regDCE_VERSION 0x005e
#define regDCE_VERSION_BASE_IDX 1
#define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
#define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regSYMCLK32_SE_CNTL 0x0065
#define regSYMCLK32_SE_CNTL_BASE_IDX 1
#define regSYMCLK32_LE_CNTL 0x0066
#define regSYMCLK32_LE_CNTL_BASE_IDX 1
#define regDTBCLK_P_CNTL 0x0068
#define regDTBCLK_P_CNTL_BASE_IDX 1
#define regDCCG_GATE_DISABLE_CNTL5 0x0069
#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1
#define regDSCCLK0_DTO_PARAM 0x006c
#define regDSCCLK0_DTO_PARAM_BASE_IDX 1
#define regDSCCLK1_DTO_PARAM 0x006d
#define regDSCCLK1_DTO_PARAM_BASE_IDX 1
#define regDSCCLK2_DTO_PARAM 0x006e
#define regDSCCLK2_DTO_PARAM_BASE_IDX 1
#define regOTG_PIXEL_RATE_DIV 0x006f
#define regOTG_PIXEL_RATE_DIV_BASE_IDX 1
#define regMILLISECOND_TIME_BASE_DIV 0x0070
#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071
#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
#define regDCCG_GATE_DISABLE_CNTL 0x0074
#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075
#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076
#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regDCCG_CAC_STATUS 0x0077
#define regDCCG_CAC_STATUS_BASE_IDX 1
#define regPIXCLK1_RESYNC_CNTL 0x0078
#define regPIXCLK1_RESYNC_CNTL_BASE_IDX 1
#define regPIXCLK2_RESYNC_CNTL 0x0079
#define regPIXCLK2_RESYNC_CNTL_BASE_IDX 1
#define regPIXCLK0_RESYNC_CNTL 0x007a
#define regPIXCLK0_RESYNC_CNTL_BASE_IDX 1
#define regMICROSECOND_TIME_BASE_DIV 0x007b
#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
#define regDCCG_GATE_DISABLE_CNTL2 0x007c
#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d
#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
#define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regDCCG_DISP_CNTL_REG 0x007f
#define regDCCG_DISP_CNTL_REG_BASE_IDX 1
#define regOTG0_PIXEL_RATE_CNTL 0x0080
#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
#define regDP_DTO0_PHASE 0x0081
#define regDP_DTO0_PHASE_BASE_IDX 1
#define regDP_DTO0_MODULO 0x0082
#define regDP_DTO0_MODULO_BASE_IDX 1
#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define regOTG1_PIXEL_RATE_CNTL 0x0084
#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
#define regDP_DTO1_PHASE 0x0085
#define regDP_DTO1_PHASE_BASE_IDX 1
#define regDP_DTO1_MODULO 0x0086
#define regDP_DTO1_MODULO_BASE_IDX 1
#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define regOTG2_PIXEL_RATE_CNTL 0x0088
#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1
#define regDP_DTO2_PHASE 0x0089
#define regDP_DTO2_PHASE_BASE_IDX 1
#define regDP_DTO2_MODULO 0x008a
#define regDP_DTO2_MODULO_BASE_IDX 1
#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b
#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define regOTG3_PIXEL_RATE_CNTL 0x008c
#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1
#define regDP_DTO3_PHASE 0x008d
#define regDP_DTO3_PHASE_BASE_IDX 1
#define regDP_DTO3_MODULO 0x008e
#define regDP_DTO3_MODULO_BASE_IDX 1
#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f
#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define regOTG4_PIXEL_RATE_CNTL 0x0090
#define regOTG4_PIXEL_RATE_CNTL_BASE_IDX 1
#define regDP_DTO4_PHASE 0x0091
#define regDP_DTO4_PHASE_BASE_IDX 1
#define regDP_DTO4_MODULO 0x0092
#define regDP_DTO4_MODULO_BASE_IDX 1
#define regOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093
#define regOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define regOTG5_PIXEL_RATE_CNTL 0x0094
#define regOTG5_PIXEL_RATE_CNTL_BASE_IDX 1
#define regDP_DTO5_PHASE 0x0095
#define regDP_DTO5_PHASE_BASE_IDX 1
#define regDP_DTO5_MODULO 0x0096
#define regDP_DTO5_MODULO_BASE_IDX 1
#define regOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097
#define regOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098
#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regDPPCLK0_DTO_PARAM 0x0099
#define regDPPCLK0_DTO_PARAM_BASE_IDX 1
#define regDPPCLK1_DTO_PARAM 0x009a
#define regDPPCLK1_DTO_PARAM_BASE_IDX 1
#define regDPPCLK2_DTO_PARAM 0x009b
#define regDPPCLK2_DTO_PARAM_BASE_IDX 1
#define regDPPCLK3_DTO_PARAM 0x009c
#define regDPPCLK3_DTO_PARAM_BASE_IDX 1
#define regDPPCLK4_DTO_PARAM 0x009d
#define regDPPCLK4_DTO_PARAM_BASE_IDX 1
#define regDPPCLK5_DTO_PARAM 0x009e
#define regDPPCLK5_DTO_PARAM_BASE_IDX 1
#define regDCCG_CAC_STATUS2 0x009f
#define regDCCG_CAC_STATUS2_BASE_IDX 1
#define regSYMCLKA_CLOCK_ENABLE 0x00a0
#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
#define regSYMCLKB_CLOCK_ENABLE 0x00a1
#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
#define regSYMCLKC_CLOCK_ENABLE 0x00a2
#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
#define regSYMCLKD_CLOCK_ENABLE 0x00a3
#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
#define regSYMCLKE_CLOCK_ENABLE 0x00a4
#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
#define regSYMCLKF_CLOCK_ENABLE 0x00a5
#define regSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
#define regDCCG_SOFT_RESET 0x00a6
#define regDCCG_SOFT_RESET_BASE_IDX 1
#define regDSCCLK_DTO_CTRL 0x00a7
#define regDSCCLK_DTO_CTRL_BASE_IDX 1
#define regDPPCLK_CTRL 0x00a8
#define regDPPCLK_CTRL_BASE_IDX 1
#define regDCCG_GATE_DISABLE_CNTL6 0x00a9
#define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX 1
#define regSYMCLK_PSP_CNTL 0x00aa
#define regSYMCLK_PSP_CNTL_BASE_IDX 1
#define regDCCG_AUDIO_DTO_SOURCE 0x00ab
#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
#define regDCCG_AUDIO_DTO0_PHASE 0x00ac
#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
#define regDCCG_AUDIO_DTO0_MODULE 0x00ad
#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
#define regDCCG_AUDIO_DTO1_PHASE 0x00ae
#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
#define regDCCG_AUDIO_DTO1_MODULE 0x00af
#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
#define regDPPCLK_DTO_CTRL 0x00b6
#define regDPPCLK_DTO_CTRL_BASE_IDX 1
#define regDCCG_VSYNC_CNT_CTRL 0x00b8
#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9
#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
#define regFORCE_SYMCLK_DISABLE 0x00ba
#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1
#define regDCCG_TEST_CLK_SEL 0x00be
#define regDCCG_TEST_CLK_SEL_BASE_IDX 1
#define regHDMICHARCLK0_CLOCK_CNTL 0x004a
#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2
#define regHDMICHARCLK1_CLOCK_CNTL 0x004b
#define regHDMICHARCLK1_CLOCK_CNTL_BASE_IDX 2
#define regHDMICHARCLK2_CLOCK_CNTL 0x004c
#define regHDMICHARCLK2_CLOCK_CNTL_BASE_IDX 2
#define regHDMICHARCLK3_CLOCK_CNTL 0x004d
#define regHDMICHARCLK3_CLOCK_CNTL_BASE_IDX 2
#define regHDMICHARCLK4_CLOCK_CNTL 0x004e
#define regHDMICHARCLK4_CLOCK_CNTL_BASE_IDX 2
#define regHDMICHARCLK5_CLOCK_CNTL 0x004f
#define regHDMICHARCLK5_CLOCK_CNTL_BASE_IDX 2
#define regPHYASYMCLK_CLOCK_CNTL 0x0052
#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2
#define regPHYBSYMCLK_CLOCK_CNTL 0x0053
#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2
#define regPHYCSYMCLK_CLOCK_CNTL 0x0054
#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2
#define regPHYDSYMCLK_CLOCK_CNTL 0x0055
#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2
#define regPHYESYMCLK_CLOCK_CNTL 0x0056
#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2
#define regPHYFSYMCLK_CLOCK_CNTL 0x0057
#define regPHYFSYMCLK_CLOCK_CNTL_BASE_IDX 2
#define regPHYGSYMCLK_CLOCK_CNTL 0x0058
#define regPHYGSYMCLK_CLOCK_CNTL_BASE_IDX 2
#define regHDMISTREAMCLK_CNTL 0x0059
#define regHDMISTREAMCLK_CNTL_BASE_IDX 2
#define regDCCG_GATE_DISABLE_CNTL3 0x005a
#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2
#define regHDMISTREAMCLK0_DTO_PARAM 0x005b
#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2
// base address: 0x0
// base address: 0x30
// addressBlock: dcn_dcec_dmu_fgsec_dispdec
// base address: 0x0
#define regDMCUB_RBBMIF_SEC_CNTL 0x017a
#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2
// addressBlock: dcn_dcec_dmu_rbbmif_dispdec
// base address: 0x0
#define regRBBMIF_TIMEOUT 0x017f
#define regRBBMIF_TIMEOUT_BASE_IDX 2
#define regRBBMIF_STATUS 0x0180
#define regRBBMIF_STATUS_BASE_IDX 2
#define regRBBMIF_STATUS_2 0x0181
#define regRBBMIF_STATUS_2_BASE_IDX 2
#define regRBBMIF_INT_STATUS 0x0182
#define regRBBMIF_INT_STATUS_BASE_IDX 2
#define regRBBMIF_TIMEOUT_DIS 0x0183
#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2
#define regRBBMIF_TIMEOUT_DIS_2 0x0184
#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2
#define regRBBMIF_STATUS_FLAG 0x0185
#define regRBBMIF_STATUS_FLAG_BASE_IDX 2
// addressBlock: dcn_dcec_dmu_ihc_dispdec
// base address: 0x0
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127
#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2
#define regDC_GPU_TIMER_READ 0x0128
#define regDC_GPU_TIMER_READ_BASE_IDX 2
#define regDC_GPU_TIMER_READ_CNTL 0x0129
#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS 0x012a
#define regDISP_INTERRUPT_STATUS_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b
#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c
#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d
#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e
#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f
#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130
#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131
#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132
#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133
#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134
#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135
#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136
#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137
#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138
#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139
#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a
#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b
#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c
#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d
#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e
#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f
#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140
#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2
#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141
#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2
#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142
#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2
#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144
#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145
#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146
#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2
#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147
#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2
#define regDCCG_INTERRUPT_DEST 0x0148
#define regDCCG_INTERRUPT_DEST_BASE_IDX 2
#define regDMU_INTERRUPT_DEST 0x0149
#define regDMU_INTERRUPT_DEST_BASE_IDX 2
#define regDMU_INTERRUPT_DEST2 0x014a
#define regDMU_INTERRUPT_DEST2_BASE_IDX 2
#define regDCPG_INTERRUPT_DEST 0x014b
#define regDCPG_INTERRUPT_DEST_BASE_IDX 2
#define regDCPG_INTERRUPT_DEST2 0x014c
#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2
#define regMMHUBBUB_INTERRUPT_DEST 0x014d
#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2
#define regWB_INTERRUPT_DEST 0x014e
#define regWB_INTERRUPT_DEST_BASE_IDX 2
#define regDCHUB_INTERRUPT_DEST 0x014f
#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2
#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150
#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
#define regDCHUB_INTERRUPT_DEST2 0x0151
#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2
#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152
#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
#define regMPC_INTERRUPT_DEST 0x0153
#define regMPC_INTERRUPT_DEST_BASE_IDX 2
#define regOPP_INTERRUPT_DEST 0x0154
#define regOPP_INTERRUPT_DEST_BASE_IDX 2
#define regOPTC_INTERRUPT_DEST 0x0155
#define regOPTC_INTERRUPT_DEST_BASE_IDX 2
#define regOTG0_INTERRUPT_DEST 0x0156
#define regOTG0_INTERRUPT_DEST_BASE_IDX 2
#define regOTG1_INTERRUPT_DEST 0x0157
#define regOTG1_INTERRUPT_DEST_BASE_IDX 2
#define regOTG2_INTERRUPT_DEST 0x0158
#define regOTG2_INTERRUPT_DEST_BASE_IDX 2
#define regOTG3_INTERRUPT_DEST 0x0159
#define regOTG3_INTERRUPT_DEST_BASE_IDX 2
#define regOTG4_INTERRUPT_DEST 0x015a
#define regOTG4_INTERRUPT_DEST_BASE_IDX 2
#define regOTG5_INTERRUPT_DEST 0x015b
#define regOTG5_INTERRUPT_DEST_BASE_IDX 2
#define regDIG_INTERRUPT_DEST 0x015c
#define regDIG_INTERRUPT_DEST_BASE_IDX 2
#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d
#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2
#define regHDCP_INTERRUPT_DEST 0x015e
#define regHDCP_INTERRUPT_DEST_BASE_IDX 2
#define regDIO_INTERRUPT_DEST 0x015f
#define regDIO_INTERRUPT_DEST_BASE_IDX 2
#define regDCIO_INTERRUPT_DEST 0x0160
#define regDCIO_INTERRUPT_DEST_BASE_IDX 2
#define regHPD_INTERRUPT_DEST 0x0161
#define regHPD_INTERRUPT_DEST_BASE_IDX 2
#define regAZ_INTERRUPT_DEST 0x0162
#define regAZ_INTERRUPT_DEST_BASE_IDX 2
#define regAUX_INTERRUPT_DEST 0x0163
#define regAUX_INTERRUPT_DEST_BASE_IDX 2
#define regDSC_INTERRUPT_DEST 0x0164
#define regDSC_INTERRUPT_DEST_BASE_IDX 2
#define regHPO_INTERRUPT_DEST 0x0165
#define regHPO_INTERRUPT_DEST_BASE_IDX 2
// addressBlock: dcn_dcec_dmu_dmu_misc_dispdec
// base address: 0x0
#define regCC_DC_PIPE_DIS 0x00ca
#define regCC_DC_PIPE_DIS_BASE_IDX 2
#define regDMU_CLK_CNTL 0x00cb
#define regDMU_CLK_CNTL_BASE_IDX 2
#define regDMCUB_SMU_INTERRUPT_CNTL 0x00cd
#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX 2
#define regSMU_INTERRUPT_CONTROL 0x00ce
#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2
#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6
#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2
#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG 0x00d8
#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2
#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG 0x00d9
#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2
// addressBlock: dcn_dcec_dmu_dc_pg_dispdec
// base address: 0x0
#define regDOMAIN0_PG_CONFIG 0x0080
#define regDOMAIN0_PG_CONFIG_BASE_IDX 2
#define regDOMAIN0_PG_STATUS 0x0081
#define regDOMAIN0_PG_STATUS_BASE_IDX 2
#define regDOMAIN1_PG_CONFIG 0x0082
#define regDOMAIN1_PG_CONFIG_BASE_IDX 2
#define regDOMAIN1_PG_STATUS 0x0083
#define regDOMAIN1_PG_STATUS_BASE_IDX 2
#define regDOMAIN2_PG_CONFIG 0x0084
#define regDOMAIN2_PG_CONFIG_BASE_IDX 2
#define regDOMAIN2_PG_STATUS 0x0085
#define regDOMAIN2_PG_STATUS_BASE_IDX 2
#define regDOMAIN3_PG_CONFIG 0x0086
#define regDOMAIN3_PG_CONFIG_BASE_IDX 2
#define regDOMAIN3_PG_STATUS 0x0087
#define regDOMAIN3_PG_STATUS_BASE_IDX 2
#define regDOMAIN16_PG_CONFIG 0x0089
#define regDOMAIN16_PG_CONFIG_BASE_IDX 2
#define regDOMAIN16_PG_STATUS 0x008a
#define regDOMAIN16_PG_STATUS_BASE_IDX 2
#define regDOMAIN17_PG_CONFIG 0x008b
#define regDOMAIN17_PG_CONFIG_BASE_IDX 2
#define regDOMAIN17_PG_STATUS 0x008c
#define regDOMAIN17_PG_STATUS_BASE_IDX 2
#define regDOMAIN18_PG_CONFIG 0x008d
#define regDOMAIN18_PG_CONFIG_BASE_IDX 2
#define regDOMAIN18_PG_STATUS 0x008e
#define regDOMAIN18_PG_STATUS_BASE_IDX 2
#define regDOMAIN19_PG_CONFIG 0x008f
#define regDOMAIN19_PG_CONFIG_BASE_IDX 2
#define regDOMAIN19_PG_STATUS 0x0090
#define regDOMAIN19_PG_STATUS_BASE_IDX 2
#define regDOMAIN22_PG_CONFIG 0x0092
#define regDOMAIN22_PG_CONFIG_BASE_IDX 2
#define regDOMAIN22_PG_STATUS 0x0093
#define regDOMAIN22_PG_STATUS_BASE_IDX 2
#define regDOMAIN23_PG_CONFIG 0x0094
#define regDOMAIN23_PG_CONFIG_BASE_IDX 2
#define regDOMAIN23_PG_STATUS 0x0095
#define regDOMAIN23_PG_STATUS_BASE_IDX 2
#define regDOMAIN24_PG_CONFIG 0x0096
#define regDOMAIN24_PG_CONFIG_BASE_IDX 2
#define regDOMAIN24_PG_STATUS 0x0097
#define regDOMAIN24_PG_STATUS_BASE_IDX 2
#define regDOMAIN25_PG_CONFIG 0x0098
#define regDOMAIN25_PG_CONFIG_BASE_IDX 2
#define regDOMAIN25_PG_STATUS 0x0099
#define regDOMAIN25_PG_STATUS_BASE_IDX 2
#define regDCPG_INTERRUPT_STATUS 0x009a
#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2
#define regDCPG_INTERRUPT_STATUS_2 0x009b
#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2
#define regDCPG_INTERRUPT_STATUS_3 0x009c
#define regDCPG_INTERRUPT_STATUS_3_BASE_IDX 2
#define regDCPG_INTERRUPT_CONTROL_1 0x009d
#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2
#define regDCPG_INTERRUPT_CONTROL_2 0x009e
#define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2
#define regDCPG_INTERRUPT_CONTROL_3 0x009f
#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2
#define regDC_IP_REQUEST_CNTL 0x00a0
#define regDC_IP_REQUEST_CNTL_BASE_IDX 2
#define regDC_PGCNTL_STATUS_REG 0x00a1
#define regDC_PGCNTL_STATUS_REG_BASE_IDX 2
#define regLONO_MEM_PWR_REQ_CNTL 0x00a4
#define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX 2
// addressBlock: dcn_dcec_dmu_dmcub_dispdec
// base address: 0x0
#define regDMCUB_REGION0_OFFSET 0x018e
#define regDMCUB_REGION0_OFFSET_BASE_IDX 2
#define regDMCUB_REGION0_OFFSET_HIGH 0x018f
#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION1_OFFSET 0x0190
#define regDMCUB_REGION1_OFFSET_BASE_IDX 2
#define regDMCUB_REGION1_OFFSET_HIGH 0x0191
#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION2_OFFSET 0x0192
#define regDMCUB_REGION2_OFFSET_BASE_IDX 2
#define regDMCUB_REGION2_OFFSET_HIGH 0x0193
#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION4_OFFSET 0x0196
#define regDMCUB_REGION4_OFFSET_BASE_IDX 2
#define regDMCUB_REGION4_OFFSET_HIGH 0x0197
#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION5_OFFSET 0x0198
#define regDMCUB_REGION5_OFFSET_BASE_IDX 2
#define regDMCUB_REGION5_OFFSET_HIGH 0x0199
#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION6_OFFSET 0x019a
#define regDMCUB_REGION6_OFFSET_BASE_IDX 2
#define regDMCUB_REGION6_OFFSET_HIGH 0x019b
#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION7_OFFSET 0x019c
#define regDMCUB_REGION7_OFFSET_BASE_IDX 2
#define regDMCUB_REGION7_OFFSET_HIGH 0x019d
#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION0_TOP_ADDRESS 0x019e
#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION1_TOP_ADDRESS 0x019f
#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0
#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1
#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2
#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3
#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4
#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5
#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6
#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7
#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8
#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9
#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa
#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab
#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac
#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad
#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae
#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af
#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0
#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1
#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2
#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3
#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4
#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2
#define regDMCUB_REGION3_CW0_OFFSET 0x01b5
#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2
#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6
#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION3_CW1_OFFSET 0x01b7
#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2
#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8
#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION3_CW2_OFFSET 0x01b9
#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2
#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba
#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION3_CW3_OFFSET 0x01bb
#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2
#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc
#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION3_CW4_OFFSET 0x01bd
#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2
#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be
#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION3_CW5_OFFSET 0x01bf
#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2
#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0
#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION3_CW6_OFFSET 0x01c1
#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2
#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2
#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_REGION3_CW7_OFFSET 0x01c3
#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2
#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4
#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2
#define regDMCUB_INTERRUPT_ENABLE 0x01c5
#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2
#define regDMCUB_INTERRUPT_ACK 0x01c6
#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2
#define regDMCUB_INTERRUPT_STATUS 0x01c7
#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2
#define regDMCUB_INTERRUPT_TYPE 0x01c8
#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2
#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9
#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2
#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca
#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2
#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb
#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2
#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc
#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2
#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd
#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2
#define regDMCUB_SEC_CNTL 0x01ce
#define regDMCUB_SEC_CNTL_BASE_IDX 2
#define regDMCUB_MEM_CNTL 0x01cf
#define regDMCUB_MEM_CNTL_BASE_IDX 2
#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0
#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_INBOX0_SIZE 0x01d1
#define regDMCUB_INBOX0_SIZE_BASE_IDX 2
#define regDMCUB_INBOX0_WPTR 0x01d2
#define regDMCUB_INBOX0_WPTR_BASE_IDX 2
#define regDMCUB_INBOX0_RPTR 0x01d3
#define regDMCUB_INBOX0_RPTR_BASE_IDX 2
#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4
#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_INBOX1_SIZE 0x01d5
#define regDMCUB_INBOX1_SIZE_BASE_IDX 2
#define regDMCUB_INBOX1_WPTR 0x01d6
#define regDMCUB_INBOX1_WPTR_BASE_IDX 2
#define regDMCUB_INBOX1_RPTR 0x01d7
#define regDMCUB_INBOX1_RPTR_BASE_IDX 2
#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8
#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_OUTBOX0_SIZE 0x01d9
#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2
#define regDMCUB_OUTBOX0_WPTR 0x01da
#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2
#define regDMCUB_OUTBOX0_RPTR 0x01db
#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2
#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc
#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2
#define regDMCUB_OUTBOX1_SIZE 0x01dd
#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2
#define regDMCUB_OUTBOX1_WPTR 0x01de
#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2
#define regDMCUB_OUTBOX1_RPTR 0x01df
#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2
#define regDMCUB_TIMER_TRIGGER0 0x01e0
#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2
#define regDMCUB_TIMER_TRIGGER1 0x01e1
#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2
#define regDMCUB_TIMER_WINDOW 0x01e2
#define regDMCUB_TIMER_WINDOW_BASE_IDX 2
#define regDMCUB_SCRATCH0 0x01e3
#define regDMCUB_SCRATCH0_BASE_IDX 2
#define regDMCUB_SCRATCH1 0x01e4
#define regDMCUB_SCRATCH1_BASE_IDX 2
#define regDMCUB_SCRATCH2 0x01e5
#define regDMCUB_SCRATCH2_BASE_IDX 2
#define regDMCUB_SCRATCH3 0x01e6
#define regDMCUB_SCRATCH3_BASE_IDX 2
#define regDMCUB_SCRATCH4 0x01e7
#define regDMCUB_SCRATCH4_BASE_IDX 2
#define regDMCUB_SCRATCH5 0x01e8
#define regDMCUB_SCRATCH5_BASE_IDX 2
#define regDMCUB_SCRATCH6 0x01e9
#define regDMCUB_SCRATCH6_BASE_IDX 2
#define regDMCUB_SCRATCH7 0x01ea
#define regDMCUB_SCRATCH7_BASE_IDX 2
#define regDMCUB_SCRATCH8 0x01eb
#define regDMCUB_SCRATCH8_BASE_IDX 2
#define regDMCUB_SCRATCH9 0x01ec
#define regDMCUB_SCRATCH9_BASE_IDX 2
#define regDMCUB_SCRATCH10 0x01ed
#define regDMCUB_SCRATCH10_BASE_IDX 2
#define regDMCUB_SCRATCH11 0x01ee
#define regDMCUB_SCRATCH11_BASE_IDX 2
#define regDMCUB_SCRATCH12 0x01ef
#define regDMCUB_SCRATCH12_BASE_IDX 2
#define regDMCUB_SCRATCH13 0x01f0
#define regDMCUB_SCRATCH13_BASE_IDX 2
#define regDMCUB_SCRATCH14 0x01f1
#define regDMCUB_SCRATCH14_BASE_IDX 2
#define regDMCUB_SCRATCH15 0x01f2
#define regDMCUB_SCRATCH15_BASE_IDX 2
#define regDMCUB_SCRATCH16 0x01f3
#define regDMCUB_SCRATCH16_BASE_IDX 2
#define regDMCUB_SCRATCH17 0x01f4
#define regDMCUB_SCRATCH17_BASE_IDX 2
#define regDMCUB_SCRATCH18 0x01f5
#define regDMCUB_SCRATCH18_BASE_IDX 2
#define regDMCUB_CNTL 0x01f6
#define regDMCUB_CNTL_BASE_IDX 2
#define regDMCUB_GPINT_DATAIN0 0x01f7
#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2
#define regDMCUB_GPINT_DATAIN1 0x01f8
#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2
#define regDMCUB_GPINT_DATAOUT 0x01f9
#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2
#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa
#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2
#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb
#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2
#define regDMCUB_MEM_PWR_CNTL 0x01fc
#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2
#define regDMCUB_TIMER_CURRENT 0x01fd
#define regDMCUB_TIMER_CURRENT_BASE_IDX 2
#define regDMCUB_PROC_ID 0x01ff
#define regDMCUB_PROC_ID_BASE_IDX 2
#define regDMCUB_CNTL2 0x0200
#define regDMCUB_CNTL2_BASE_IDX 2
#define regDMCUB_GPINT_DATAIN2 0x0215
#define regDMCUB_GPINT_DATAIN2_BASE_IDX 2
#define regDMCUB_GPINT_DATAIN3 0x0216
#define regDMCUB_GPINT_DATAIN3_BASE_IDX 2
#define regDMCUB_GPINT_DATAIN4 0x0217
#define regDMCUB_GPINT_DATAIN4_BASE_IDX 2
#define regDMCUB_GPINT_DATAIN5 0x0218
#define regDMCUB_GPINT_DATAIN5_BASE_IDX 2
#define regDMCUB_GPINT_DATAIN6 0x0219
#define regDMCUB_GPINT_DATAIN6_BASE_IDX 2
#define regDMCUB_REGION3_TMR_AXI_SPACE 0x021a
#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX 2
#define regDMCUB_SCRATCH19 0x021b
#define regDMCUB_SCRATCH19_BASE_IDX 2
#define regDMCUB_SCRATCH20 0x021c
#define regDMCUB_SCRATCH20_BASE_IDX 2
#define regDMCUB_SCRATCH21 0x021d
#define regDMCUB_SCRATCH21_BASE_IDX 2
#define regDMCUB_SCRATCH22 0x021e
#define regDMCUB_SCRATCH22_BASE_IDX 2
#define regDMCUB_SCRATCH23 0x021f
#define regDMCUB_SCRATCH23_BASE_IDX 2
#define regHOST_INTERRUPT_CSR 0x0222
#define regHOST_INTERRUPT_CSR_BASE_IDX 2
#define regDMCUB_REG_INBOX0_RDY 0x0223
#define regDMCUB_REG_INBOX0_RDY_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG0 0x0224
#define regDMCUB_REG_INBOX0_MSG0_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG1 0x0225
#define regDMCUB_REG_INBOX0_MSG1_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG2 0x0226
#define regDMCUB_REG_INBOX0_MSG2_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG3 0x0227
#define regDMCUB_REG_INBOX0_MSG3_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG4 0x0228
#define regDMCUB_REG_INBOX0_MSG4_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG5 0x0229
#define regDMCUB_REG_INBOX0_MSG5_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG6 0x022a
#define regDMCUB_REG_INBOX0_MSG6_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG7 0x022b
#define regDMCUB_REG_INBOX0_MSG7_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG8 0x022c
#define regDMCUB_REG_INBOX0_MSG8_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG9 0x022d
#define regDMCUB_REG_INBOX0_MSG9_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG10 0x022e
#define regDMCUB_REG_INBOX0_MSG10_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG11 0x022f
#define regDMCUB_REG_INBOX0_MSG11_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG12 0x0230
#define regDMCUB_REG_INBOX0_MSG12_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG13 0x0231
#define regDMCUB_REG_INBOX0_MSG13_BASE_IDX 2
#define regDMCUB_REG_INBOX0_MSG14 0x0232
#define regDMCUB_REG_INBOX0_MSG14_BASE_IDX 2
#define regDMCUB_REG_INBOX0_RSP 0x0233
#define regDMCUB_REG_INBOX0_RSP_BASE_IDX 2
#define regDMCUB_REG_OUTBOX0_RDY 0x0234
#define regDMCUB_REG_OUTBOX0_RDY_BASE_IDX 2
#define regDMCUB_REG_OUTBOX0_MSG0 0x0235
#define regDMCUB_REG_OUTBOX0_MSG0_BASE_IDX 2
#define regDMCUB_REG_OUTBOX0_RSP 0x0236
#define regDMCUB_REG_OUTBOX0_RSP_BASE_IDX 2
#define regDMCUB_REG_INBOX1_RDY 0x0237
#define regDMCUB_REG_INBOX1_RDY_BASE_IDX 2
#define regDMCUB_REG_INBOX1_MSG0 0x0238
#define regDMCUB_REG_INBOX1_MSG0_BASE_IDX 2
#define regDMCUB_REG_INBOX1_MSG1 0x0239
#define regDMCUB_REG_INBOX1_MSG1_BASE_IDX 2
#define regDMCUB_REG_INBOX1_RSP 0x023a
#define regDMCUB_REG_INBOX1_RSP_BASE_IDX 2
#define regDMCUB_REG_INBOX2_RDY 0x023b
#define regDMCUB_REG_INBOX2_RDY_BASE_IDX 2
#define regDMCUB_REG_INBOX2_MSG0 0x023c
#define regDMCUB_REG_INBOX2_MSG0_BASE_IDX 2
#define regDMCUB_REG_INBOX2_MSG1 0x023d
#define regDMCUB_REG_INBOX2_MSG1_BASE_IDX 2
#define regDMCUB_REG_INBOX2_RSP 0x023e
#define regDMCUB_REG_INBOX2_RSP_BASE_IDX 2
#define regDMCUB_REG_INBOX3_RDY 0x023f
#define regDMCUB_REG_INBOX3_RDY_BASE_IDX 2
#define regDMCUB_REG_INBOX3_MSG0 0x0240
#define regDMCUB_REG_INBOX3_MSG0_BASE_IDX 2
#define regDMCUB_REG_INBOX3_MSG1 0x0241
#define regDMCUB_REG_INBOX3_MSG1_BASE_IDX 2
#define regDMCUB_REG_INBOX3_RSP 0x0242
#define regDMCUB_REG_INBOX3_RSP_BASE_IDX 2
#define regDMCUB_REG_INBOX4_RDY 0x0243
#define regDMCUB_REG_INBOX4_RDY_BASE_IDX 2
#define regDMCUB_REG_INBOX4_MSG0 0x0244
#define regDMCUB_REG_INBOX4_MSG0_BASE_IDX 2
#define regDMCUB_REG_INBOX4_MSG1 0x0245
#define regDMCUB_REG_INBOX4_MSG1_BASE_IDX 2
#define regDMCUB_REG_INBOX4_RSP 0x0246
#define regDMCUB_REG_INBOX4_RSP_BASE_IDX 2
// addressBlock: dcn_dcec_wb0_dispdec_dwb_top_dispdec
// base address: 0x0
#define regDWB_ENABLE_CLK_CTRL 0x3228
#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2
#define regDWB_MEM_PWR_CTRL 0x3229
#define regDWB_MEM_PWR_CTRL_BASE_IDX 2
#define regFC_MODE_CTRL 0x322a
#define regFC_MODE_CTRL_BASE_IDX 2
#define regFC_FLOW_CTRL 0x322b
#define regFC_FLOW_CTRL_BASE_IDX 2
#define regFC_WINDOW_START 0x322c
#define regFC_WINDOW_START_BASE_IDX 2
#define regFC_WINDOW_SIZE 0x322d
#define regFC_WINDOW_SIZE_BASE_IDX 2
#define regFC_SOURCE_SIZE 0x322e
#define regFC_SOURCE_SIZE_BASE_IDX 2
#define regDWB_UPDATE_CTRL 0x322f
#define regDWB_UPDATE_CTRL_BASE_IDX 2
#define regDWB_CRC_CTRL 0x3230
#define regDWB_CRC_CTRL_BASE_IDX 2
#define regDWB_CRC_MASK_R_G 0x3231
#define regDWB_CRC_MASK_R_G_BASE_IDX 2
#define regDWB_CRC_MASK_B_A 0x3232
#define regDWB_CRC_MASK_B_A_BASE_IDX 2
#define regDWB_CRC_VAL_R_G 0x3233
#define regDWB_CRC_VAL_R_G_BASE_IDX 2
#define regDWB_CRC_VAL_B_A 0x3234
#define regDWB_CRC_VAL_B_A_BASE_IDX 2
#define regDWB_OUT_CTRL 0x3235
#define regDWB_OUT_CTRL_BASE_IDX 2
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2
#define regDWB_HOST_READ_CONTROL 0x3238
#define regDWB_HOST_READ_CONTROL_BASE_IDX 2
#define regDWB_OVERFLOW_STATUS 0x3239
#define regDWB_OVERFLOW_STATUS_BASE_IDX 2
#define regDWB_OVERFLOW_COUNTER 0x323a
#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2
#define regDWB_SOFT_RESET 0x323b
#define regDWB_SOFT_RESET_BASE_IDX 2
#define regDWB_DEBUG_CTRL 0x323c
#define regDWB_DEBUG_CTRL_BASE_IDX 2
#define regDWB_DEBUG 0x323d
#define regDWB_DEBUG_BASE_IDX 2
// addressBlock: dcn_dcec_wb0_dispdec_dwbcp_dispdec
// base address: 0x0
#define regDWB_HDR_MULT_COEF 0x3294
#define regDWB_HDR_MULT_COEF_BASE_IDX 2
#define regDWB_GAMUT_REMAP_MODE 0x3295
#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2
#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296
#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2
#define regDWB_GAMUT_REMAPA_C11_C12 0x3297
#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2
#define regDWB_GAMUT_REMAPA_C13_C14 0x3298
#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2
#define regDWB_GAMUT_REMAPA_C21_C22 0x3299
#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2
#define regDWB_GAMUT_REMAPA_C23_C24 0x329a
#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2
#define regDWB_GAMUT_REMAPA_C31_C32 0x329b
#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2
#define regDWB_GAMUT_REMAPA_C33_C34 0x329c
#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2
#define regDWB_GAMUT_REMAPB_C11_C12 0x329d
#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2
#define regDWB_GAMUT_REMAPB_C13_C14 0x329e
#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2
#define regDWB_GAMUT_REMAPB_C21_C22 0x329f
#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2
#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0
#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2
#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1
#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2
#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2
#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2
#define regDWB_OGAM_CONTROL 0x32a3
#define regDWB_OGAM_CONTROL_BASE_IDX 2
#define regDWB_OGAM_LUT_INDEX 0x32a4
#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2
#define regDWB_OGAM_LUT_DATA 0x32a5
#define regDWB_OGAM_LUT_DATA_BASE_IDX 2
#define regDWB_OGAM_LUT_CONTROL 0x32a6
#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2
#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7
#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8
#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9
#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa
#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac
#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae
#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0
#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1
#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2
#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3
#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4
#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5
#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6
#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2
#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7
#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2
#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8
#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9
#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba
#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb
#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc
#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd
#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_10_11 0x32be
#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf
#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0
#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1
#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2
#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3
#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4
#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5
#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6
#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7
#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8
#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2
#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9
#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2
#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca
#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb
#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc
#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd
#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf
#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1
#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3
#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4
#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5
#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6
#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7
#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8
#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9
#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2
#define regDWB_OGAM_RAMB_OFFSET_G 0x32da
#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2
#define regDWB_OGAM_RAMB_OFFSET_R 0x32db
#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc
#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd
#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_4_5 0x32de
#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_6_7 0x32df
#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0
#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1
#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2
#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3
#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4
#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5
#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6
#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7
#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8
#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9
#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea
#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb
#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2
#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec
#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2
// addressBlock: dcn_dcec_mmhubbub_mcif_wb0_dispdec
// base address: 0x0
#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272
#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define regMCIF_WB_BUFMGR_STATUS 0x0274
#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define regMCIF_WB_BUF_PITCH 0x0275
#define regMCIF_WB_BUF_PITCH_BASE_IDX 2
#define regMCIF_WB_BUF_1_STATUS 0x0276
#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define regMCIF_WB_BUF_1_STATUS2 0x0277
#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define regMCIF_WB_BUF_2_STATUS 0x0278
#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define regMCIF_WB_BUF_2_STATUS2 0x0279
#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define regMCIF_WB_BUF_3_STATUS 0x027a
#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define regMCIF_WB_BUF_3_STATUS2 0x027b
#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define regMCIF_WB_BUF_4_STATUS 0x027c
#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define regMCIF_WB_BUF_4_STATUS2 0x027d
#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define regMCIF_WB_ARBITRATION_CONTROL 0x027e
#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define regMCIF_WB_SCLK_CHANGE 0x027f
#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280
#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
#define regMCIF_WB_TEST_DEBUG_DATA 0x0281
#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
#define regMCIF_WB_BUF_1_ADDR_Y 0x0282
#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define regMCIF_WB_BUF_1_ADDR_C 0x0284
#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define regMCIF_WB_BUF_2_ADDR_Y 0x0286
#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define regMCIF_WB_BUF_2_ADDR_C 0x0288
#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define regMCIF_WB_BUF_3_ADDR_Y 0x028a
#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define regMCIF_WB_BUF_3_ADDR_C 0x028c
#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define regMCIF_WB_BUF_4_ADDR_Y 0x028e
#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define regMCIF_WB_BUF_4_ADDR_C 0x0290
#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292
#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293
#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294
#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296
#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define regMULTI_LEVEL_QOS_CTRL 0x0297
#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define regMCIF_WB_SECURITY_LEVEL 0x0298
#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX 2
#define regMCIF_WB_BUF_LUMA_SIZE 0x0299
#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a
#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b
#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c
#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d
#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e
#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f
#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0
#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1
#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2
#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3
#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4
#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5
#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6
#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI 0x02a7
#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX 2
#define regMCIF_WB_VMID_CONTROL 0x02a8
#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2
#define regMCIF_WB_MIN_TTO 0x02a9
#define regMCIF_WB_MIN_TTO_BASE_IDX 2
// addressBlock: dcn_dcec_mmhubbub_mmhubbub_dispdec
// base address: 0x0
#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa
#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define regMCIF_WB_WATERMARK 0x02ab
#define regMCIF_WB_WATERMARK_BASE_IDX 2
#define regMMHUBBUB_WARMUP_CONFIG 0x02ac
#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2
#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad
#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2
#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae
#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2
#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af
#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2
#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0
#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2
#define regMMHUBBUB_MIN_TTO 0x02b1
#define regMMHUBBUB_MIN_TTO_BASE_IDX 2
#define regMMHUBBUB_CTRL 0x0333
#define regMMHUBBUB_CTRL_BASE_IDX 2
#define regWBIF_SMU_WM_CONTROL 0x0334
#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2
#define regWBIF0_MISC_CTRL 0x0335
#define regWBIF0_MISC_CTRL_BASE_IDX 2
#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336
#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337
#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define regMMHUBBUB_MEM_PWR_STATUS 0x033e
#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
#define regMMHUBBUB_MEM_PWR_CNTL 0x033f
#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2
#define regMMHUBBUB_CLOCK_CNTL 0x0340
#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2
#define regMMHUBBUB_SOFT_RESET 0x0341
#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2
#define regDMU_IF_ERR_STATUS 0x0345
#define regDMU_IF_ERR_STATUS_BASE_IDX 2
#define regMMHUBBUB_CLIENT_UNIT_ID 0x0346
#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2
#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0348
#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0controller_dispdec
// base address: 0x0
#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
#define regAZALIA_AUDIO_DTO 0x03c3
#define regAZALIA_AUDIO_DTO_BASE_IDX 2
#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4
#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
#define regAZALIA_SOCCLK_CONTROL 0x03c5
#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2
#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
#define regAZALIA_DATA_DMA_CONTROL 0x03c7
#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
#define regAZALIA_BDL_DMA_CONTROL 0x03c8
#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9
#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
#define regAZALIA_CORB_DMA_CONTROL 0x03ca
#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3
#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
#define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9
#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da
#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db
#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc
#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
#define regAZALIA_INPUT_CRC0_RESULT 0x03dd
#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de
#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df
#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0
#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1
#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
#define regAZALIA_INPUT_CRC1_RESULT 0x03e2
#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
#define regAZALIA_CRC0_CONTROL0 0x03e3
#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2
#define regAZALIA_CRC0_CONTROL1 0x03e4
#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2
#define regAZALIA_CRC0_CONTROL2 0x03e5
#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2
#define regAZALIA_CRC0_CONTROL3 0x03e6
#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2
#define regAZALIA_CRC0_RESULT 0x03e7
#define regAZALIA_CRC0_RESULT_BASE_IDX 2
#define regAZALIA_CRC1_CONTROL0 0x03e8
#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2
#define regAZALIA_CRC1_CONTROL1 0x03e9
#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2
#define regAZALIA_CRC1_CONTROL2 0x03ea
#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2
#define regAZALIA_CRC1_CONTROL3 0x03eb
#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2
#define regAZALIA_CRC1_RESULT 0x03ec
#define regAZALIA_CRC1_RESULT_BASE_IDX 2
#define regAZALIA_SOFT_RESET 0x03ed
#define regAZALIA_SOFT_RESET_BASE_IDX 2
#define regAZALIA_MEM_PWR_CTRL 0x03ee
#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2
#define regAZALIA_MEM_PWR_STATUS 0x03ef
#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0root_dispdec
// base address: 0x0
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412
#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413
#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
// addressBlock: dcn_dcec_hda_az_misc_dispdec
// base address: 0x0
#define regAZ_CLOCK_CNTL 0x0372
#define regAZ_CLOCK_CNTL_BASE_IDX 2
#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL 0x0373
#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 2
#define regAZ_STRAPS 0x0374
#define regAZ_STRAPS_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream0_dispdec
// base address: 0x0
#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e
#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f
#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream1_dispdec
// base address: 0x8
#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360
#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361
#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream2_dispdec
// base address: 0x10
#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362
#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363
#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream3_dispdec
// base address: 0x18
#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364
#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365
#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream4_dispdec
// base address: 0x20
#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366
#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367
#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream5_dispdec
// base address: 0x28
#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368
#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369
#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream6_dispdec
// base address: 0x30
#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a
#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b
#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream7_dispdec
// base address: 0x38
#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c
#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d
#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream8_dispdec
// base address: 0x320
#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426
#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427
#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream9_dispdec
// base address: 0x328
#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428
#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429
#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream10_dispdec
// base address: 0x330
#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a
#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b
#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream11_dispdec
// base address: 0x338
#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c
#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d
#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream12_dispdec
// base address: 0x340
#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e
#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f
#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream13_dispdec
// base address: 0x348
#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430
#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431
#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream14_dispdec
// base address: 0x350
#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432
#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433
#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0stream15_dispdec
// base address: 0x358
#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434
#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435
#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0endpoint0_dispdec
// base address: 0x0
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0endpoint1_dispdec
// base address: 0x18
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0endpoint2_dispdec
// base address: 0x30
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0endpoint3_dispdec
// base address: 0x48
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0endpoint4_dispdec
// base address: 0x60
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0endpoint5_dispdec
// base address: 0x78
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0endpoint6_dispdec
// base address: 0x90
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0endpoint7_dispdec
// base address: 0xa8
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0inputendpoint0_dispdec
// base address: 0x0
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0inputendpoint1_dispdec
// base address: 0x10
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0inputendpoint2_dispdec
// base address: 0x20
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0inputendpoint3_dispdec
// base address: 0x30
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0inputendpoint4_dispdec
// base address: 0x40
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0inputendpoint5_dispdec
// base address: 0x50
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0inputendpoint6_dispdec
// base address: 0x60
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_hda_azf0inputendpoint7_dispdec
// base address: 0x70
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dchubbubl_hubbub_dispdec
// base address: 0x0
#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9
#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
#define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa
#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
#define regDCHUBBUB_ARB_QOS_FORCE 0x04fb
#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc
#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL 0x04fd
#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX 2
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fe
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A 0x04ff
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX 2
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x0500
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2
#define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_A 0x0501
#define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_A_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x0502
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0503
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A 0x0504
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A 0x0505
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A 0x0506
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A 0x0507
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A 0x0508
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A 0x0509
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A_BASE_IDX 2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A 0x050a
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A 0x050b
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A_BASE_IDX 2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A 0x050c
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A 0x050d
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A_BASE_IDX 2
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x050e
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x050f
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2
#define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_A 0x0510
#define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_A_BASE_IDX 2
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0511
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B 0x0512
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX 2
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0513
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2
#define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_B 0x0514
#define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_B_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0515
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0516
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B 0x0517
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B 0x0518
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B 0x0519
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B 0x051a
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B 0x051b
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B_BASE_IDX 2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B 0x051c
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B_BASE_IDX 2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B 0x051d
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B 0x051e
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B_BASE_IDX 2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B 0x051f
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B 0x0520
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B_BASE_IDX 2
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0521
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0522
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2
#define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_B 0x0523
#define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_B_BASE_IDX 2
#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0524
#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
#define regDCHUBBUB_ARB_MALL_CNTL 0x0525
#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX 2
#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0526
#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0527
#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
#define regSURFACE_CHECK0_ADDRESS_LSB 0x0528
#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2
#define regSURFACE_CHECK0_ADDRESS_MSB 0x0529
#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2
#define regSURFACE_CHECK1_ADDRESS_LSB 0x052a
#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2
#define regSURFACE_CHECK1_ADDRESS_MSB 0x052b
#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2
#define regSURFACE_CHECK2_ADDRESS_LSB 0x052c
#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2
#define regSURFACE_CHECK2_ADDRESS_MSB 0x052d
#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2
#define regSURFACE_CHECK3_ADDRESS_LSB 0x052e
#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2
#define regSURFACE_CHECK3_ADDRESS_MSB 0x052f
#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2
#define regVTG0_CONTROL 0x0530
#define regVTG0_CONTROL_BASE_IDX 2
#define regVTG1_CONTROL 0x0531
#define regVTG1_CONTROL_BASE_IDX 2
#define regVTG2_CONTROL 0x0532
#define regVTG2_CONTROL_BASE_IDX 2
#define regVTG3_CONTROL 0x0533
#define regVTG3_CONTROL_BASE_IDX 2
#define regDCHUBBUB_SOFT_RESET 0x0534
#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2
#define regDCHUBBUB_CLOCK_CNTL 0x0535
#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
#define regDCFCLK_CNTL 0x0536
#define regDCFCLK_CNTL_BASE_IDX 2
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0537
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0538
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2
#define regDCHUBBUB_VLINE_SNAPSHOT 0x0539
#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
#define regDCHUBBUB_CTRL_STATUS 0x053a
#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x0540
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x0541
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2
#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x0542
#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2
#define regFMON_CTRL 0x0543
#define regFMON_CTRL_BASE_IDX 2
#define regDCHUBBUB_TEST_DEBUG_INDEX 0x0544
#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2
#define regDCHUBBUB_TEST_DEBUG_DATA 0x0545
#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dchubbubl_hubbub_sdpif_dispdec
// base address: 0x0
#define regDCHUBBUB_SDPIF_CFG0 0x046f
#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2
#define regDCHUBBUB_SDPIF_CFG1 0x0470
#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2
#define regDCHUBBUB_SDPIF_CFG2 0x0471
#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2
#define regVM_REQUEST_PHYSICAL 0x0472
#define regVM_REQUEST_PHYSICAL_BASE_IDX 2
#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473
#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2
#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474
#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2
#define regDCN_VM_FB_LOCATION_BASE 0x0475
#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2
#define regDCN_VM_FB_LOCATION_TOP 0x0476
#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2
#define regDCN_VM_FB_OFFSET 0x0477
#define regDCN_VM_FB_OFFSET_BASE_IDX 2
#define regDCN_VM_AGP_BOT 0x0478
#define regDCN_VM_AGP_BOT_BASE_IDX 2
#define regDCN_VM_AGP_TOP 0x0479
#define regDCN_VM_AGP_TOP_BASE_IDX 2
#define regDCN_VM_AGP_BASE 0x047a
#define regDCN_VM_AGP_BASE_BASE_IDX 2
#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b
#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2
#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c
#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2
#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d
#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2
#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e
#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2
#define regDCHUBBUB_SDPIF_PIPE_NOALLOC 0x047f
#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX 2
#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x0480
#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2
#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL 0x0481
#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX 2
#define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL 0x0482
#define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL_BASE_IDX 2
#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL 0x0483
#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX 2
#define regDCHUBBUB_SDPIF_PIPE_DATAFETCH 0x0484
#define regDCHUBBUB_SDPIF_PIPE_DATAFETCH_BASE_IDX 2
#define regSDPIF_REQUEST_RATE_LIMIT 0x0485
#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX 2
#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0486
#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2
#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0487
#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2
#define regDCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL 0x0488
#define regDCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL_BASE_IDX 2
// addressBlock: dcn_dcec_dchubbubl_hubbub_ret_path_dispdec
// base address: 0x0
#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af
#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0
#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
#define regDCHUBBUB_CRC_CTRL 0x04b1
#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2
#define regDCHUBBUB_CRC0_VAL_R_G 0x04b2
#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
#define regDCHUBBUB_CRC0_VAL_B_A 0x04b3
#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
#define regDCHUBBUB_CRC1_VAL_R_G 0x04b4
#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
#define regDCHUBBUB_CRC1_VAL_B_A 0x04b5
#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
#define regDCHUBBUB_DCC_STAT_CNTL 0x04b6
#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2
#define regDCHUBBUB_DCC_STAT0 0x04b7
#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2
#define regDCHUBBUB_DCC_STAT1 0x04b8
#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2
#define regDCHUBBUB_DCC_STAT2 0x04b9
#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2
#define regDCHUBBUB_COMPBUF_CTRL 0x04ba
#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2
#define regDCHUBBUB_DET0_CTRL 0x04bb
#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2
#define regDCHUBBUB_DET1_CTRL 0x04bc
#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2
#define regDCHUBBUB_DET2_CTRL 0x04bd
#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2
#define regDCHUBBUB_DET3_CTRL 0x04be
#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2
#define regDCHUBBUB_STAT 0x04bf
#define regDCHUBBUB_STAT_BASE_IDX 2
#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0
#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2
#define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1
#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2
#define regCOMPBUF_MEM_PWR_CTRL_2 0x04c2
#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2
#define regDCHUBBUB_MEM_PWR_STATUS 0x04c3
#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
#define regCOMPBUF_RESERVED_SPACE 0x04c4
#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2
#define regDCN_DECOMP_STATUS 0x04c5
#define regDCN_DECOMP_STATUS_BASE_IDX 2
#define regDCHUBBUB_DEBUG_CTRL_0 0x04c6
#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
#define regDCHUBBUB_DEBUG_CTRL_1 0x04c7
#define regDCHUBBUB_DEBUG_CTRL_1_BASE_IDX 2
#define regDCHUBBUB_DEBUG_CTRL_2 0x04c8
#define regDCHUBBUB_DEBUG_CTRL_2_BASE_IDX 2
#define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX 0x04c9
#define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX_BASE_IDX 2
#define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA 0x04ca
#define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dchubbubl_hubbub_vmrq_if_dispdec
// base address: 0x0
#define regDCN_VM_CONTEXT0_CNTL 0x0559
#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT1_CNTL 0x0560
#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT2_CNTL 0x0567
#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT3_CNTL 0x056e
#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT4_CNTL 0x0575
#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT5_CNTL 0x057c
#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT6_CNTL 0x0583
#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT7_CNTL 0x058a
#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT8_CNTL 0x0591
#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT9_CNTL 0x0598
#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT10_CNTL 0x059f
#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT11_CNTL 0x05a6
#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT12_CNTL 0x05ad
#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT13_CNTL 0x05b4
#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT14_CNTL 0x05bb
#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT15_CNTL 0x05c2
#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9
#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2
#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca
#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2
#define regDCN_VM_FAULT_CNTL 0x05cb
#define regDCN_VM_FAULT_CNTL_BASE_IDX 2
#define regDCN_VM_FAULT_STATUS 0x05cc
#define regDCN_VM_FAULT_STATUS_BASE_IDX 2
#define regDCN_VM_FAULT_ADDR_MSB 0x05cd
#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2
#define regDCN_VM_FAULT_ADDR_LSB 0x05ce
#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp0_dispdec_hubp_dispdec
// base address: 0x0
#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5
#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6
#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7
#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9
#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define regHUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE 0x05ea
#define regHUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX 2
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05eb
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05ec
#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ed
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ee
#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ef
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05f0
#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f1
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f2
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f3
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define regHUBP0_DCHUBP_CNTL 0x05f4
#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2
#define regHUBP0_HUBP_CLK_CNTL 0x05f5
#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f6
#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define regHUBP0_DCHUBP_MALL_CONFIG 0x05f7
#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX 2
#define regHUBP0_DCHUBP_MALL_SUB_VP0 0x05f8
#define regHUBP0_DCHUBP_MALL_SUB_VP0_BASE_IDX 2
#define regHUBP0_DCHUBP_MALL_SUB_VP1 0x05f9
#define regHUBP0_DCHUBP_MALL_SUB_VP1_BASE_IDX 2
#define regHUBP0_DCHUBP_MALL_SUB_VP2 0x05fa
#define regHUBP0_DCHUBP_MALL_SUB_VP2_BASE_IDX 2
#define regHUBP0_DCHUBP_MCACHEID_CONFIG 0x05fb
#define regHUBP0_DCHUBP_MCACHEID_CONFIG_BASE_IDX 2
#define regHUBP0_HUBPREQ_DEBUG_DB 0x05fc
#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define regHUBP0_HUBPREQ_DEBUG 0x05fd
#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
#define regHUBP0_HUBP_DEBUG_CTRL 0x05fe
#define regHUBP0_HUBP_DEBUG_CTRL_BASE_IDX 2
#define regHUBP0_HUBP_DEBUG_MUX_DCFCLK 0x05ff
#define regHUBP0_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2
#define regHUBP0_HUBP_DEBUG_MUX_DPPCLK 0x0600
#define regHUBP0_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0601
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0602
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
#define regHUBP0_HUBP_MALL_STATUS 0x0603
#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp0_dispdec_hubpreq_dispdec
// base address: 0x0
#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607
#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608
#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define regHUBPREQ0_VMID_SETTINGS_0 0x0609
#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x0612
#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x0613
#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x0614
#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0617
#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0618
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0619
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x061a
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x061b
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x061c
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x061d
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x061e
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x061f
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0620
#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
#define regHUBPREQ0_DCN_TTU_QOS_WM 0x0621
#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x0622
#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x0623
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x0624
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x0625
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x0626
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0627
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0628
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0629
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x062a
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x062b
#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x062c
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x062d
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x063a
#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define regHUBPREQ0_BLANK_OFFSET_0 0x063b
#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
#define regHUBPREQ0_BLANK_OFFSET_1 0x063c
#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
#define regHUBPREQ0_DST_DIMENSIONS 0x063d
#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
#define regHUBPREQ0_DST_AFTER_SCALER 0x063e
#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
#define regHUBPREQ0_PREFETCH_SETTINGS 0x063f
#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2
#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0640
#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2
#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x0641
#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x0642
#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x0643
#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x0644
#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x0645
#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ0_FLIP_PARAMETERS_0 0x0646
#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ0_FLIP_PARAMETERS_1 0x0647
#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0648
#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ0_NOM_PARAMETERS_0 0x0649
#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ0_NOM_PARAMETERS_1 0x064a
#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ0_NOM_PARAMETERS_2 0x064b
#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ0_NOM_PARAMETERS_3 0x064c
#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ0_NOM_PARAMETERS_4 0x064d
#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ0_NOM_PARAMETERS_5 0x064e
#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ0_NOM_PARAMETERS_6 0x064f
#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ0_NOM_PARAMETERS_7 0x0650
#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x0651
#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define regHUBPREQ0_PER_LINE_DELIVERY 0x0652
#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
#define regHUBPREQ0_CURSOR_SETTINGS 0x0653
#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2
#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x0654
#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x0655
#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x0656
#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0657
#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x065a
#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x065b
#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ0_FLIP_PARAMETERS_3 0x065c
#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ0_FLIP_PARAMETERS_4 0x065d
#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ0_FLIP_PARAMETERS_5 0x065e
#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ0_FLIP_PARAMETERS_6 0x065f
#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ0_UCLK_PSTATE_FORCE 0x0660
#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX 2
#define regHUBPREQ0_HUBPREQ_STATUS_REG0 0x0661
#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX 2
#define regHUBPREQ0_HUBPREQ_STATUS_REG1 0x0662
#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX 2
#define regHUBPREQ0_HUBPREQ_STATUS_REG2 0x0663
#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX 2
#define regHUBPREQ0_HUBPREQ_STATUS_REG3 0x0664
#define regHUBPREQ0_HUBPREQ_STATUS_REG3_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp0_dispdec_hubpret_dispdec
// base address: 0x0
#define regHUBPRET0_HUBPRET_CONTROL 0x066d
#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066e
#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066f
#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x0670
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0671
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define regHUBPRET0_HUBPRET_READ_LINE0 0x0672
#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
#define regHUBPRET0_HUBPRET_READ_LINE1 0x0673
#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
#define regHUBPRET0_HUBPRET_INTERRUPT 0x0674
#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0675
#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0676
#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp0_dispdec_cursor0_dispdec
// base address: 0x0
#define regCURSOR0_0_CURSOR_CONTROL 0x0679
#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x067a
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067b
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_0_CURSOR_SIZE 0x067c
#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2
#define regCURSOR0_0_CURSOR_POSITION 0x067d
#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2
#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067e
#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2
#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067f
#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define regCURSOR0_0_CURSOR_DST_OFFSET 0x0680
#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2
#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0681
#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0682
#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0683
#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0684
#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define regCURSOR0_0_DMDATA_CNTL 0x0685
#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2
#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0686
#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2
#define regCURSOR0_0_DMDATA_STATUS 0x0687
#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2
#define regCURSOR0_0_DMDATA_SW_CNTL 0x0688
#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2
#define regCURSOR0_0_DMDATA_SW_DATA 0x0689
#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2
#define regCURSOR0_0_HUBP_3DLUT_CONTROL 0x068a
#define regCURSOR0_0_HUBP_3DLUT_CONTROL_BASE_IDX 2
#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW 0x068b
#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2
#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH 0x068c
#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM 0x068d
#define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp1_dispdec_hubp_dispdec
// base address: 0x370
#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1
#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2
#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3
#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5
#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define regHUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE 0x06c6
#define regHUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX 2
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c7
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c8
#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c9
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06ca
#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06cb
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cc
#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cd
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06ce
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06cf
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define regHUBP1_DCHUBP_CNTL 0x06d0
#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2
#define regHUBP1_HUBP_CLK_CNTL 0x06d1
#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d2
#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define regHUBP1_DCHUBP_MALL_CONFIG 0x06d3
#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX 2
#define regHUBP1_DCHUBP_MALL_SUB_VP0 0x06d4
#define regHUBP1_DCHUBP_MALL_SUB_VP0_BASE_IDX 2
#define regHUBP1_DCHUBP_MALL_SUB_VP1 0x06d5
#define regHUBP1_DCHUBP_MALL_SUB_VP1_BASE_IDX 2
#define regHUBP1_DCHUBP_MALL_SUB_VP2 0x06d6
#define regHUBP1_DCHUBP_MALL_SUB_VP2_BASE_IDX 2
#define regHUBP1_DCHUBP_MCACHEID_CONFIG 0x06d7
#define regHUBP1_DCHUBP_MCACHEID_CONFIG_BASE_IDX 2
#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d8
#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define regHUBP1_HUBPREQ_DEBUG 0x06d9
#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
#define regHUBP1_HUBP_DEBUG_CTRL 0x06da
#define regHUBP1_HUBP_DEBUG_CTRL_BASE_IDX 2
#define regHUBP1_HUBP_DEBUG_MUX_DCFCLK 0x06db
#define regHUBP1_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2
#define regHUBP1_HUBP_DEBUG_MUX_DPPCLK 0x06dc
#define regHUBP1_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06dd
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06de
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
#define regHUBP1_HUBP_MALL_STATUS 0x06df
#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp1_dispdec_hubpreq_dispdec
// base address: 0x370
#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3
#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4
#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5
#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06ee
#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06ef
#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f0
#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06f3
#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06f4
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06f5
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06f6
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x06f7
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x06f8
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x06f9
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x06fa
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x06fb
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define regHUBPREQ1_DCN_EXPANSION_MODE 0x06fc
#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
#define regHUBPREQ1_DCN_TTU_QOS_WM 0x06fd
#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x06fe
#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x06ff
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0700
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0701
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x0702
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x0703
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0704
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x0705
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x0706
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0707
#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0708
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0709
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0716
#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define regHUBPREQ1_BLANK_OFFSET_0 0x0717
#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
#define regHUBPREQ1_BLANK_OFFSET_1 0x0718
#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
#define regHUBPREQ1_DST_DIMENSIONS 0x0719
#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
#define regHUBPREQ1_DST_AFTER_SCALER 0x071a
#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
#define regHUBPREQ1_PREFETCH_SETTINGS 0x071b
#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2
#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x071c
#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2
#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x071d
#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x071e
#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x071f
#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0720
#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x0721
#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ1_FLIP_PARAMETERS_0 0x0722
#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ1_FLIP_PARAMETERS_1 0x0723
#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ1_FLIP_PARAMETERS_2 0x0724
#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ1_NOM_PARAMETERS_0 0x0725
#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ1_NOM_PARAMETERS_1 0x0726
#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ1_NOM_PARAMETERS_2 0x0727
#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ1_NOM_PARAMETERS_3 0x0728
#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ1_NOM_PARAMETERS_4 0x0729
#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ1_NOM_PARAMETERS_5 0x072a
#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ1_NOM_PARAMETERS_6 0x072b
#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ1_NOM_PARAMETERS_7 0x072c
#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x072d
#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define regHUBPREQ1_PER_LINE_DELIVERY 0x072e
#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
#define regHUBPREQ1_CURSOR_SETTINGS 0x072f
#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2
#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0730
#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x0731
#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x0732
#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x0733
#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x0736
#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x0737
#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0738
#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0739
#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ1_FLIP_PARAMETERS_5 0x073a
#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ1_FLIP_PARAMETERS_6 0x073b
#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ1_UCLK_PSTATE_FORCE 0x073c
#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX 2
#define regHUBPREQ1_HUBPREQ_STATUS_REG0 0x073d
#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX 2
#define regHUBPREQ1_HUBPREQ_STATUS_REG1 0x073e
#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX 2
#define regHUBPREQ1_HUBPREQ_STATUS_REG2 0x073f
#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX 2
#define regHUBPREQ1_HUBPREQ_STATUS_REG3 0x0740
#define regHUBPREQ1_HUBPREQ_STATUS_REG3_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp1_dispdec_hubpret_dispdec
// base address: 0x370
#define regHUBPRET1_HUBPRET_CONTROL 0x0749
#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x074a
#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074b
#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074c
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074d
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define regHUBPRET1_HUBPRET_READ_LINE0 0x074e
#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
#define regHUBPRET1_HUBPRET_READ_LINE1 0x074f
#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
#define regHUBPRET1_HUBPRET_INTERRUPT 0x0750
#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0751
#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0752
#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp1_dispdec_cursor0_dispdec
// base address: 0x370
#define regCURSOR0_1_CURSOR_CONTROL 0x0755
#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0756
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0757
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_1_CURSOR_SIZE 0x0758
#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2
#define regCURSOR0_1_CURSOR_POSITION 0x0759
#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2
#define regCURSOR0_1_CURSOR_HOT_SPOT 0x075a
#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2
#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075b
#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075c
#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2
#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075d
#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075e
#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075f
#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x0760
#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define regCURSOR0_1_DMDATA_CNTL 0x0761
#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2
#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0762
#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2
#define regCURSOR0_1_DMDATA_STATUS 0x0763
#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2
#define regCURSOR0_1_DMDATA_SW_CNTL 0x0764
#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2
#define regCURSOR0_1_DMDATA_SW_DATA 0x0765
#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2
#define regCURSOR0_1_HUBP_3DLUT_CONTROL 0x0766
#define regCURSOR0_1_HUBP_3DLUT_CONTROL_BASE_IDX 2
#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW 0x0767
#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2
#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH 0x0768
#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM 0x0769
#define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp2_dispdec_hubp_dispdec
// base address: 0x6e0
#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d
#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e
#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define regHUBP2_DCSURF_TILING_CONFIG 0x079f
#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2
#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1
#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define regHUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE 0x07a2
#define regHUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX 2
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a3
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a4
#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a5
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a6
#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a7
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a8
#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a9
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07aa
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07ab
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define regHUBP2_DCHUBP_CNTL 0x07ac
#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2
#define regHUBP2_HUBP_CLK_CNTL 0x07ad
#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2
#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ae
#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define regHUBP2_DCHUBP_MALL_CONFIG 0x07af
#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX 2
#define regHUBP2_DCHUBP_MALL_SUB_VP0 0x07b0
#define regHUBP2_DCHUBP_MALL_SUB_VP0_BASE_IDX 2
#define regHUBP2_DCHUBP_MALL_SUB_VP1 0x07b1
#define regHUBP2_DCHUBP_MALL_SUB_VP1_BASE_IDX 2
#define regHUBP2_DCHUBP_MALL_SUB_VP2 0x07b2
#define regHUBP2_DCHUBP_MALL_SUB_VP2_BASE_IDX 2
#define regHUBP2_DCHUBP_MCACHEID_CONFIG 0x07b3
#define regHUBP2_DCHUBP_MCACHEID_CONFIG_BASE_IDX 2
#define regHUBP2_HUBPREQ_DEBUG_DB 0x07b4
#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define regHUBP2_HUBPREQ_DEBUG 0x07b5
#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
#define regHUBP2_HUBP_DEBUG_CTRL 0x07b6
#define regHUBP2_HUBP_DEBUG_CTRL_BASE_IDX 2
#define regHUBP2_HUBP_DEBUG_MUX_DCFCLK 0x07b7
#define regHUBP2_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2
#define regHUBP2_HUBP_DEBUG_MUX_DPPCLK 0x07b8
#define regHUBP2_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b9
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07ba
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
#define regHUBP2_HUBP_MALL_STATUS 0x07bb
#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp2_dispdec_hubpreq_dispdec
// base address: 0x6e0
#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf
#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0
#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1
#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07ca
#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07cb
#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07cc
#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07cf
#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d0
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07d1
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07d2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07d3
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07d4
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07d5
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07d6
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07d7
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07d8
#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2
#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07d9
#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2
#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07da
#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07db
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07dc
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07dd
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07de
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07df
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e0
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07e1
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07e2
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07e3
#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07e4
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07e5
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07f2
#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define regHUBPREQ2_BLANK_OFFSET_0 0x07f3
#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2
#define regHUBPREQ2_BLANK_OFFSET_1 0x07f4
#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2
#define regHUBPREQ2_DST_DIMENSIONS 0x07f5
#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2
#define regHUBPREQ2_DST_AFTER_SCALER 0x07f6
#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2
#define regHUBPREQ2_PREFETCH_SETTINGS 0x07f7
#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2
#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x07f8
#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2
#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x07f9
#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x07fa
#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x07fb
#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x07fc
#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x07fd
#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ2_FLIP_PARAMETERS_0 0x07fe
#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ2_FLIP_PARAMETERS_1 0x07ff
#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0800
#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ2_NOM_PARAMETERS_0 0x0801
#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ2_NOM_PARAMETERS_1 0x0802
#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ2_NOM_PARAMETERS_2 0x0803
#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ2_NOM_PARAMETERS_3 0x0804
#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ2_NOM_PARAMETERS_4 0x0805
#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ2_NOM_PARAMETERS_5 0x0806
#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ2_NOM_PARAMETERS_6 0x0807
#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ2_NOM_PARAMETERS_7 0x0808
#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2
#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0809
#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define regHUBPREQ2_PER_LINE_DELIVERY 0x080a
#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2
#define regHUBPREQ2_CURSOR_SETTINGS 0x080b
#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2
#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x080c
#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x080d
#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x080e
#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x080f
#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x0812
#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x0813
#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ2_FLIP_PARAMETERS_3 0x0814
#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ2_FLIP_PARAMETERS_4 0x0815
#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ2_FLIP_PARAMETERS_5 0x0816
#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ2_FLIP_PARAMETERS_6 0x0817
#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ2_UCLK_PSTATE_FORCE 0x0818
#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX 2
#define regHUBPREQ2_HUBPREQ_STATUS_REG0 0x0819
#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX 2
#define regHUBPREQ2_HUBPREQ_STATUS_REG1 0x081a
#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX 2
#define regHUBPREQ2_HUBPREQ_STATUS_REG2 0x081b
#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX 2
#define regHUBPREQ2_HUBPREQ_STATUS_REG3 0x081c
#define regHUBPREQ2_HUBPREQ_STATUS_REG3_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp2_dispdec_hubpret_dispdec
// base address: 0x6e0
#define regHUBPRET2_HUBPRET_CONTROL 0x0825
#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2
#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0826
#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0827
#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0828
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0829
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define regHUBPRET2_HUBPRET_READ_LINE0 0x082a
#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2
#define regHUBPRET2_HUBPRET_READ_LINE1 0x082b
#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2
#define regHUBPRET2_HUBPRET_INTERRUPT 0x082c
#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2
#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082d
#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082e
#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp2_dispdec_cursor0_dispdec
// base address: 0x6e0
#define regCURSOR0_2_CURSOR_CONTROL 0x0831
#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0832
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0833
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_2_CURSOR_SIZE 0x0834
#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2
#define regCURSOR0_2_CURSOR_POSITION 0x0835
#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2
#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0836
#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2
#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0837
#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0838
#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2
#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0839
#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x083a
#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083b
#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083c
#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define regCURSOR0_2_DMDATA_CNTL 0x083d
#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2
#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083e
#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2
#define regCURSOR0_2_DMDATA_STATUS 0x083f
#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2
#define regCURSOR0_2_DMDATA_SW_CNTL 0x0840
#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2
#define regCURSOR0_2_DMDATA_SW_DATA 0x0841
#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2
#define regCURSOR0_2_HUBP_3DLUT_CONTROL 0x0842
#define regCURSOR0_2_HUBP_3DLUT_CONTROL_BASE_IDX 2
#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW 0x0843
#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2
#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH 0x0844
#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM 0x0845
#define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp3_dispdec_hubp_dispdec
// base address: 0xa50
#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879
#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a
#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define regHUBP3_DCSURF_TILING_CONFIG 0x087b
#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2
#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d
#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define regHUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE 0x087e
#define regHUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX 2
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087f
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x0880
#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0881
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0882
#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0883
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0884
#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0885
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0886
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0887
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define regHUBP3_DCHUBP_CNTL 0x0888
#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2
#define regHUBP3_HUBP_CLK_CNTL 0x0889
#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
#define regHUBP3_DCHUBP_VMPG_CONFIG 0x088a
#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define regHUBP3_DCHUBP_MALL_CONFIG 0x088b
#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX 2
#define regHUBP3_DCHUBP_MALL_SUB_VP0 0x088c
#define regHUBP3_DCHUBP_MALL_SUB_VP0_BASE_IDX 2
#define regHUBP3_DCHUBP_MALL_SUB_VP1 0x088d
#define regHUBP3_DCHUBP_MALL_SUB_VP1_BASE_IDX 2
#define regHUBP3_DCHUBP_MALL_SUB_VP2 0x088e
#define regHUBP3_DCHUBP_MALL_SUB_VP2_BASE_IDX 2
#define regHUBP3_DCHUBP_MCACHEID_CONFIG 0x088f
#define regHUBP3_DCHUBP_MCACHEID_CONFIG_BASE_IDX 2
#define regHUBP3_HUBPREQ_DEBUG_DB 0x0890
#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define regHUBP3_HUBPREQ_DEBUG 0x0891
#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
#define regHUBP3_HUBP_DEBUG_CTRL 0x0892
#define regHUBP3_HUBP_DEBUG_CTRL_BASE_IDX 2
#define regHUBP3_HUBP_DEBUG_MUX_DCFCLK 0x0893
#define regHUBP3_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2
#define regHUBP3_HUBP_DEBUG_MUX_DPPCLK 0x0894
#define regHUBP3_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0895
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0896
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
#define regHUBP3_HUBP_MALL_STATUS 0x0897
#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp3_dispdec_hubpreq_dispdec
// base address: 0xa50
#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b
#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c
#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define regHUBPREQ3_VMID_SETTINGS_0 0x089d
#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08a6
#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08a7
#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08a8
#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08ab
#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08ac
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08ad
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08ae
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08af
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b0
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08b1
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08b2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08b3
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08b4
#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2
#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08b5
#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2
#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08b6
#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08b7
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08b8
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08b9
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08ba
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08bb
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08bc
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08bd
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08be
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08bf
#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c0
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08c1
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08ce
#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define regHUBPREQ3_BLANK_OFFSET_0 0x08cf
#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2
#define regHUBPREQ3_BLANK_OFFSET_1 0x08d0
#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2
#define regHUBPREQ3_DST_DIMENSIONS 0x08d1
#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2
#define regHUBPREQ3_DST_AFTER_SCALER 0x08d2
#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2
#define regHUBPREQ3_PREFETCH_SETTINGS 0x08d3
#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2
#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08d4
#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2
#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08d5
#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08d6
#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08d7
#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08d8
#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08d9
#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08da
#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08db
#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08dc
#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ3_NOM_PARAMETERS_0 0x08dd
#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2
#define regHUBPREQ3_NOM_PARAMETERS_1 0x08de
#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2
#define regHUBPREQ3_NOM_PARAMETERS_2 0x08df
#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2
#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e0
#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ3_NOM_PARAMETERS_4 0x08e1
#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ3_NOM_PARAMETERS_5 0x08e2
#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ3_NOM_PARAMETERS_6 0x08e3
#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ3_NOM_PARAMETERS_7 0x08e4
#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2
#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08e5
#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define regHUBPREQ3_PER_LINE_DELIVERY 0x08e6
#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2
#define regHUBPREQ3_CURSOR_SETTINGS 0x08e7
#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2
#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08e8
#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08e9
#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08ea
#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08eb
#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08ee
#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08ef
#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f0
#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2
#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08f1
#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2
#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08f2
#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2
#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08f3
#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2
#define regHUBPREQ3_UCLK_PSTATE_FORCE 0x08f4
#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX 2
#define regHUBPREQ3_HUBPREQ_STATUS_REG0 0x08f5
#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX 2
#define regHUBPREQ3_HUBPREQ_STATUS_REG1 0x08f6
#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX 2
#define regHUBPREQ3_HUBPREQ_STATUS_REG2 0x08f7
#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX 2
#define regHUBPREQ3_HUBPREQ_STATUS_REG3 0x08f8
#define regHUBPREQ3_HUBPREQ_STATUS_REG3_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp3_dispdec_hubpret_dispdec
// base address: 0xa50
#define regHUBPRET3_HUBPRET_CONTROL 0x0901
#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2
#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0902
#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0903
#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0904
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0905
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define regHUBPRET3_HUBPRET_READ_LINE0 0x0906
#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2
#define regHUBPRET3_HUBPRET_READ_LINE1 0x0907
#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2
#define regHUBPRET3_HUBPRET_INTERRUPT 0x0908
#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2
#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0909
#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x090a
#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcbubp3_dispdec_cursor0_dispdec
// base address: 0xa50
#define regCURSOR0_3_CURSOR_CONTROL 0x090d
#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090e
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090f
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_3_CURSOR_SIZE 0x0910
#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2
#define regCURSOR0_3_CURSOR_POSITION 0x0911
#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2
#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0912
#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2
#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0913
#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0914
#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2
#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0915
#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0916
#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0917
#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0918
#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define regCURSOR0_3_DMDATA_CNTL 0x0919
#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2
#define regCURSOR0_3_DMDATA_QOS_CNTL 0x091a
#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2
#define regCURSOR0_3_DMDATA_STATUS 0x091b
#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2
#define regCURSOR0_3_DMDATA_SW_CNTL 0x091c
#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2
#define regCURSOR0_3_DMDATA_SW_DATA 0x091d
#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2
#define regCURSOR0_3_HUBP_3DLUT_CONTROL 0x091e
#define regCURSOR0_3_HUBP_3DLUT_CONTROL_BASE_IDX 2
#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW 0x091f
#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2
#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH 0x0920
#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2
#define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM 0x0921
#define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2
// addressBlock: dcn_dcec_dpp0_dispdec_cnvc_cfg_dispdec
// base address: 0x0
#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf
#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0
#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2
#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1
#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2
#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2
#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2
#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3
#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2
#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4
#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2
#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5
#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2
#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6
#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2
#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7
#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2
#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8
#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2
#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9
#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2
#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda
#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2
#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb
#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2
#define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd
#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2
#define regCNVC_CFG0_PRE_DEALPHA 0x0cde
#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf
#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0
#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1
#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2
#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3
#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4
#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5
#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6
#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7
#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8
#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9
#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea
#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2
#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb
#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2
#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec
#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2
#define regCNVC_CFG0_PRE_DEGAM 0x0ced
#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2
#define regCNVC_CFG0_PRE_REALPHA 0x0cee
#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2
// addressBlock: dcn_dcec_dpp0_dispdec_cm_cur_dispdec
// base address: 0x0
#define regCM_CUR0_CURSOR0_CONTROL 0x0cf1
#define regCM_CUR0_CURSOR0_CONTROL_BASE_IDX 2
#define regCM_CUR0_CURSOR0_COLOR0 0x0cf2
#define regCM_CUR0_CURSOR0_COLOR0_BASE_IDX 2
#define regCM_CUR0_CURSOR0_COLOR1 0x0cf3
#define regCM_CUR0_CURSOR0_COLOR1_BASE_IDX 2
#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y 0x0cf4
#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2
#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0cf5
#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_MODE 0x0cf6
#define regCM_CUR0_CUR0_MATRIX_MODE_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C11_C12_A 0x0cf7
#define regCM_CUR0_CUR0_MATRIX_C11_C12_A_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C13_C14_A 0x0cf8
#define regCM_CUR0_CUR0_MATRIX_C13_C14_A_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C21_C22_A 0x0cf9
#define regCM_CUR0_CUR0_MATRIX_C21_C22_A_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C23_C24_A 0x0cfa
#define regCM_CUR0_CUR0_MATRIX_C23_C24_A_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C31_C32_A 0x0cfb
#define regCM_CUR0_CUR0_MATRIX_C31_C32_A_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C33_C34_A 0x0cfc
#define regCM_CUR0_CUR0_MATRIX_C33_C34_A_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C11_C12_B 0x0cfd
#define regCM_CUR0_CUR0_MATRIX_C11_C12_B_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C13_C14_B 0x0cfe
#define regCM_CUR0_CUR0_MATRIX_C13_C14_B_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C21_C22_B 0x0cff
#define regCM_CUR0_CUR0_MATRIX_C21_C22_B_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C23_C24_B 0x0d00
#define regCM_CUR0_CUR0_MATRIX_C23_C24_B_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C31_C32_B 0x0d01
#define regCM_CUR0_CUR0_MATRIX_C31_C32_B_BASE_IDX 2
#define regCM_CUR0_CUR0_MATRIX_C33_C34_B 0x0d02
#define regCM_CUR0_CUR0_MATRIX_C33_C34_B_BASE_IDX 2
// addressBlock: dcn_dcec_dpp0_dispdec_dscl_dispdec
// base address: 0x0
#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0d06
#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0d07
#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define regDSCL0_SCL_MODE 0x0d08
#define regDSCL0_SCL_MODE_BASE_IDX 2
#define regDSCL0_SCL_TAP_CONTROL 0x0d09
#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2
#define regDSCL0_DSCL_CONTROL 0x0d0a
#define regDSCL0_DSCL_CONTROL_BASE_IDX 2
#define regDSCL0_DSCL_2TAP_CONTROL 0x0d0b
#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2
#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0d0c
#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d0d
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d0e
#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d0f
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d10
#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d11
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d12
#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d13
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d14
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d15
#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d16
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define regDSCL0_SCL_BLACK_COLOR 0x0d17
#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2
#define regDSCL0_DSCL_UPDATE 0x0d18
#define regDSCL0_DSCL_UPDATE_BASE_IDX 2
#define regDSCL0_DSCL_AUTOCAL 0x0d19
#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2
#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d1a
#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d1b
#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define regDSCL0_OTG_H_BLANK 0x0d1c
#define regDSCL0_OTG_H_BLANK_BASE_IDX 2
#define regDSCL0_OTG_V_BLANK 0x0d1d
#define regDSCL0_OTG_V_BLANK_BASE_IDX 2
#define regDSCL0_RECOUT_START 0x0d1e
#define regDSCL0_RECOUT_START_BASE_IDX 2
#define regDSCL0_RECOUT_SIZE 0x0d1f
#define regDSCL0_RECOUT_SIZE_BASE_IDX 2
#define regDSCL0_MPC_SIZE 0x0d20
#define regDSCL0_MPC_SIZE_BASE_IDX 2
#define regDSCL0_LB_DATA_FORMAT 0x0d21
#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2
#define regDSCL0_LB_MEMORY_CTRL 0x0d22
#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2
#define regDSCL0_LB_V_COUNTER 0x0d23
#define regDSCL0_LB_V_COUNTER_BASE_IDX 2
#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d24
#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d25
#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define regDSCL0_OBUF_CONTROL 0x0d26
#define regDSCL0_OBUF_CONTROL_BASE_IDX 2
#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d27
#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_MODE 0x0d28
#define regDSCL0_DSCL_EASF_H_MODE_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_MODE 0x0d29
#define regDSCL0_DSCL_EASF_V_MODE_BASE_IDX 2
#define regDSCL0_DSCL_SC_MODE 0x0d2a
#define regDSCL0_DSCL_SC_MODE_BASE_IDX 2
#define regDSCL0_DSCL_SC_MATRIX_C0C1 0x0d2b
#define regDSCL0_DSCL_SC_MATRIX_C0C1_BASE_IDX 2
#define regDSCL0_DSCL_SC_MATRIX_C2C3 0x0d2c
#define regDSCL0_DSCL_SC_MATRIX_C2C3_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x0d2d
#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x0d2e
#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x0d2f
#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x0d30
#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x0d31
#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x0d32
#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x0d33
#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2
#define regDSCL0_DSCL_EASF_RINGEST_FORCE 0x0d34
#define regDSCL0_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF_CNTL 0x0d35
#define regDSCL0_DSCL_EASF_H_BF_CNTL_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x0d36
#define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF_CNTL 0x0d37
#define regDSCL0_DSCL_EASF_V_BF_CNTL_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x0d38
#define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0 0x0d39
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1 0x0d3a
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2 0x0d3b
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3 0x0d3c
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4 0x0d3d
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5 0x0d3e
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6 0x0d3f
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7 0x0d40
#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0 0x0d41
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1 0x0d42
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2 0x0d43
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3 0x0d44
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4 0x0d45
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5 0x0d46
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6 0x0d47
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7 0x0d48
#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0 0x0d49
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1 0x0d4a
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2 0x0d4b
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3 0x0d4c
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4 0x0d4d
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5 0x0d4e
#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0 0x0d4f
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1 0x0d50
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2 0x0d51
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3 0x0d52
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4 0x0d53
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5 0x0d54
#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2
#define regDSCL0_ISHARP_MODE 0x0d55
#define regDSCL0_ISHARP_MODE_BASE_IDX 2
#define regDSCL0_ISHARP_DELTA_CTRL 0x0d56
#define regDSCL0_ISHARP_DELTA_CTRL_BASE_IDX 2
#define regDSCL0_ISHARP_DELTA_INDEX 0x0d57
#define regDSCL0_ISHARP_DELTA_INDEX_BASE_IDX 2
#define regDSCL0_ISHARP_DELTA_DATA 0x0d58
#define regDSCL0_ISHARP_DELTA_DATA_BASE_IDX 2
#define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP 0x0d59
#define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2
#define regDSCL0_ISHARP_NOISEDET_THRESHOLD 0x0d5a
#define regDSCL0_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2
#define regDSCL0_ISHARP_NOISE_GAIN_PWL 0x0d5b
#define regDSCL0_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2
#define regDSCL0_ISHARP_LBA_PWL_SEG0 0x0d5c
#define regDSCL0_ISHARP_LBA_PWL_SEG0_BASE_IDX 2
#define regDSCL0_ISHARP_LBA_PWL_SEG1 0x0d5d
#define regDSCL0_ISHARP_LBA_PWL_SEG1_BASE_IDX 2
#define regDSCL0_ISHARP_LBA_PWL_SEG2 0x0d5e
#define regDSCL0_ISHARP_LBA_PWL_SEG2_BASE_IDX 2
#define regDSCL0_ISHARP_LBA_PWL_SEG3 0x0d5f
#define regDSCL0_ISHARP_LBA_PWL_SEG3_BASE_IDX 2
#define regDSCL0_ISHARP_LBA_PWL_SEG4 0x0d60
#define regDSCL0_ISHARP_LBA_PWL_SEG4_BASE_IDX 2
#define regDSCL0_ISHARP_LBA_PWL_SEG5 0x0d61
#define regDSCL0_ISHARP_LBA_PWL_SEG5_BASE_IDX 2
#define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x0d62
#define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dcn_dcec_dpp0_dispdec_cm_dispdec
// base address: 0x0
#define regCM0_CM_CONTROL 0x0d67
#define regCM0_CM_CONTROL_BASE_IDX 2
#define regCM0_CM_POST_CSC_CONTROL 0x0d68
#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2
#define regCM0_CM_POST_CSC_C11_C12 0x0d69
#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2
#define regCM0_CM_POST_CSC_C13_C14 0x0d6a
#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2
#define regCM0_CM_POST_CSC_C21_C22 0x0d6b
#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2
#define regCM0_CM_POST_CSC_C23_C24 0x0d6c
#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2
#define regCM0_CM_POST_CSC_C31_C32 0x0d6d
#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2
#define regCM0_CM_POST_CSC_C33_C34 0x0d6e
#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2
#define regCM0_CM_POST_CSC_B_C11_C12 0x0d6f
#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2
#define regCM0_CM_POST_CSC_B_C13_C14 0x0d70
#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2
#define regCM0_CM_POST_CSC_B_C21_C22 0x0d71
#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2
#define regCM0_CM_POST_CSC_B_C23_C24 0x0d72
#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2
#define regCM0_CM_POST_CSC_B_C31_C32 0x0d73
#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2
#define regCM0_CM_POST_CSC_B_C33_C34 0x0d74
#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2
#define regCM0_CM_BIAS_CR_R 0x0d75
#define regCM0_CM_BIAS_CR_R_BASE_IDX 2
#define regCM0_CM_BIAS_Y_G_CB_B 0x0d76
#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_CONTROL 0x0d77
#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2
#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d78
#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
#define regCM0_CM_GAMCOR_LUT_DATA 0x0d79
#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2
#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d7a
#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d7b
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d7c
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d7d
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d7e
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d7f
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d80
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d81
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d82
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d83
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d84
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d85
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d86
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d87
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d88
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d89
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d8a
#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d8b
#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d8c
#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d8d
#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d8e
#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d8f
#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d90
#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d91
#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d92
#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d93
#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d94
#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d95
#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d96
#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d97
#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d98
#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d99
#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d9a
#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d9b
#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d9c
#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d9d
#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d9e
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d9f
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0da0
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0da1
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0da2
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0da3
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0da4
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0da5
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0da6
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0da7
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0da8
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0da9
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0daa
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0dab
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0dac
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0dad
#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0dae
#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0daf
#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0db0
#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0db1
#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0db2
#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0db3
#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0db4
#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0db5
#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0db6
#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0db7
#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0db8
#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0db9
#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0dba
#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0dbb
#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0dbc
#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0dbd
#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0dbe
#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0dbf
#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0dc0
#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
#define regCM0_CM_HDR_MULT_COEF 0x0dc1
#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2
#define regCM0_CM_MEM_PWR_CTRL 0x0dc2
#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
#define regCM0_CM_MEM_PWR_STATUS 0x0dc3
#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
#define regCM0_CM_DEALPHA 0x0dc5
#define regCM0_CM_DEALPHA_BASE_IDX 2
#define regCM0_CM_COEF_FORMAT 0x0dc6
#define regCM0_CM_COEF_FORMAT_BASE_IDX 2
#define regCM0_CM_TEST_DEBUG_INDEX 0x0dc7
#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define regCM0_CM_TEST_DEBUG_DATA 0x0dc8
#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dpp0_dispdec_dpp_top_dispdec
// base address: 0x0
#define regDPP_TOP0_DPP_CONTROL 0x0cc5
#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2
#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6
#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2
#define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7
#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2
#define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8
#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2
#define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9
#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2
#define regDPP_TOP0_HOST_READ_CONTROL 0x0cca
#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dpp1_dispdec_cnvc_cfg_dispdec
// base address: 0x5ac
#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a
#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b
#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2
#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c
#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2
#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d
#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2
#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e
#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2
#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f
#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2
#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40
#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2
#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41
#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2
#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42
#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2
#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43
#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2
#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44
#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2
#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45
#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2
#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46
#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2
#define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48
#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2
#define regCNVC_CFG1_PRE_DEALPHA 0x0e49
#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a
#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b
#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c
#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d
#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e
#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f
#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50
#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51
#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52
#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53
#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54
#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55
#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2
#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56
#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2
#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57
#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2
#define regCNVC_CFG1_PRE_DEGAM 0x0e58
#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2
#define regCNVC_CFG1_PRE_REALPHA 0x0e59
#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2
// addressBlock: dcn_dcec_dpp1_dispdec_cm_cur_dispdec
// base address: 0x5ac
#define regCM_CUR1_CURSOR0_CONTROL 0x0e5c
#define regCM_CUR1_CURSOR0_CONTROL_BASE_IDX 2
#define regCM_CUR1_CURSOR0_COLOR0 0x0e5d
#define regCM_CUR1_CURSOR0_COLOR0_BASE_IDX 2
#define regCM_CUR1_CURSOR0_COLOR1 0x0e5e
#define regCM_CUR1_CURSOR0_COLOR1_BASE_IDX 2
#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y 0x0e5f
#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2
#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0e60
#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_MODE 0x0e61
#define regCM_CUR1_CUR0_MATRIX_MODE_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C11_C12_A 0x0e62
#define regCM_CUR1_CUR0_MATRIX_C11_C12_A_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C13_C14_A 0x0e63
#define regCM_CUR1_CUR0_MATRIX_C13_C14_A_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C21_C22_A 0x0e64
#define regCM_CUR1_CUR0_MATRIX_C21_C22_A_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C23_C24_A 0x0e65
#define regCM_CUR1_CUR0_MATRIX_C23_C24_A_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C31_C32_A 0x0e66
#define regCM_CUR1_CUR0_MATRIX_C31_C32_A_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C33_C34_A 0x0e67
#define regCM_CUR1_CUR0_MATRIX_C33_C34_A_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C11_C12_B 0x0e68
#define regCM_CUR1_CUR0_MATRIX_C11_C12_B_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C13_C14_B 0x0e69
#define regCM_CUR1_CUR0_MATRIX_C13_C14_B_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C21_C22_B 0x0e6a
#define regCM_CUR1_CUR0_MATRIX_C21_C22_B_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C23_C24_B 0x0e6b
#define regCM_CUR1_CUR0_MATRIX_C23_C24_B_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C31_C32_B 0x0e6c
#define regCM_CUR1_CUR0_MATRIX_C31_C32_B_BASE_IDX 2
#define regCM_CUR1_CUR0_MATRIX_C33_C34_B 0x0e6d
#define regCM_CUR1_CUR0_MATRIX_C33_C34_B_BASE_IDX 2
// addressBlock: dcn_dcec_dpp1_dispdec_dscl_dispdec
// base address: 0x5ac
#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e71
#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e72
#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define regDSCL1_SCL_MODE 0x0e73
#define regDSCL1_SCL_MODE_BASE_IDX 2
#define regDSCL1_SCL_TAP_CONTROL 0x0e74
#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2
#define regDSCL1_DSCL_CONTROL 0x0e75
#define regDSCL1_DSCL_CONTROL_BASE_IDX 2
#define regDSCL1_DSCL_2TAP_CONTROL 0x0e76
#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2
#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e77
#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e78
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e79
#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e7a
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e7b
#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e7c
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e7d
#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e7e
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e7f
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e80
#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e81
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define regDSCL1_SCL_BLACK_COLOR 0x0e82
#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2
#define regDSCL1_DSCL_UPDATE 0x0e83
#define regDSCL1_DSCL_UPDATE_BASE_IDX 2
#define regDSCL1_DSCL_AUTOCAL 0x0e84
#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2
#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e85
#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e86
#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define regDSCL1_OTG_H_BLANK 0x0e87
#define regDSCL1_OTG_H_BLANK_BASE_IDX 2
#define regDSCL1_OTG_V_BLANK 0x0e88
#define regDSCL1_OTG_V_BLANK_BASE_IDX 2
#define regDSCL1_RECOUT_START 0x0e89
#define regDSCL1_RECOUT_START_BASE_IDX 2
#define regDSCL1_RECOUT_SIZE 0x0e8a
#define regDSCL1_RECOUT_SIZE_BASE_IDX 2
#define regDSCL1_MPC_SIZE 0x0e8b
#define regDSCL1_MPC_SIZE_BASE_IDX 2
#define regDSCL1_LB_DATA_FORMAT 0x0e8c
#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2
#define regDSCL1_LB_MEMORY_CTRL 0x0e8d
#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2
#define regDSCL1_LB_V_COUNTER 0x0e8e
#define regDSCL1_LB_V_COUNTER_BASE_IDX 2
#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e8f
#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e90
#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define regDSCL1_OBUF_CONTROL 0x0e91
#define regDSCL1_OBUF_CONTROL_BASE_IDX 2
#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e92
#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_MODE 0x0e93
#define regDSCL1_DSCL_EASF_H_MODE_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_MODE 0x0e94
#define regDSCL1_DSCL_EASF_V_MODE_BASE_IDX 2
#define regDSCL1_DSCL_SC_MODE 0x0e95
#define regDSCL1_DSCL_SC_MODE_BASE_IDX 2
#define regDSCL1_DSCL_SC_MATRIX_C0C1 0x0e96
#define regDSCL1_DSCL_SC_MATRIX_C0C1_BASE_IDX 2
#define regDSCL1_DSCL_SC_MATRIX_C2C3 0x0e97
#define regDSCL1_DSCL_SC_MATRIX_C2C3_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x0e98
#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x0e99
#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x0e9a
#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x0e9b
#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x0e9c
#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x0e9d
#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x0e9e
#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2
#define regDSCL1_DSCL_EASF_RINGEST_FORCE 0x0e9f
#define regDSCL1_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF_CNTL 0x0ea0
#define regDSCL1_DSCL_EASF_H_BF_CNTL_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x0ea1
#define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF_CNTL 0x0ea2
#define regDSCL1_DSCL_EASF_V_BF_CNTL_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x0ea3
#define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0 0x0ea4
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1 0x0ea5
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2 0x0ea6
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3 0x0ea7
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4 0x0ea8
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5 0x0ea9
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6 0x0eaa
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7 0x0eab
#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0 0x0eac
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1 0x0ead
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2 0x0eae
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3 0x0eaf
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4 0x0eb0
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5 0x0eb1
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6 0x0eb2
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7 0x0eb3
#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0 0x0eb4
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1 0x0eb5
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2 0x0eb6
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3 0x0eb7
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4 0x0eb8
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5 0x0eb9
#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0 0x0eba
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1 0x0ebb
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2 0x0ebc
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3 0x0ebd
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4 0x0ebe
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5 0x0ebf
#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2
#define regDSCL1_ISHARP_MODE 0x0ec0
#define regDSCL1_ISHARP_MODE_BASE_IDX 2
#define regDSCL1_ISHARP_DELTA_CTRL 0x0ec1
#define regDSCL1_ISHARP_DELTA_CTRL_BASE_IDX 2
#define regDSCL1_ISHARP_DELTA_INDEX 0x0ec2
#define regDSCL1_ISHARP_DELTA_INDEX_BASE_IDX 2
#define regDSCL1_ISHARP_DELTA_DATA 0x0ec3
#define regDSCL1_ISHARP_DELTA_DATA_BASE_IDX 2
#define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP 0x0ec4
#define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2
#define regDSCL1_ISHARP_NOISEDET_THRESHOLD 0x0ec5
#define regDSCL1_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2
#define regDSCL1_ISHARP_NOISE_GAIN_PWL 0x0ec6
#define regDSCL1_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2
#define regDSCL1_ISHARP_LBA_PWL_SEG0 0x0ec7
#define regDSCL1_ISHARP_LBA_PWL_SEG0_BASE_IDX 2
#define regDSCL1_ISHARP_LBA_PWL_SEG1 0x0ec8
#define regDSCL1_ISHARP_LBA_PWL_SEG1_BASE_IDX 2
#define regDSCL1_ISHARP_LBA_PWL_SEG2 0x0ec9
#define regDSCL1_ISHARP_LBA_PWL_SEG2_BASE_IDX 2
#define regDSCL1_ISHARP_LBA_PWL_SEG3 0x0eca
#define regDSCL1_ISHARP_LBA_PWL_SEG3_BASE_IDX 2
#define regDSCL1_ISHARP_LBA_PWL_SEG4 0x0ecb
#define regDSCL1_ISHARP_LBA_PWL_SEG4_BASE_IDX 2
#define regDSCL1_ISHARP_LBA_PWL_SEG5 0x0ecc
#define regDSCL1_ISHARP_LBA_PWL_SEG5_BASE_IDX 2
#define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x0ecd
#define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dcn_dcec_dpp1_dispdec_cm_dispdec
// base address: 0x5ac
#define regCM1_CM_CONTROL 0x0ed2
#define regCM1_CM_CONTROL_BASE_IDX 2
#define regCM1_CM_POST_CSC_CONTROL 0x0ed3
#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2
#define regCM1_CM_POST_CSC_C11_C12 0x0ed4
#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2
#define regCM1_CM_POST_CSC_C13_C14 0x0ed5
#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2
#define regCM1_CM_POST_CSC_C21_C22 0x0ed6
#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2
#define regCM1_CM_POST_CSC_C23_C24 0x0ed7
#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2
#define regCM1_CM_POST_CSC_C31_C32 0x0ed8
#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2
#define regCM1_CM_POST_CSC_C33_C34 0x0ed9
#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2
#define regCM1_CM_POST_CSC_B_C11_C12 0x0eda
#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2
#define regCM1_CM_POST_CSC_B_C13_C14 0x0edb
#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2
#define regCM1_CM_POST_CSC_B_C21_C22 0x0edc
#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2
#define regCM1_CM_POST_CSC_B_C23_C24 0x0edd
#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2
#define regCM1_CM_POST_CSC_B_C31_C32 0x0ede
#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2
#define regCM1_CM_POST_CSC_B_C33_C34 0x0edf
#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2
#define regCM1_CM_BIAS_CR_R 0x0ee0
#define regCM1_CM_BIAS_CR_R_BASE_IDX 2
#define regCM1_CM_BIAS_Y_G_CB_B 0x0ee1
#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_CONTROL 0x0ee2
#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2
#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ee3
#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
#define regCM1_CM_GAMCOR_LUT_DATA 0x0ee4
#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2
#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0ee5
#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0ee6
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ee7
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0ee8
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0ee9
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eea
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eeb
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eec
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eed
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eee
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eef
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0ef0
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0ef1
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0ef2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0ef3
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0ef4
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ef5
#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ef6
#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ef7
#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ef8
#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ef9
#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0efa
#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0efb
#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0efc
#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0efd
#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0efe
#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0eff
#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0f00
#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0f01
#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0f02
#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0f03
#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0f04
#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0f05
#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0f06
#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0f07
#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0f08
#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0f09
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0f0a
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0f0b
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0f0c
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0f0d
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0f0e
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0f0f
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0f10
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0f11
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0f12
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0f13
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0f14
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0f15
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0f16
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0f17
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0f18
#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0f19
#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0f1a
#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0f1b
#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0f1c
#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0f1d
#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0f1e
#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0f1f
#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0f20
#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0f21
#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0f22
#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0f23
#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0f24
#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0f25
#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0f26
#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0f27
#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0f28
#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0f29
#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0f2a
#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0f2b
#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
#define regCM1_CM_HDR_MULT_COEF 0x0f2c
#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2
#define regCM1_CM_MEM_PWR_CTRL 0x0f2d
#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
#define regCM1_CM_MEM_PWR_STATUS 0x0f2e
#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
#define regCM1_CM_DEALPHA 0x0f30
#define regCM1_CM_DEALPHA_BASE_IDX 2
#define regCM1_CM_COEF_FORMAT 0x0f31
#define regCM1_CM_COEF_FORMAT_BASE_IDX 2
#define regCM1_CM_TEST_DEBUG_INDEX 0x0f32
#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define regCM1_CM_TEST_DEBUG_DATA 0x0f33
#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dpp1_dispdec_dpp_top_dispdec
// base address: 0x5ac
#define regDPP_TOP1_DPP_CONTROL 0x0e30
#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2
#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31
#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2
#define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32
#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2
#define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33
#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2
#define regDPP_TOP1_DPP_CRC_CTRL 0x0e34
#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2
#define regDPP_TOP1_HOST_READ_CONTROL 0x0e35
#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dpp2_dispdec_cnvc_cfg_dispdec
// base address: 0xb58
#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5
#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6
#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2
#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7
#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2
#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8
#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2
#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9
#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2
#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa
#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2
#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab
#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2
#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac
#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2
#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad
#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2
#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae
#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2
#define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf
#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2
#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0
#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2
#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1
#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2
#define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3
#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2
#define regCNVC_CFG2_PRE_DEALPHA 0x0fb4
#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5
#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6
#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7
#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8
#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9
#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba
#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb
#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc
#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd
#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe
#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf
#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0
#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2
#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1
#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2
#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2
#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2
#define regCNVC_CFG2_PRE_DEGAM 0x0fc3
#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2
#define regCNVC_CFG2_PRE_REALPHA 0x0fc4
#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2
// addressBlock: dcn_dcec_dpp2_dispdec_cm_cur_dispdec
// base address: 0xb58
#define regCM_CUR2_CURSOR0_CONTROL 0x0fc7
#define regCM_CUR2_CURSOR0_CONTROL_BASE_IDX 2
#define regCM_CUR2_CURSOR0_COLOR0 0x0fc8
#define regCM_CUR2_CURSOR0_COLOR0_BASE_IDX 2
#define regCM_CUR2_CURSOR0_COLOR1 0x0fc9
#define regCM_CUR2_CURSOR0_COLOR1_BASE_IDX 2
#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y 0x0fca
#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2
#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0fcb
#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_MODE 0x0fcc
#define regCM_CUR2_CUR0_MATRIX_MODE_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C11_C12_A 0x0fcd
#define regCM_CUR2_CUR0_MATRIX_C11_C12_A_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C13_C14_A 0x0fce
#define regCM_CUR2_CUR0_MATRIX_C13_C14_A_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C21_C22_A 0x0fcf
#define regCM_CUR2_CUR0_MATRIX_C21_C22_A_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C23_C24_A 0x0fd0
#define regCM_CUR2_CUR0_MATRIX_C23_C24_A_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C31_C32_A 0x0fd1
#define regCM_CUR2_CUR0_MATRIX_C31_C32_A_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C33_C34_A 0x0fd2
#define regCM_CUR2_CUR0_MATRIX_C33_C34_A_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C11_C12_B 0x0fd3
#define regCM_CUR2_CUR0_MATRIX_C11_C12_B_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C13_C14_B 0x0fd4
#define regCM_CUR2_CUR0_MATRIX_C13_C14_B_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C21_C22_B 0x0fd5
#define regCM_CUR2_CUR0_MATRIX_C21_C22_B_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C23_C24_B 0x0fd6
#define regCM_CUR2_CUR0_MATRIX_C23_C24_B_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C31_C32_B 0x0fd7
#define regCM_CUR2_CUR0_MATRIX_C31_C32_B_BASE_IDX 2
#define regCM_CUR2_CUR0_MATRIX_C33_C34_B 0x0fd8
#define regCM_CUR2_CUR0_MATRIX_C33_C34_B_BASE_IDX 2
// addressBlock: dcn_dcec_dpp2_dispdec_dscl_dispdec
// base address: 0xb58
#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fdc
#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fdd
#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define regDSCL2_SCL_MODE 0x0fde
#define regDSCL2_SCL_MODE_BASE_IDX 2
#define regDSCL2_SCL_TAP_CONTROL 0x0fdf
#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2
#define regDSCL2_DSCL_CONTROL 0x0fe0
#define regDSCL2_DSCL_CONTROL_BASE_IDX 2
#define regDSCL2_DSCL_2TAP_CONTROL 0x0fe1
#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2
#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fe2
#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fe3
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fe4
#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fe5
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fe6
#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fe7
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fe8
#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fe9
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fea
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0feb
#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fec
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define regDSCL2_SCL_BLACK_COLOR 0x0fed
#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2
#define regDSCL2_DSCL_UPDATE 0x0fee
#define regDSCL2_DSCL_UPDATE_BASE_IDX 2
#define regDSCL2_DSCL_AUTOCAL 0x0fef
#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2
#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0ff0
#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0ff1
#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define regDSCL2_OTG_H_BLANK 0x0ff2
#define regDSCL2_OTG_H_BLANK_BASE_IDX 2
#define regDSCL2_OTG_V_BLANK 0x0ff3
#define regDSCL2_OTG_V_BLANK_BASE_IDX 2
#define regDSCL2_RECOUT_START 0x0ff4
#define regDSCL2_RECOUT_START_BASE_IDX 2
#define regDSCL2_RECOUT_SIZE 0x0ff5
#define regDSCL2_RECOUT_SIZE_BASE_IDX 2
#define regDSCL2_MPC_SIZE 0x0ff6
#define regDSCL2_MPC_SIZE_BASE_IDX 2
#define regDSCL2_LB_DATA_FORMAT 0x0ff7
#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2
#define regDSCL2_LB_MEMORY_CTRL 0x0ff8
#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2
#define regDSCL2_LB_V_COUNTER 0x0ff9
#define regDSCL2_LB_V_COUNTER_BASE_IDX 2
#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0ffa
#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0ffb
#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define regDSCL2_OBUF_CONTROL 0x0ffc
#define regDSCL2_OBUF_CONTROL_BASE_IDX 2
#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ffd
#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_MODE 0x0ffe
#define regDSCL2_DSCL_EASF_H_MODE_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_MODE 0x0fff
#define regDSCL2_DSCL_EASF_V_MODE_BASE_IDX 2
#define regDSCL2_DSCL_SC_MODE 0x1000
#define regDSCL2_DSCL_SC_MODE_BASE_IDX 2
#define regDSCL2_DSCL_SC_MATRIX_C0C1 0x1001
#define regDSCL2_DSCL_SC_MATRIX_C0C1_BASE_IDX 2
#define regDSCL2_DSCL_SC_MATRIX_C2C3 0x1002
#define regDSCL2_DSCL_SC_MATRIX_C2C3_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x1003
#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x1004
#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1005
#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1006
#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1007
#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x1008
#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x1009
#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2
#define regDSCL2_DSCL_EASF_RINGEST_FORCE 0x100a
#define regDSCL2_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF_CNTL 0x100b
#define regDSCL2_DSCL_EASF_H_BF_CNTL_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x100c
#define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF_CNTL 0x100d
#define regDSCL2_DSCL_EASF_V_BF_CNTL_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x100e
#define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0 0x100f
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1 0x1010
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2 0x1011
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3 0x1012
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4 0x1013
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5 0x1014
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6 0x1015
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7 0x1016
#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0 0x1017
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1 0x1018
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2 0x1019
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3 0x101a
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4 0x101b
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5 0x101c
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6 0x101d
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7 0x101e
#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0 0x101f
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1 0x1020
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2 0x1021
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3 0x1022
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4 0x1023
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5 0x1024
#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0 0x1025
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1 0x1026
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2 0x1027
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3 0x1028
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4 0x1029
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5 0x102a
#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2
#define regDSCL2_ISHARP_MODE 0x102b
#define regDSCL2_ISHARP_MODE_BASE_IDX 2
#define regDSCL2_ISHARP_DELTA_CTRL 0x102c
#define regDSCL2_ISHARP_DELTA_CTRL_BASE_IDX 2
#define regDSCL2_ISHARP_DELTA_INDEX 0x102d
#define regDSCL2_ISHARP_DELTA_INDEX_BASE_IDX 2
#define regDSCL2_ISHARP_DELTA_DATA 0x102e
#define regDSCL2_ISHARP_DELTA_DATA_BASE_IDX 2
#define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP 0x102f
#define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2
#define regDSCL2_ISHARP_NOISEDET_THRESHOLD 0x1030
#define regDSCL2_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2
#define regDSCL2_ISHARP_NOISE_GAIN_PWL 0x1031
#define regDSCL2_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2
#define regDSCL2_ISHARP_LBA_PWL_SEG0 0x1032
#define regDSCL2_ISHARP_LBA_PWL_SEG0_BASE_IDX 2
#define regDSCL2_ISHARP_LBA_PWL_SEG1 0x1033
#define regDSCL2_ISHARP_LBA_PWL_SEG1_BASE_IDX 2
#define regDSCL2_ISHARP_LBA_PWL_SEG2 0x1034
#define regDSCL2_ISHARP_LBA_PWL_SEG2_BASE_IDX 2
#define regDSCL2_ISHARP_LBA_PWL_SEG3 0x1035
#define regDSCL2_ISHARP_LBA_PWL_SEG3_BASE_IDX 2
#define regDSCL2_ISHARP_LBA_PWL_SEG4 0x1036
#define regDSCL2_ISHARP_LBA_PWL_SEG4_BASE_IDX 2
#define regDSCL2_ISHARP_LBA_PWL_SEG5 0x1037
#define regDSCL2_ISHARP_LBA_PWL_SEG5_BASE_IDX 2
#define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x1038
#define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dcn_dcec_dpp2_dispdec_cm_dispdec
// base address: 0xb58
#define regCM2_CM_CONTROL 0x103d
#define regCM2_CM_CONTROL_BASE_IDX 2
#define regCM2_CM_POST_CSC_CONTROL 0x103e
#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2
#define regCM2_CM_POST_CSC_C11_C12 0x103f
#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2
#define regCM2_CM_POST_CSC_C13_C14 0x1040
#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2
#define regCM2_CM_POST_CSC_C21_C22 0x1041
#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2
#define regCM2_CM_POST_CSC_C23_C24 0x1042
#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2
#define regCM2_CM_POST_CSC_C31_C32 0x1043
#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2
#define regCM2_CM_POST_CSC_C33_C34 0x1044
#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2
#define regCM2_CM_POST_CSC_B_C11_C12 0x1045
#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2
#define regCM2_CM_POST_CSC_B_C13_C14 0x1046
#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2
#define regCM2_CM_POST_CSC_B_C21_C22 0x1047
#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2
#define regCM2_CM_POST_CSC_B_C23_C24 0x1048
#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2
#define regCM2_CM_POST_CSC_B_C31_C32 0x1049
#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2
#define regCM2_CM_POST_CSC_B_C33_C34 0x104a
#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2
#define regCM2_CM_BIAS_CR_R 0x104b
#define regCM2_CM_BIAS_CR_R_BASE_IDX 2
#define regCM2_CM_BIAS_Y_G_CB_B 0x104c
#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_CONTROL 0x104d
#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2
#define regCM2_CM_GAMCOR_LUT_INDEX 0x104e
#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
#define regCM2_CM_GAMCOR_LUT_DATA 0x104f
#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2
#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1050
#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1051
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1052
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1053
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1054
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1055
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1056
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1057
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1058
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x1059
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x105a
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x105b
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x105c
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x105d
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x105e
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x105f
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1060
#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1061
#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1062
#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1063
#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x1064
#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x1065
#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x1066
#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x1067
#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x1068
#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x1069
#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x106a
#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x106b
#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x106c
#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x106d
#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x106e
#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x106f
#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1070
#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1071
#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1072
#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1073
#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x1074
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x1075
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x1076
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x1077
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x1078
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x1079
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x107a
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x107b
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x107c
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x107d
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x107e
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x107f
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1080
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1081
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1082
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1083
#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x1084
#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x1085
#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x1086
#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x1087
#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x1088
#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x1089
#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x108a
#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x108b
#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x108c
#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x108d
#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x108e
#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x108f
#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1090
#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1091
#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1092
#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1093
#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x1094
#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x1095
#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x1096
#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
#define regCM2_CM_HDR_MULT_COEF 0x1097
#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2
#define regCM2_CM_MEM_PWR_CTRL 0x1098
#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
#define regCM2_CM_MEM_PWR_STATUS 0x1099
#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
#define regCM2_CM_DEALPHA 0x109b
#define regCM2_CM_DEALPHA_BASE_IDX 2
#define regCM2_CM_COEF_FORMAT 0x109c
#define regCM2_CM_COEF_FORMAT_BASE_IDX 2
#define regCM2_CM_TEST_DEBUG_INDEX 0x109d
#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define regCM2_CM_TEST_DEBUG_DATA 0x109e
#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dpp2_dispdec_dpp_top_dispdec
// base address: 0xb58
#define regDPP_TOP2_DPP_CONTROL 0x0f9b
#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2
#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c
#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2
#define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d
#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2
#define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e
#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2
#define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f
#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2
#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0
#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dpp3_dispdec_cnvc_cfg_dispdec
// base address: 0x1104
#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110
#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define regCNVC_CFG3_FORMAT_CONTROL 0x1111
#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2
#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112
#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2
#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113
#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2
#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114
#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2
#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115
#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2
#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116
#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2
#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117
#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2
#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118
#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2
#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119
#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2
#define regCNVC_CFG3_COLOR_KEYER_RED 0x111a
#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2
#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b
#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2
#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c
#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2
#define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e
#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2
#define regCNVC_CFG3_PRE_DEALPHA 0x111f
#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_MODE 0x1120
#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121
#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122
#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123
#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124
#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125
#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126
#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127
#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128
#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129
#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a
#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b
#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2
#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c
#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2
#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d
#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2
#define regCNVC_CFG3_PRE_DEGAM 0x112e
#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2
#define regCNVC_CFG3_PRE_REALPHA 0x112f
#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2
// addressBlock: dcn_dcec_dpp3_dispdec_cm_cur_dispdec
// base address: 0x1104
#define regCM_CUR3_CURSOR0_CONTROL 0x1132
#define regCM_CUR3_CURSOR0_CONTROL_BASE_IDX 2
#define regCM_CUR3_CURSOR0_COLOR0 0x1133
#define regCM_CUR3_CURSOR0_COLOR0_BASE_IDX 2
#define regCM_CUR3_CURSOR0_COLOR1 0x1134
#define regCM_CUR3_CURSOR0_COLOR1_BASE_IDX 2
#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y 0x1135
#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2
#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x1136
#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_MODE 0x1137
#define regCM_CUR3_CUR0_MATRIX_MODE_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C11_C12_A 0x1138
#define regCM_CUR3_CUR0_MATRIX_C11_C12_A_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C13_C14_A 0x1139
#define regCM_CUR3_CUR0_MATRIX_C13_C14_A_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C21_C22_A 0x113a
#define regCM_CUR3_CUR0_MATRIX_C21_C22_A_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C23_C24_A 0x113b
#define regCM_CUR3_CUR0_MATRIX_C23_C24_A_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C31_C32_A 0x113c
#define regCM_CUR3_CUR0_MATRIX_C31_C32_A_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C33_C34_A 0x113d
#define regCM_CUR3_CUR0_MATRIX_C33_C34_A_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C11_C12_B 0x113e
#define regCM_CUR3_CUR0_MATRIX_C11_C12_B_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C13_C14_B 0x113f
#define regCM_CUR3_CUR0_MATRIX_C13_C14_B_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C21_C22_B 0x1140
#define regCM_CUR3_CUR0_MATRIX_C21_C22_B_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C23_C24_B 0x1141
#define regCM_CUR3_CUR0_MATRIX_C23_C24_B_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C31_C32_B 0x1142
#define regCM_CUR3_CUR0_MATRIX_C31_C32_B_BASE_IDX 2
#define regCM_CUR3_CUR0_MATRIX_C33_C34_B 0x1143
#define regCM_CUR3_CUR0_MATRIX_C33_C34_B_BASE_IDX 2
// addressBlock: dcn_dcec_dpp3_dispdec_dscl_dispdec
// base address: 0x1104
#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x1147
#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x1148
#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define regDSCL3_SCL_MODE 0x1149
#define regDSCL3_SCL_MODE_BASE_IDX 2
#define regDSCL3_SCL_TAP_CONTROL 0x114a
#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2
#define regDSCL3_DSCL_CONTROL 0x114b
#define regDSCL3_DSCL_CONTROL_BASE_IDX 2
#define regDSCL3_DSCL_2TAP_CONTROL 0x114c
#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2
#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x114d
#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x114e
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define regDSCL3_SCL_HORZ_FILTER_INIT 0x114f
#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1150
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1151
#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1152
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define regDSCL3_SCL_VERT_FILTER_INIT 0x1153
#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1154
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1155
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1156
#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x1157
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define regDSCL3_SCL_BLACK_COLOR 0x1158
#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2
#define regDSCL3_DSCL_UPDATE 0x1159
#define regDSCL3_DSCL_UPDATE_BASE_IDX 2
#define regDSCL3_DSCL_AUTOCAL 0x115a
#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2
#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x115b
#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x115c
#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define regDSCL3_OTG_H_BLANK 0x115d
#define regDSCL3_OTG_H_BLANK_BASE_IDX 2
#define regDSCL3_OTG_V_BLANK 0x115e
#define regDSCL3_OTG_V_BLANK_BASE_IDX 2
#define regDSCL3_RECOUT_START 0x115f
#define regDSCL3_RECOUT_START_BASE_IDX 2
#define regDSCL3_RECOUT_SIZE 0x1160
#define regDSCL3_RECOUT_SIZE_BASE_IDX 2
#define regDSCL3_MPC_SIZE 0x1161
#define regDSCL3_MPC_SIZE_BASE_IDX 2
#define regDSCL3_LB_DATA_FORMAT 0x1162
#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2
#define regDSCL3_LB_MEMORY_CTRL 0x1163
#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2
#define regDSCL3_LB_V_COUNTER 0x1164
#define regDSCL3_LB_V_COUNTER_BASE_IDX 2
#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1165
#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1166
#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define regDSCL3_OBUF_CONTROL 0x1167
#define regDSCL3_OBUF_CONTROL_BASE_IDX 2
#define regDSCL3_OBUF_MEM_PWR_CTRL 0x1168
#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_MODE 0x1169
#define regDSCL3_DSCL_EASF_H_MODE_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_MODE 0x116a
#define regDSCL3_DSCL_EASF_V_MODE_BASE_IDX 2
#define regDSCL3_DSCL_SC_MODE 0x116b
#define regDSCL3_DSCL_SC_MODE_BASE_IDX 2
#define regDSCL3_DSCL_SC_MATRIX_C0C1 0x116c
#define regDSCL3_DSCL_SC_MATRIX_C0C1_BASE_IDX 2
#define regDSCL3_DSCL_SC_MATRIX_C2C3 0x116d
#define regDSCL3_DSCL_SC_MATRIX_C2C3_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x116e
#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x116f
#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1170
#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1171
#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1172
#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x1173
#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x1174
#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2
#define regDSCL3_DSCL_EASF_RINGEST_FORCE 0x1175
#define regDSCL3_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF_CNTL 0x1176
#define regDSCL3_DSCL_EASF_H_BF_CNTL_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x1177
#define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF_CNTL 0x1178
#define regDSCL3_DSCL_EASF_V_BF_CNTL_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x1179
#define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0 0x117a
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1 0x117b
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2 0x117c
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3 0x117d
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4 0x117e
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5 0x117f
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6 0x1180
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7 0x1181
#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0 0x1182
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1 0x1183
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2 0x1184
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3 0x1185
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4 0x1186
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5 0x1187
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6 0x1188
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7 0x1189
#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0 0x118a
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1 0x118b
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2 0x118c
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3 0x118d
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4 0x118e
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5 0x118f
#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0 0x1190
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1 0x1191
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2 0x1192
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3 0x1193
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4 0x1194
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5 0x1195
#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2
#define regDSCL3_ISHARP_MODE 0x1196
#define regDSCL3_ISHARP_MODE_BASE_IDX 2
#define regDSCL3_ISHARP_DELTA_CTRL 0x1197
#define regDSCL3_ISHARP_DELTA_CTRL_BASE_IDX 2
#define regDSCL3_ISHARP_DELTA_INDEX 0x1198
#define regDSCL3_ISHARP_DELTA_INDEX_BASE_IDX 2
#define regDSCL3_ISHARP_DELTA_DATA 0x1199
#define regDSCL3_ISHARP_DELTA_DATA_BASE_IDX 2
#define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP 0x119a
#define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2
#define regDSCL3_ISHARP_NOISEDET_THRESHOLD 0x119b
#define regDSCL3_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2
#define regDSCL3_ISHARP_NOISE_GAIN_PWL 0x119c
#define regDSCL3_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2
#define regDSCL3_ISHARP_LBA_PWL_SEG0 0x119d
#define regDSCL3_ISHARP_LBA_PWL_SEG0_BASE_IDX 2
#define regDSCL3_ISHARP_LBA_PWL_SEG1 0x119e
#define regDSCL3_ISHARP_LBA_PWL_SEG1_BASE_IDX 2
#define regDSCL3_ISHARP_LBA_PWL_SEG2 0x119f
#define regDSCL3_ISHARP_LBA_PWL_SEG2_BASE_IDX 2
#define regDSCL3_ISHARP_LBA_PWL_SEG3 0x11a0
#define regDSCL3_ISHARP_LBA_PWL_SEG3_BASE_IDX 2
#define regDSCL3_ISHARP_LBA_PWL_SEG4 0x11a1
#define regDSCL3_ISHARP_LBA_PWL_SEG4_BASE_IDX 2
#define regDSCL3_ISHARP_LBA_PWL_SEG5 0x11a2
#define regDSCL3_ISHARP_LBA_PWL_SEG5_BASE_IDX 2
#define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x11a3
#define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dcn_dcec_dpp3_dispdec_cm_dispdec
// base address: 0x1104
#define regCM3_CM_CONTROL 0x11a8
#define regCM3_CM_CONTROL_BASE_IDX 2
#define regCM3_CM_POST_CSC_CONTROL 0x11a9
#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2
#define regCM3_CM_POST_CSC_C11_C12 0x11aa
#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2
#define regCM3_CM_POST_CSC_C13_C14 0x11ab
#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2
#define regCM3_CM_POST_CSC_C21_C22 0x11ac
#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2
#define regCM3_CM_POST_CSC_C23_C24 0x11ad
#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2
#define regCM3_CM_POST_CSC_C31_C32 0x11ae
#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2
#define regCM3_CM_POST_CSC_C33_C34 0x11af
#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2
#define regCM3_CM_POST_CSC_B_C11_C12 0x11b0
#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2
#define regCM3_CM_POST_CSC_B_C13_C14 0x11b1
#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2
#define regCM3_CM_POST_CSC_B_C21_C22 0x11b2
#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2
#define regCM3_CM_POST_CSC_B_C23_C24 0x11b3
#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2
#define regCM3_CM_POST_CSC_B_C31_C32 0x11b4
#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2
#define regCM3_CM_POST_CSC_B_C33_C34 0x11b5
#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2
#define regCM3_CM_BIAS_CR_R 0x11b6
#define regCM3_CM_BIAS_CR_R_BASE_IDX 2
#define regCM3_CM_BIAS_Y_G_CB_B 0x11b7
#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_CONTROL 0x11b8
#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2
#define regCM3_CM_GAMCOR_LUT_INDEX 0x11b9
#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
#define regCM3_CM_GAMCOR_LUT_DATA 0x11ba
#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2
#define regCM3_CM_GAMCOR_LUT_CONTROL 0x11bb
#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x11bc
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x11bd
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x11be
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x11bf
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x11c0
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x11c1
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x11c2
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x11c3
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x11c4
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x11c5
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x11c6
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x11c7
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x11c8
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x11c9
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x11ca
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x11cb
#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x11cc
#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x11cd
#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x11ce
#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x11cf
#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x11d0
#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x11d1
#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x11d2
#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x11d3
#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x11d4
#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x11d5
#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x11d6
#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x11d7
#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x11d8
#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x11d9
#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11da
#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11db
#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11dc
#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11dd
#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11de
#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11df
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11e0
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11e1
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11e2
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11e3
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11e4
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11e5
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11e6
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11e7
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11e8
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11e9
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11ea
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11eb
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11ec
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11ed
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11ee
#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11ef
#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11f0
#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11f1
#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11f2
#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11f3
#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11f4
#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11f5
#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11f6
#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11f7
#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11f8
#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11f9
#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11fa
#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11fb
#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11fc
#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11fd
#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11fe
#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11ff
#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x1200
#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x1201
#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
#define regCM3_CM_HDR_MULT_COEF 0x1202
#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2
#define regCM3_CM_MEM_PWR_CTRL 0x1203
#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
#define regCM3_CM_MEM_PWR_STATUS 0x1204
#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
#define regCM3_CM_DEALPHA 0x1206
#define regCM3_CM_DEALPHA_BASE_IDX 2
#define regCM3_CM_COEF_FORMAT 0x1207
#define regCM3_CM_COEF_FORMAT_BASE_IDX 2
#define regCM3_CM_TEST_DEBUG_INDEX 0x1208
#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define regCM3_CM_TEST_DEBUG_DATA 0x1209
#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dpp3_dispdec_dpp_top_dispdec
// base address: 0x1104
#define regDPP_TOP3_DPP_CONTROL 0x1106
#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2
#define regDPP_TOP3_DPP_SOFT_RESET 0x1107
#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2
#define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108
#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2
#define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109
#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2
#define regDPP_TOP3_DPP_CRC_CTRL 0x110a
#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2
#define regDPP_TOP3_HOST_READ_CONTROL 0x110b
#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_mpc_mpcc0_dispdec
// base address: 0x0
#define regMPCC0_MPCC_TOP_SEL 0x0000
#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3
#define regMPCC0_MPCC_BOT_SEL 0x0001
#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3
#define regMPCC0_MPCC_OPP_ID 0x0002
#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3
#define regMPCC0_MPCC_CONTROL 0x0003
#define regMPCC0_MPCC_CONTROL_BASE_IDX 3
#define regMPCC0_MPCC_SM_CONTROL 0x0004
#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3
#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005
#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
#define regMPCC0_MPCC_TOP_GAIN 0x0006
#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3
#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007
#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008
#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0009
#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3
#define regMPCC0_MPCC_BG_R_CR 0x000a
#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3
#define regMPCC0_MPCC_BG_G_Y 0x000b
#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3
#define regMPCC0_MPCC_BG_B_CB 0x000c
#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3
#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000d
#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3
#define regMPCC0_MPCC_STATUS 0x000e
#define regMPCC0_MPCC_STATUS_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc1_dispdec
// base address: 0x54
#define regMPCC1_MPCC_TOP_SEL 0x0015
#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3
#define regMPCC1_MPCC_BOT_SEL 0x0016
#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3
#define regMPCC1_MPCC_OPP_ID 0x0017
#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3
#define regMPCC1_MPCC_CONTROL 0x0018
#define regMPCC1_MPCC_CONTROL_BASE_IDX 3
#define regMPCC1_MPCC_SM_CONTROL 0x0019
#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3
#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x001a
#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
#define regMPCC1_MPCC_TOP_GAIN 0x001b
#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3
#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x001c
#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x001d
#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x001e
#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3
#define regMPCC1_MPCC_BG_R_CR 0x001f
#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3
#define regMPCC1_MPCC_BG_G_Y 0x0020
#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3
#define regMPCC1_MPCC_BG_B_CB 0x0021
#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3
#define regMPCC1_MPCC_MEM_PWR_CTRL 0x0022
#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3
#define regMPCC1_MPCC_STATUS 0x0023
#define regMPCC1_MPCC_STATUS_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc2_dispdec
// base address: 0xa8
#define regMPCC2_MPCC_TOP_SEL 0x002a
#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3
#define regMPCC2_MPCC_BOT_SEL 0x002b
#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3
#define regMPCC2_MPCC_OPP_ID 0x002c
#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3
#define regMPCC2_MPCC_CONTROL 0x002d
#define regMPCC2_MPCC_CONTROL_BASE_IDX 3
#define regMPCC2_MPCC_SM_CONTROL 0x002e
#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3
#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x002f
#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
#define regMPCC2_MPCC_TOP_GAIN 0x0030
#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3
#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0031
#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0032
#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0033
#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3
#define regMPCC2_MPCC_BG_R_CR 0x0034
#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3
#define regMPCC2_MPCC_BG_G_Y 0x0035
#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3
#define regMPCC2_MPCC_BG_B_CB 0x0036
#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3
#define regMPCC2_MPCC_MEM_PWR_CTRL 0x0037
#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3
#define regMPCC2_MPCC_STATUS 0x0038
#define regMPCC2_MPCC_STATUS_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc3_dispdec
// base address: 0xfc
#define regMPCC3_MPCC_TOP_SEL 0x003f
#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3
#define regMPCC3_MPCC_BOT_SEL 0x0040
#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3
#define regMPCC3_MPCC_OPP_ID 0x0041
#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3
#define regMPCC3_MPCC_CONTROL 0x0042
#define regMPCC3_MPCC_CONTROL_BASE_IDX 3
#define regMPCC3_MPCC_SM_CONTROL 0x0043
#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3
#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0044
#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
#define regMPCC3_MPCC_TOP_GAIN 0x0045
#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3
#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0046
#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0047
#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0048
#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3
#define regMPCC3_MPCC_BG_R_CR 0x0049
#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3
#define regMPCC3_MPCC_BG_G_Y 0x004a
#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3
#define regMPCC3_MPCC_BG_B_CB 0x004b
#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3
#define regMPCC3_MPCC_MEM_PWR_CTRL 0x004c
#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3
#define regMPCC3_MPCC_STATUS 0x004d
#define regMPCC3_MPCC_STATUS_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpc_cfg_dispdec
// base address: 0x0
#define regMPC_CLOCK_CONTROL 0x02b2
#define regMPC_CLOCK_CONTROL_BASE_IDX 3
#define regMPC_SOFT_RESET 0x02b3
#define regMPC_SOFT_RESET_BASE_IDX 3
#define regMPC_CRC_CTRL 0x02b4
#define regMPC_CRC_CTRL_BASE_IDX 3
#define regMPC_CRC_SEL_CONTROL 0x02b5
#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3
#define regMPC_CRC_RESULT_AR 0x02b6
#define regMPC_CRC_RESULT_AR_BASE_IDX 3
#define regMPC_CRC_RESULT_GB 0x02b7
#define regMPC_CRC_RESULT_GB_BASE_IDX 3
#define regMPC_CRC_RESULT_C 0x02b8
#define regMPC_CRC_RESULT_C_BASE_IDX 3
#define regMPC_BYPASS_BG_AR 0x02bc
#define regMPC_BYPASS_BG_AR_BASE_IDX 3
#define regMPC_BYPASS_BG_GB 0x02bd
#define regMPC_BYPASS_BG_GB_BASE_IDX 3
#define regMPC_HOST_READ_CONTROL 0x02be
#define regMPC_HOST_READ_CONTROL_BASE_IDX 3
#define regMPC_DPP_PENDING_STATUS 0x02bf
#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3
#define regMPC_PENDING_STATUS_MISC 0x02c0
#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x02c1
#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3
#define regADR_CFG_VUPDATE_LOCK_SET0 0x02c2
#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3
#define regADR_VUPDATE_LOCK_SET0 0x02c3
#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3
#define regCFG_VUPDATE_LOCK_SET0 0x02c4
#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3
#define regCUR_VUPDATE_LOCK_SET0 0x02c5
#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x02c6
#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3
#define regADR_CFG_VUPDATE_LOCK_SET1 0x02c7
#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3
#define regADR_VUPDATE_LOCK_SET1 0x02c8
#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3
#define regCFG_VUPDATE_LOCK_SET1 0x02c9
#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3
#define regCUR_VUPDATE_LOCK_SET1 0x02ca
#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x02cb
#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3
#define regADR_CFG_VUPDATE_LOCK_SET2 0x02cc
#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3
#define regADR_VUPDATE_LOCK_SET2 0x02cd
#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3
#define regCFG_VUPDATE_LOCK_SET2 0x02ce
#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3
#define regCUR_VUPDATE_LOCK_SET2 0x02cf
#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x02d0
#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3
#define regADR_CFG_VUPDATE_LOCK_SET3 0x02d1
#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3
#define regADR_VUPDATE_LOCK_SET3 0x02d2
#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3
#define regCFG_VUPDATE_LOCK_SET3 0x02d3
#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3
#define regCUR_VUPDATE_LOCK_SET3 0x02d4
#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3
#define regHUBP0_3DLUT_FL_CONFIG 0x02d5
#define regHUBP0_3DLUT_FL_CONFIG_BASE_IDX 3
#define regHUBP0_3DLUT_FL_BIAS_SCALE 0x02d6
#define regHUBP0_3DLUT_FL_BIAS_SCALE_BASE_IDX 3
#define regHUBP1_3DLUT_FL_CONFIG 0x02d7
#define regHUBP1_3DLUT_FL_CONFIG_BASE_IDX 3
#define regHUBP1_3DLUT_FL_BIAS_SCALE 0x02d8
#define regHUBP1_3DLUT_FL_BIAS_SCALE_BASE_IDX 3
#define regHUBP2_3DLUT_FL_CONFIG 0x02d9
#define regHUBP2_3DLUT_FL_CONFIG_BASE_IDX 3
#define regHUBP2_3DLUT_FL_BIAS_SCALE 0x02da
#define regHUBP2_3DLUT_FL_BIAS_SCALE_BASE_IDX 3
#define regHUBP3_3DLUT_FL_CONFIG 0x02db
#define regHUBP3_3DLUT_FL_CONFIG_BASE_IDX 3
#define regHUBP3_3DLUT_FL_BIAS_SCALE 0x02dc
#define regHUBP3_3DLUT_FL_BIAS_SCALE_BASE_IDX 3
#define regMPC_DWB0_MUX 0x02ee
#define regMPC_DWB0_MUX_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc_ogam0_dispdec
// base address: 0x0
#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x007e
#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x007f
#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0080
#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0081
#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0082
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0083
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0084
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0085
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0086
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0087
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0088
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0089
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x008a
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x008b
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x008c
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x008d
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x008e
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x008f
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0090
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0091
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0092
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0093
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0094
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0095
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0096
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0097
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x0098
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x0099
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x009a
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x009b
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x009c
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x009d
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x009e
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x009f
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x00a0
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x00a1
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x00a2
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x00a3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x00a4
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x00a5
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x00a6
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x00a7
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x00a8
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x00a9
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x00aa
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x00ab
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x00ac
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x00ad
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x00ae
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x00af
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x00b0
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x00b1
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x00b2
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x00b3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x00b4
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x00b5
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x00b6
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x00b7
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x00b8
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x00b9
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x00ba
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x00bb
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x00bc
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x00bd
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x00be
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x00bf
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x00c0
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x00c1
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x00c2
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x00c3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x00c4
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x00c5
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x00c6
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x00c7
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x00c8
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x00c9
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x00ca
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x00cb
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x00cc
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x00cd
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x00ce
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x00cf
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x00d0
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x00d1
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x00d2
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x00d3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x00d4
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x00d5
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc_ogam1_dispdec
// base address: 0x178
#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x00dc
#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x00dd
#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x00de
#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x00df
#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x00e0
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x00e1
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x00e2
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x00e3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x00e4
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x00e5
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x00e6
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x00e7
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x00e8
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x00e9
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x00ea
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x00eb
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x00ec
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x00ed
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x00ee
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x00ef
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x00f0
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x00f1
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x00f2
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x00f3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x00f4
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x00f5
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x00f6
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x00f7
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x00f8
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x00f9
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x00fa
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x00fb
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x00fc
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x00fd
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x00fe
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x00ff
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x0100
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x0101
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x0102
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x0103
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x0104
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x0105
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0106
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0107
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0108
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0109
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x010a
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x010b
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x010c
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x010d
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x010e
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x010f
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x0110
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x0111
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x0112
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x0113
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x0114
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x0115
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x0116
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x0117
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x0118
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x0119
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x011a
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x011b
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x011c
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x011d
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x011e
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x011f
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x0120
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x0121
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x0122
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x0123
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x0124
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x0125
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0126
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x0127
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x0128
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x0129
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x012a
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x012b
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x012c
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x012d
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x012e
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x012f
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x0130
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x0131
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x0132
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x0133
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc_ogam2_dispdec
// base address: 0x2f0
#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x013a
#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x013b
#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x013c
#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x013d
#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x013e
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x013f
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0140
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0141
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0142
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0143
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0144
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0145
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0146
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x0147
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x0148
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x0149
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x014a
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x014b
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x014c
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x014d
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x014e
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x014f
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0150
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0151
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0152
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0153
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x0154
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x0155
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x0156
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x0157
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x0158
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x0159
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x015a
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x015b
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x015c
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x015d
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x015e
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x015f
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0160
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0161
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0162
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0163
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0164
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0165
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0166
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0167
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0168
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0169
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x016a
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x016b
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x016c
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x016d
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x016e
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x016f
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0170
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0171
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0172
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0173
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x0174
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x0175
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x0176
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x0177
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x0178
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x0179
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x017a
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x017b
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x017c
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x017d
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x017e
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x017f
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0180
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0181
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0182
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0183
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0184
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x0185
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x0186
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x0187
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x0188
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x0189
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x018a
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x018b
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x018c
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x018d
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x018e
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x018f
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0190
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0191
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc_ogam3_dispdec
// base address: 0x468
#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0198
#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0199
#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x019a
#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x019b
#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x019c
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x019d
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x019e
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x019f
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x01a0
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x01a1
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x01a2
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x01a3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x01a4
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x01a5
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x01a6
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x01a7
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x01a8
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x01a9
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x01aa
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x01ab
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x01ac
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x01ad
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x01ae
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x01af
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x01b0
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x01b1
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x01b2
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x01b3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x01b4
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x01b5
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x01b6
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x01b7
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x01b8
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x01b9
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x01ba
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x01bb
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x01bc
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x01bd
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x01be
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x01bf
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x01c0
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x01c1
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01c2
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01c3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01c4
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01c5
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01c6
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01c7
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x01c8
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x01c9
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x01ca
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x01cb
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x01cc
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x01cd
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x01ce
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x01cf
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x01d0
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x01d1
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x01d2
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x01d3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x01d4
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x01d5
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x01d6
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x01d7
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x01d8
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x01d9
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x01da
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x01db
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x01dc
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x01dd
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x01de
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x01df
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x01e0
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x01e1
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01e2
#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x01e3
#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x01e4
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x01e5
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x01e6
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x01e7
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x01e8
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x01e9
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x01ea
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x01eb
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x01ec
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x01ed
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x01ee
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x01ef
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc_mcm0_dispdec
// base address: 0x0
#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL 0x0453
#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R 0x0454
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G 0x0455
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B 0x0456
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R 0x0457
#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B 0x0458
#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX 0x0459
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA 0x045a
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x045b
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x045c
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x045d
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x045e
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x045f
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0460
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0461
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0462
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0463
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0464
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0465
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0466
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0467
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0468
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0469
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x046a
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x046b
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x046c
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x046d
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x046e
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x046f
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0470
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0471
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0472
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0473
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0474
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0475
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0476
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0477
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0478
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0479
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x047a
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x047b
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x047c
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x047d
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x047e
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x047f
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0480
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0481
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0482
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0483
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0484
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0485
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0486
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0487
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0488
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0489
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE 0x048a
#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX 0x048b
#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA 0x048c
#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT 0x048d
#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x048e
#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x048f
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0490
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0491
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0492
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL 0x0493
#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX 0x0494
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA 0x0495
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL 0x0496
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0497
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0498
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0499
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x049a
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x049b
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x049c
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x049d
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x049e
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x049f
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x04a0
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x04a1
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x04a2
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x04a3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x04a4
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x04a5
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x04a6
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x04a7
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x04a8
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x04a9
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x04aa
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x04ab
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x04ac
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x04ad
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x04ae
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x04af
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x04b0
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x04b1
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x04b2
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x04b3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x04b4
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x04b5
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x04b6
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x04b7
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x04b8
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x04b9
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x04ba
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x04bb
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x04bc
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x04bd
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x04be
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x04bf
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x04c0
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x04c1
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x04c2
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x04c3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x04c4
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x04c5
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x04c6
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x04c7
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x04c8
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x04c9
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x04ca
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x04cb
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x04cc
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x04cd
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x04ce
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x04cf
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x04d0
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x04d1
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x04d2
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x04d3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x04d4
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x04d5
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x04d6
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x04d7
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x04d8
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x04d9
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x04da
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x04db
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x04dc
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x04dd
#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x04de
#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x04df
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x04e0
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x04e1
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x04e2
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x04e3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x04e4
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x04e5
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x04e6
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x04e7
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x04e8
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x04e9
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x04ea
#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x04eb
#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x04ec
#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x04ed
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x04ee
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x04ef
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x04f0
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x04f1
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x04f2
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x04f3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x04f4
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x04f5
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x04f6
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x04f7
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x04f8
#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL 0x04f9
#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x04fa
#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x04fb
#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc_mcm1_dispdec
// base address: 0x2c0
#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL 0x0503
#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R 0x0504
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G 0x0505
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B 0x0506
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R 0x0507
#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B 0x0508
#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX 0x0509
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA 0x050a
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x050b
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x050c
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x050d
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x050e
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x050f
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0510
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0511
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0512
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0513
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0514
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0515
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0516
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0517
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0518
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0519
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x051a
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x051b
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x051c
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x051d
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x051e
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x051f
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0520
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0521
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0522
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0523
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0524
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0525
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0526
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0527
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0528
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0529
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x052a
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x052b
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x052c
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x052d
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x052e
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x052f
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0530
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0531
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0532
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0533
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0534
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0535
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0536
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0537
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0538
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0539
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE 0x053a
#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX 0x053b
#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA 0x053c
#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT 0x053d
#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x053e
#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x053f
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0540
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0541
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0542
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL 0x0543
#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX 0x0544
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA 0x0545
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL 0x0546
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0547
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0548
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0549
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x054a
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x054b
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x054c
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x054d
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x054e
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x054f
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0550
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0551
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0552
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0553
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0554
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0555
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0556
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0557
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0558
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0559
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x055a
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x055b
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x055c
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x055d
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x055e
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x055f
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0560
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0561
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0562
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0563
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0564
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0565
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0566
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0567
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0568
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0569
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x056a
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x056b
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x056c
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x056d
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x056e
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x056f
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0570
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0571
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0572
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0573
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0574
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0575
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0576
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0577
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0578
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0579
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x057a
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x057b
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x057c
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x057d
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x057e
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x057f
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0580
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0581
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0582
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0583
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0584
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0585
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0586
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0587
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0588
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0589
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x058a
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x058b
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x058c
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x058d
#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x058e
#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x058f
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x0590
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x0591
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x0592
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x0593
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x0594
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x0595
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x0596
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x0597
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x0598
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x0599
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x059a
#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x059b
#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x059c
#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x059d
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x059e
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x059f
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x05a0
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x05a1
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x05a2
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x05a3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x05a4
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x05a5
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x05a6
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x05a7
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x05a8
#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL 0x05a9
#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x05aa
#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x05ab
#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc_mcm2_dispdec
// base address: 0x580
#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL 0x05b3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R 0x05b4
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G 0x05b5
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B 0x05b6
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R 0x05b7
#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B 0x05b8
#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX 0x05b9
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA 0x05ba
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x05bb
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x05bc
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x05bd
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x05be
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x05bf
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x05c0
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x05c1
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x05c2
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x05c3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x05c4
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x05c5
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x05c6
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x05c7
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x05c8
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x05c9
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x05ca
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x05cb
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x05cc
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x05cd
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x05ce
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x05cf
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x05d0
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x05d1
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x05d2
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x05d3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x05d4
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x05d5
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x05d6
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x05d7
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x05d8
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x05d9
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x05da
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x05db
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x05dc
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x05dd
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x05de
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x05df
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x05e0
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x05e1
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x05e2
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x05e3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x05e4
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x05e5
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x05e6
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x05e7
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x05e8
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x05e9
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE 0x05ea
#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX 0x05eb
#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA 0x05ec
#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT 0x05ed
#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x05ee
#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x05ef
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x05f0
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x05f1
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x05f2
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL 0x05f3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX 0x05f4
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA 0x05f5
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL 0x05f6
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x05f7
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x05f8
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x05f9
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x05fa
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x05fb
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x05fc
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x05fd
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x05fe
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x05ff
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0600
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0601
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0602
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0603
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0604
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0605
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0606
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0607
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0608
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0609
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x060a
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x060b
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x060c
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x060d
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x060e
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x060f
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0610
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0611
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0612
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0613
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0614
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0615
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0616
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0617
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0618
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0619
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x061a
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x061b
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x061c
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x061d
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x061e
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x061f
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0620
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0621
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0622
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0623
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0624
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0625
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0626
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0627
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0628
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0629
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x062a
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x062b
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x062c
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x062d
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x062e
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x062f
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0630
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0631
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0632
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0633
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0634
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0635
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0636
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0637
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0638
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0639
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x063a
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x063b
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x063c
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x063d
#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x063e
#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x063f
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x0640
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x0641
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x0642
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x0643
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x0644
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x0645
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x0646
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x0647
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x0648
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x0649
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x064a
#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x064b
#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x064c
#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x064d
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x064e
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x064f
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x0650
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x0651
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x0652
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x0653
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x0654
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x0655
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x0656
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x0657
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x0658
#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL 0x0659
#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x065a
#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x065b
#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpcc_mcm3_dispdec
// base address: 0x840
#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL 0x0663
#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R 0x0664
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G 0x0665
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B 0x0666
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R 0x0667
#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B 0x0668
#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX 0x0669
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA 0x066a
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x066b
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x066c
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x066d
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x066e
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x066f
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0670
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0671
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0672
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0673
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0674
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0675
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0676
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0677
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0678
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0679
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x067a
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x067b
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x067c
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x067d
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x067e
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x067f
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0680
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0681
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0682
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0683
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0684
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0685
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0686
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0687
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0688
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0689
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x068a
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x068b
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x068c
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x068d
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x068e
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x068f
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0690
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0691
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0692
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0693
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0694
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0695
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0696
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0697
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0698
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0699
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE 0x069a
#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX 0x069b
#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA 0x069c
#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT 0x069d
#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x069e
#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x069f
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x06a0
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x06a1
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x06a2
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL 0x06a3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX 0x06a4
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA 0x06a5
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL 0x06a6
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x06a7
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x06a8
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x06a9
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x06aa
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x06ab
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x06ac
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x06ad
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x06ae
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x06af
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x06b0
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x06b1
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x06b2
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x06b3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x06b4
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x06b5
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x06b6
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x06b7
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x06b8
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x06b9
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x06ba
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x06bb
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x06bc
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x06bd
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x06be
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x06bf
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x06c0
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x06c1
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x06c2
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x06c3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x06c4
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x06c5
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x06c6
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x06c7
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x06c8
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x06c9
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x06ca
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x06cb
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x06cc
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x06cd
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x06ce
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x06cf
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x06d0
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x06d1
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x06d2
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x06d3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x06d4
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x06d5
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x06d6
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x06d7
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x06d8
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x06d9
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x06da
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x06db
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x06dc
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x06dd
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x06de
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x06df
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x06e0
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x06e1
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x06e2
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x06e3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x06e4
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x06e5
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x06e6
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x06e7
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x06e8
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x06e9
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x06ea
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x06eb
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x06ec
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x06ed
#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x06ee
#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x06ef
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x06f0
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x06f1
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x06f2
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x06f3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x06f4
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x06f5
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x06f6
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x06f7
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x06f8
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x06f9
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x06fa
#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x06fb
#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x06fc
#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x06fd
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x06fe
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x06ff
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x0700
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x0701
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x0702
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x0703
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x0704
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x0705
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x0706
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x0707
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x0708
#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL 0x0709
#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x070a
#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x070b
#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3
// addressBlock: dcn_dcec_mpc_mpc_ocsc_dispdec
// base address: 0x0
#define regMPC_OUT0_MUX 0x02f2
#define regMPC_OUT0_MUX_BASE_IDX 3
#define regMPC_OUT0_DENORM_CONTROL 0x02f3
#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3
#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x02f4
#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3
#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x02f5
#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3
#define regMPC_OUT1_MUX 0x02f6
#define regMPC_OUT1_MUX_BASE_IDX 3
#define regMPC_OUT1_DENORM_CONTROL 0x02f7
#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3
#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x02f8
#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3
#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x02f9
#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3
#define regMPC_OUT2_MUX 0x02fa
#define regMPC_OUT2_MUX_BASE_IDX 3
#define regMPC_OUT2_DENORM_CONTROL 0x02fb
#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3
#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x02fc
#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3
#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x02fd
#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3
#define regMPC_OUT3_MUX 0x02fe
#define regMPC_OUT3_MUX_BASE_IDX 3
#define regMPC_OUT3_DENORM_CONTROL 0x02ff
#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3
#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x0300
#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3
#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x0301
#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3
#define regMPC_OUT_CSC_COEF_FORMAT 0x030a
#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3
#define regMPC_OUT0_CSC_MODE 0x030b
#define regMPC_OUT0_CSC_MODE_BASE_IDX 3
#define regMPC_OUT0_CSC_C11_C12_A 0x030c
#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3
#define regMPC_OUT0_CSC_C13_C14_A 0x030d
#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3
#define regMPC_OUT0_CSC_C21_C22_A 0x030e
#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3
#define regMPC_OUT0_CSC_C23_C24_A 0x030f
#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3
#define regMPC_OUT0_CSC_C31_C32_A 0x0310
#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3
#define regMPC_OUT0_CSC_C33_C34_A 0x0311
#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3
#define regMPC_OUT0_CSC_C11_C12_B 0x0312
#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3
#define regMPC_OUT0_CSC_C13_C14_B 0x0313
#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3
#define regMPC_OUT0_CSC_C21_C22_B 0x0314
#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3
#define regMPC_OUT0_CSC_C23_C24_B 0x0315
#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3
#define regMPC_OUT0_CSC_C31_C32_B 0x0316
#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3
#define regMPC_OUT0_CSC_C33_C34_B 0x0317
#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3
#define regMPC_OUT1_CSC_MODE 0x0318
#define regMPC_OUT1_CSC_MODE_BASE_IDX 3
#define regMPC_OUT1_CSC_C11_C12_A 0x0319
#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3
#define regMPC_OUT1_CSC_C13_C14_A 0x031a
#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3
#define regMPC_OUT1_CSC_C21_C22_A 0x031b
#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3
#define regMPC_OUT1_CSC_C23_C24_A 0x031c
#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3
#define regMPC_OUT1_CSC_C31_C32_A 0x031d
#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3
#define regMPC_OUT1_CSC_C33_C34_A 0x031e
#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3
#define regMPC_OUT1_CSC_C11_C12_B 0x031f
#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3
#define regMPC_OUT1_CSC_C13_C14_B 0x0320
#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3
#define regMPC_OUT1_CSC_C21_C22_B 0x0321
#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3
#define regMPC_OUT1_CSC_C23_C24_B 0x0322
#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3
#define regMPC_OUT1_CSC_C31_C32_B 0x0323
#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3
#define regMPC_OUT1_CSC_C33_C34_B 0x0324
#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3
#define regMPC_OUT2_CSC_MODE 0x0325
#define regMPC_OUT2_CSC_MODE_BASE_IDX 3
#define regMPC_OUT2_CSC_C11_C12_A 0x0326
#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3
#define regMPC_OUT2_CSC_C13_C14_A 0x0327
#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3
#define regMPC_OUT2_CSC_C21_C22_A 0x0328
#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3
#define regMPC_OUT2_CSC_C23_C24_A 0x0329
#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3
#define regMPC_OUT2_CSC_C31_C32_A 0x032a
#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3
#define regMPC_OUT2_CSC_C33_C34_A 0x032b
#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3
#define regMPC_OUT2_CSC_C11_C12_B 0x032c
#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3
#define regMPC_OUT2_CSC_C13_C14_B 0x032d
#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3
#define regMPC_OUT2_CSC_C21_C22_B 0x032e
#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3
#define regMPC_OUT2_CSC_C23_C24_B 0x032f
#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3
#define regMPC_OUT2_CSC_C31_C32_B 0x0330
#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3
#define regMPC_OUT2_CSC_C33_C34_B 0x0331
#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3
#define regMPC_OUT3_CSC_MODE 0x0332
#define regMPC_OUT3_CSC_MODE_BASE_IDX 3
#define regMPC_OUT3_CSC_C11_C12_A 0x0333
#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3
#define regMPC_OUT3_CSC_C13_C14_A 0x0334
#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3
#define regMPC_OUT3_CSC_C21_C22_A 0x0335
#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3
#define regMPC_OUT3_CSC_C23_C24_A 0x0336
#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3
#define regMPC_OUT3_CSC_C31_C32_A 0x0337
#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3
#define regMPC_OUT3_CSC_C33_C34_A 0x0338
#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3
#define regMPC_OUT3_CSC_C11_C12_B 0x0339
#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3
#define regMPC_OUT3_CSC_C13_C14_B 0x033a
#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3
#define regMPC_OUT3_CSC_C21_C22_B 0x033b
#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3
#define regMPC_OUT3_CSC_C23_C24_B 0x033c
#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3
#define regMPC_OUT3_CSC_C31_C32_B 0x033d
#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3
#define regMPC_OUT3_CSC_C33_C34_B 0x033e
#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3
#define regMPC_OCSC_TEST_DEBUG_INDEX 0x035b
#define regMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX 3
#define regMPC_OCSC_TEST_DEBUG_DATA 0x035c
#define regMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX 3
// addressBlock: dcn_dcec_opp_abm0_dispdec
// base address: 0x0
#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a
#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b
#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3
#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c
#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d
#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e
#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f
#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
#define regABM0_BL1_PWM_ABM_CNTL 0x0e80
#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3
#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81
#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
#define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82
#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
#define regABM0_DC_ABM1_CNTL 0x0e83
#define regABM0_DC_ABM1_CNTL_BASE_IDX 3
#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84
#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
#define regABM0_DC_ABM1_ACE_PWL_CNTL 0x0e85
#define regABM0_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0e86
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3
#define regABM0_DC_ABM1_ACE_THRES_DATA 0x0e87
#define regABM0_DC_ABM1_ACE_THRES_DATA_BASE_IDX 3
#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e88
#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8a
#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8b
#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e8c
#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e8d
#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e8e
#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e8f
#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e90
#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e91
#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e92
#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e93
#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e94
#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e95
#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
#define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0e96
#define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3
#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e97
#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e98
#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e99
#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9a
#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
#define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0e9b
#define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3
#define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0e9c
#define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3
#define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0e9d
#define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3
#define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0e9e
#define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3
#define regABM0_DC_ABM1_HG_RESULT_INDEX 0x0e9f
#define regABM0_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3
#define regABM0_DC_ABM1_HG_RESULT_DATA 0x0ea0
#define regABM0_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3
#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0ea1
#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
// addressBlock: dcn_dcec_opp_abm1_dispdec
// base address: 0x104
#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb
#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc
#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3
#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd
#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe
#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf
#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0
#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1
#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3
#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2
#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
#define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3
#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
#define regABM1_DC_ABM1_CNTL 0x0ec4
#define regABM1_DC_ABM1_CNTL_BASE_IDX 3
#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5
#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
#define regABM1_DC_ABM1_ACE_PWL_CNTL 0x0ec6
#define regABM1_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0ec7
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3
#define regABM1_DC_ABM1_ACE_THRES_DATA 0x0ec8
#define regABM1_DC_ABM1_ACE_THRES_DATA_BASE_IDX 3
#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ec9
#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecb
#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ecc
#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ecd
#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ece
#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ecf
#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed0
#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed1
#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed2
#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed3
#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed4
#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed5
#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0ed6
#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
#define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0ed7
#define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3
#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0ed8
#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0ed9
#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0eda
#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0edb
#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
#define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0edc
#define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3
#define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0edd
#define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3
#define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0ede
#define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3
#define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0edf
#define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3
#define regABM1_DC_ABM1_HG_RESULT_INDEX 0x0ee0
#define regABM1_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3
#define regABM1_DC_ABM1_HG_RESULT_DATA 0x0ee1
#define regABM1_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3
#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ee2
#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
// addressBlock: dcn_dcec_opp_abm2_dispdec
// base address: 0x208
#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc
#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
#define regABM2_BL1_PWM_USER_LEVEL 0x0efd
#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3
#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe
#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff
#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00
#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01
#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
#define regABM2_BL1_PWM_ABM_CNTL 0x0f02
#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3
#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03
#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
#define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04
#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
#define regABM2_DC_ABM1_CNTL 0x0f05
#define regABM2_DC_ABM1_CNTL_BASE_IDX 3
#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06
#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
#define regABM2_DC_ABM1_ACE_PWL_CNTL 0x0f07
#define regABM2_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0f08
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3
#define regABM2_DC_ABM1_ACE_THRES_DATA 0x0f09
#define regABM2_DC_ABM1_ACE_THRES_DATA_BASE_IDX 3
#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0a
#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f0c
#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f0d
#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f0e
#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f0f
#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f10
#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f11
#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f12
#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f13
#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f14
#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f15
#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f16
#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f17
#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
#define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0f18
#define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3
#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f19
#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1a
#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1b
#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1c
#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
#define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0f1d
#define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3
#define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0f1e
#define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3
#define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0f1f
#define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3
#define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0f20
#define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3
#define regABM2_DC_ABM1_HG_RESULT_INDEX 0x0f21
#define regABM2_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3
#define regABM2_DC_ABM1_HG_RESULT_DATA 0x0f22
#define regABM2_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3
#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f23
#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
// addressBlock: dcn_dcec_opp_abm3_dispdec
// base address: 0x30c
#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d
#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e
#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3
#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f
#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40
#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41
#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42
#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
#define regABM3_BL1_PWM_ABM_CNTL 0x0f43
#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3
#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44
#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
#define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45
#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
#define regABM3_DC_ABM1_CNTL 0x0f46
#define regABM3_DC_ABM1_CNTL_BASE_IDX 3
#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47
#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
#define regABM3_DC_ABM1_ACE_PWL_CNTL 0x0f48
#define regABM3_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0f49
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3
#define regABM3_DC_ABM1_ACE_THRES_DATA 0x0f4a
#define regABM3_DC_ABM1_ACE_THRES_DATA_BASE_IDX 3
#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4b
#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f4d
#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f4e
#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f4f
#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f50
#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f51
#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f52
#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f53
#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f54
#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f55
#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f56
#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f57
#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f58
#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
#define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0f59
#define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3
#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5a
#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5b
#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5c
#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f5d
#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
#define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0f5e
#define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3
#define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0f5f
#define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3
#define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0f60
#define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3
#define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0f61
#define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3
#define regABM3_DC_ABM1_HG_RESULT_INDEX 0x0f62
#define regABM3_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3
#define regABM3_DC_ABM1_HG_RESULT_DATA 0x0f63
#define regABM3_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3
#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f64
#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
// addressBlock: dcn_dcec_opp_dpg0_dispdec
// base address: 0x0
#define regDPG0_DPG_CONTROL 0x1854
#define regDPG0_DPG_CONTROL_BASE_IDX 2
#define regDPG0_DPG_RAMP_CONTROL 0x1855
#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2
#define regDPG0_DPG_DIMENSIONS 0x1856
#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2
#define regDPG0_DPG_COLOUR_R_CR 0x1857
#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2
#define regDPG0_DPG_COLOUR_G_Y 0x1858
#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2
#define regDPG0_DPG_COLOUR_B_CB 0x1859
#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2
#define regDPG0_DPG_OFFSET_SEGMENT 0x185a
#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define regDPG0_DPG_STATUS 0x185b
#define regDPG0_DPG_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_opp_fmt0_dispdec
// base address: 0x0
#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c
#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d
#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e
#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f
#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define regFMT0_FMT_CONTROL 0x1840
#define regFMT0_FMT_CONTROL_BASE_IDX 2
#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841
#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842
#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843
#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844
#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define regFMT0_FMT_CLAMP_CNTL 0x1845
#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846
#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847
#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define regFMT0_FMT_422_CONTROL 0x1849
#define regFMT0_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_opp_oppbuf0_dispdec
// base address: 0x0
#define regOPPBUF0_OPPBUF_CONTROL 0x1884
#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2
#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885
#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886
#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
#define regOPPBUF0_OPPBUF_CONTROL1 0x1889
#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2
// addressBlock: dcn_dcec_opp_opp_pipe0_dispdec
// base address: 0x0
#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c
#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_opp_opp_pipe_crc0_dispdec
// base address: 0x0
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dcn_dcec_opp_dpg1_dispdec
// base address: 0x168
#define regDPG1_DPG_CONTROL 0x18ae
#define regDPG1_DPG_CONTROL_BASE_IDX 2
#define regDPG1_DPG_RAMP_CONTROL 0x18af
#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2
#define regDPG1_DPG_DIMENSIONS 0x18b0
#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2
#define regDPG1_DPG_COLOUR_R_CR 0x18b1
#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2
#define regDPG1_DPG_COLOUR_G_Y 0x18b2
#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2
#define regDPG1_DPG_COLOUR_B_CB 0x18b3
#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2
#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4
#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define regDPG1_DPG_STATUS 0x18b5
#define regDPG1_DPG_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_opp_fmt1_dispdec
// base address: 0x168
#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896
#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897
#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898
#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899
#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define regFMT1_FMT_CONTROL 0x189a
#define regFMT1_FMT_CONTROL_BASE_IDX 2
#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b
#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c
#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d
#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e
#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define regFMT1_FMT_CLAMP_CNTL 0x189f
#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0
#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1
#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define regFMT1_FMT_422_CONTROL 0x18a3
#define regFMT1_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_opp_oppbuf1_dispdec
// base address: 0x168
#define regOPPBUF1_OPPBUF_CONTROL 0x18de
#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2
#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df
#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0
#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3
#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2
// addressBlock: dcn_dcec_opp_opp_pipe1_dispdec
// base address: 0x168
#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6
#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_opp_opp_pipe_crc1_dispdec
// base address: 0x168
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dcn_dcec_opp_dpg2_dispdec
// base address: 0x2d0
#define regDPG2_DPG_CONTROL 0x1908
#define regDPG2_DPG_CONTROL_BASE_IDX 2
#define regDPG2_DPG_RAMP_CONTROL 0x1909
#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2
#define regDPG2_DPG_DIMENSIONS 0x190a
#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2
#define regDPG2_DPG_COLOUR_R_CR 0x190b
#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2
#define regDPG2_DPG_COLOUR_G_Y 0x190c
#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2
#define regDPG2_DPG_COLOUR_B_CB 0x190d
#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2
#define regDPG2_DPG_OFFSET_SEGMENT 0x190e
#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define regDPG2_DPG_STATUS 0x190f
#define regDPG2_DPG_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_opp_fmt2_dispdec
// base address: 0x2d0
#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0
#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1
#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2
#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3
#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define regFMT2_FMT_CONTROL 0x18f4
#define regFMT2_FMT_CONTROL_BASE_IDX 2
#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5
#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6
#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7
#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8
#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define regFMT2_FMT_CLAMP_CNTL 0x18f9
#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa
#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb
#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define regFMT2_FMT_422_CONTROL 0x18fd
#define regFMT2_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_opp_oppbuf2_dispdec
// base address: 0x2d0
#define regOPPBUF2_OPPBUF_CONTROL 0x1938
#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2
#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939
#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a
#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
#define regOPPBUF2_OPPBUF_CONTROL1 0x193d
#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2
// addressBlock: dcn_dcec_opp_opp_pipe2_dispdec
// base address: 0x2d0
#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940
#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_opp_opp_pipe_crc2_dispdec
// base address: 0x2d0
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dcn_dcec_opp_dpg3_dispdec
// base address: 0x438
#define regDPG3_DPG_CONTROL 0x1962
#define regDPG3_DPG_CONTROL_BASE_IDX 2
#define regDPG3_DPG_RAMP_CONTROL 0x1963
#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2
#define regDPG3_DPG_DIMENSIONS 0x1964
#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2
#define regDPG3_DPG_COLOUR_R_CR 0x1965
#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2
#define regDPG3_DPG_COLOUR_G_Y 0x1966
#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2
#define regDPG3_DPG_COLOUR_B_CB 0x1967
#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2
#define regDPG3_DPG_OFFSET_SEGMENT 0x1968
#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define regDPG3_DPG_STATUS 0x1969
#define regDPG3_DPG_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_opp_fmt3_dispdec
// base address: 0x438
#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a
#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b
#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c
#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d
#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define regFMT3_FMT_CONTROL 0x194e
#define regFMT3_FMT_CONTROL_BASE_IDX 2
#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f
#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950
#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951
#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952
#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define regFMT3_FMT_CLAMP_CNTL 0x1953
#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954
#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955
#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define regFMT3_FMT_422_CONTROL 0x1957
#define regFMT3_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_opp_oppbuf3_dispdec
// base address: 0x438
#define regOPPBUF3_OPPBUF_CONTROL 0x1992
#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2
#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993
#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994
#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
#define regOPPBUF3_OPPBUF_CONTROL1 0x1997
#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2
// addressBlock: dcn_dcec_opp_opp_pipe3_dispdec
// base address: 0x438
#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a
#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_opp_opp_pipe_crc3_dispdec
// base address: 0x438
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dcn_dcec_opp_dscrm0_dispdec
// base address: 0x0
#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64
#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
// addressBlock: dcn_dcec_opp_dscrm1_dispdec
// base address: 0x4
#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65
#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
// addressBlock: dcn_dcec_opp_dscrm2_dispdec
// base address: 0x8
#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66
#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
// addressBlock: dcn_dcec_opp_dscrm3_dispdec
// base address: 0xc
#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67
#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
// addressBlock: dcn_dcec_opp_opp_top_dispdec
// base address: 0x0
#define regOPP_TOP_CLK_CONTROL 0x1a5e
#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2
#define regOPP_ABM_CONTROL 0x1a60
#define regOPP_ABM_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_optc_odm0_dispdec
// base address: 0x0
#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca
#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb
#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc
#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd
#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define regODM0_OPTC_WIDTH_CONTROL 0x1ace
#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define regODM0_OPTC_WIDTH_CONTROL2 0x1acf
#define regODM0_OPTC_WIDTH_CONTROL2_BASE_IDX 2
#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1ad0
#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define regODM0_OPTC_MEMORY_CONFIG 0x1ad1
#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad2
#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dcn_dcec_optc_odm1_dispdec
// base address: 0x40
#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada
#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb
#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc
#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define regODM1_OPTC_BYTES_PER_PIXEL 0x1add
#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define regODM1_OPTC_WIDTH_CONTROL 0x1ade
#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define regODM1_OPTC_WIDTH_CONTROL2 0x1adf
#define regODM1_OPTC_WIDTH_CONTROL2_BASE_IDX 2
#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1ae0
#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define regODM1_OPTC_MEMORY_CONFIG 0x1ae1
#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae2
#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dcn_dcec_optc_odm2_dispdec
// base address: 0x80
#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea
#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb
#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec
#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed
#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define regODM2_OPTC_WIDTH_CONTROL 0x1aee
#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define regODM2_OPTC_WIDTH_CONTROL2 0x1aef
#define regODM2_OPTC_WIDTH_CONTROL2_BASE_IDX 2
#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1af0
#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define regODM2_OPTC_MEMORY_CONFIG 0x1af1
#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af2
#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dcn_dcec_optc_odm3_dispdec
// base address: 0xc0
#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa
#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb
#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc
#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd
#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define regODM3_OPTC_WIDTH_CONTROL 0x1afe
#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define regODM3_OPTC_WIDTH_CONTROL2 0x1aff
#define regODM3_OPTC_WIDTH_CONTROL2_BASE_IDX 2
#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1b00
#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define regODM3_OPTC_MEMORY_CONFIG 0x1b01
#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b02
#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dcn_dcec_optc_otg0_dispdec
// base address: 0x0
#define regOTG0_OTG_H_TOTAL 0x1b2a
#define regOTG0_OTG_H_TOTAL_BASE_IDX 2
#define regOTG0_OTG_H_BLANK_START_END 0x1b2b
#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2
#define regOTG0_OTG_H_SYNC_A 0x1b2c
#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2
#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d
#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e
#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2
#define regOTG0_OTG_V_TOTAL 0x1b2f
#define regOTG0_OTG_V_TOTAL_BASE_IDX 2
#define regOTG0_OTG_V_TOTAL_MIN 0x1b30
#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2
#define regOTG0_OTG_V_TOTAL_MAX 0x1b31
#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2
#define regOTG0_OTG_V_TOTAL_MID 0x1b32
#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2
#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33
#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define regOTG0_OTG_V_COUNT_STOP_CONTROL 0x1b34
#define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2
#define regOTG0_OTG_V_COUNT_STOP_CONTROL2 0x1b35
#define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2
#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b36
#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b37
#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define regOTG0_OTG_V_BLANK_START_END 0x1b38
#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2
#define regOTG0_OTG_V_SYNC_A 0x1b39
#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2
#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b3a
#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define regOTG0_OTG_TRIGA_CNTL 0x1b3b
#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2
#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3c
#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define regOTG0_OTG_TRIGB_CNTL 0x1b3d
#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2
#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3e
#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3f
#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define regOTG0_OTG_FLOW_CONTROL 0x1b40
#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2
#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b41
#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define regOTG0_OTG_CONTROL 0x1b43
#define regOTG0_OTG_CONTROL_BASE_IDX 2
#define regOTG0_OTG_DLPC_CONTROL 0x1b44
#define regOTG0_OTG_DLPC_CONTROL_BASE_IDX 2
#define regOTG0_OTG_INTERLACE_CONTROL 0x1b45
#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define regOTG0_OTG_INTERLACE_STATUS 0x1b46
#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2
#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47
#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48
#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define regOTG0_OTG_STATUS 0x1b49
#define regOTG0_OTG_STATUS_BASE_IDX 2
#define regOTG0_OTG_STATUS_POSITION 0x1b4a
#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2
#define regOTG0_OTG_LONG_VBLANK_STATUS 0x1b4b
#define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX 2
#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4c
#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4d
#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4e
#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define regOTG0_OTG_STATUS_HV_COUNT 0x1b4f
#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define regOTG0_OTG_COUNT_CONTROL 0x1b50
#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2
#define regOTG0_OTG_COUNT_RESET 0x1b51
#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2
#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b52
#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b53
#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define regOTG0_OTG_STEREO_STATUS 0x1b54
#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2
#define regOTG0_OTG_STEREO_CONTROL 0x1b55
#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2
#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b56
#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b57
#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b58
#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b59
#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b5a
#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define regOTG0_OTG_UPDATE_LOCK 0x1b5b
#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2
#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5c
#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regOTG0_OTG_MASTER_EN 0x1b5d
#define regOTG0_OTG_MASTER_EN_BASE_IDX 2
#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b5f
#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b60
#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b61
#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b62
#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b63
#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b64
#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define regOTG0_OTG_CRC_CNTL 0x1b65
#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2
#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b66
#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b67
#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b68
#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b69
#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define regOTG0_OTG_CRC0_DATA_RG 0x1b6a
#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2
#define regOTG0_OTG_CRC0_DATA_B 0x1b6b
#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2
#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6c
#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b6d
#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b6e
#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b6f
#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define regOTG0_OTG_CRC1_DATA_RG 0x1b70
#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2
#define regOTG0_OTG_CRC1_DATA_B 0x1b71
#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2
#define regOTG0_OTG_CRC2_DATA_RG 0x1b72
#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2
#define regOTG0_OTG_CRC2_DATA_B 0x1b73
#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2
#define regOTG0_OTG_CRC3_DATA_RG 0x1b74
#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2
#define regOTG0_OTG_CRC3_DATA_B 0x1b75
#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2
#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b76
#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b77
#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1b78
#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1b79
#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1b7a
#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1b7b
#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1b7c
#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1b7d
#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1b7e
#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1b7f
#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b80
#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b81
#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b82
#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b83
#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define regOTG0_OTG_CLOCK_CONTROL 0x1b84
#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2
#define regOTG0_OTG_VSTARTUP_PARAM 0x1b85
#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define regOTG0_OTG_VUPDATE_PARAM 0x1b86
#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2
#define regOTG0_OTG_VREADY_PARAM 0x1b87
#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2
#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b88
#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b89
#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define regOTG0_OTG_GSL_CONTROL 0x1b8a
#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2
#define regOTG0_OTG_GSL_WINDOW_X 0x1b8b
#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2
#define regOTG0_OTG_GSL_WINDOW_Y 0x1b8c
#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8d
#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b8e
#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b8f
#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b90
#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b91
#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b92
#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2
#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b93
#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b94
#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b95
#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b96
#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b97
#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b98
#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
#define regOTG0_OTG_DRR_CONTROL 0x1b99
#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2
#define regOTG0_OTG_DRR_CONTOL2 0x1b9a
#define regOTG0_OTG_DRR_CONTOL2_BASE_IDX 2
#define regOTG0_OTG_M_CONST_DTO0 0x1b9b
#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2
#define regOTG0_OTG_M_CONST_DTO1 0x1b9c
#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2
#define regOTG0_OTG_REQUEST_CONTROL 0x1b9d
#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2
#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9e
#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
#define regOTG0_OTG_PSTATE_REGISTER 0x1b9f
#define regOTG0_OTG_PSTATE_REGISTER_BASE_IDX 2
#define regOTG0_OTG_SPARE_REGISTER 0x1ba1
#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dcn_dcec_optc_otg1_dispdec
// base address: 0x200
#define regOTG1_OTG_H_TOTAL 0x1baa
#define regOTG1_OTG_H_TOTAL_BASE_IDX 2
#define regOTG1_OTG_H_BLANK_START_END 0x1bab
#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2
#define regOTG1_OTG_H_SYNC_A 0x1bac
#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2
#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad
#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define regOTG1_OTG_H_TIMING_CNTL 0x1bae
#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2
#define regOTG1_OTG_V_TOTAL 0x1baf
#define regOTG1_OTG_V_TOTAL_BASE_IDX 2
#define regOTG1_OTG_V_TOTAL_MIN 0x1bb0
#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2
#define regOTG1_OTG_V_TOTAL_MAX 0x1bb1
#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2
#define regOTG1_OTG_V_TOTAL_MID 0x1bb2
#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2
#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3
#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define regOTG1_OTG_V_COUNT_STOP_CONTROL 0x1bb4
#define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2
#define regOTG1_OTG_V_COUNT_STOP_CONTROL2 0x1bb5
#define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2
#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb6
#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb7
#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define regOTG1_OTG_V_BLANK_START_END 0x1bb8
#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2
#define regOTG1_OTG_V_SYNC_A 0x1bb9
#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2
#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bba
#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define regOTG1_OTG_TRIGA_CNTL 0x1bbb
#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2
#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bbc
#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define regOTG1_OTG_TRIGB_CNTL 0x1bbd
#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2
#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbe
#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbf
#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define regOTG1_OTG_FLOW_CONTROL 0x1bc0
#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2
#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bc1
#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define regOTG1_OTG_CONTROL 0x1bc3
#define regOTG1_OTG_CONTROL_BASE_IDX 2
#define regOTG1_OTG_DLPC_CONTROL 0x1bc4
#define regOTG1_OTG_DLPC_CONTROL_BASE_IDX 2
#define regOTG1_OTG_INTERLACE_CONTROL 0x1bc5
#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define regOTG1_OTG_INTERLACE_STATUS 0x1bc6
#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2
#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7
#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8
#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define regOTG1_OTG_STATUS 0x1bc9
#define regOTG1_OTG_STATUS_BASE_IDX 2
#define regOTG1_OTG_STATUS_POSITION 0x1bca
#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2
#define regOTG1_OTG_LONG_VBLANK_STATUS 0x1bcb
#define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX 2
#define regOTG1_OTG_NOM_VERT_POSITION 0x1bcc
#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcd
#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define regOTG1_OTG_STATUS_VF_COUNT 0x1bce
#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define regOTG1_OTG_STATUS_HV_COUNT 0x1bcf
#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define regOTG1_OTG_COUNT_CONTROL 0x1bd0
#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2
#define regOTG1_OTG_COUNT_RESET 0x1bd1
#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2
#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd2
#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd3
#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define regOTG1_OTG_STEREO_STATUS 0x1bd4
#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2
#define regOTG1_OTG_STEREO_CONTROL 0x1bd5
#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2
#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd6
#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd7
#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd8
#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd9
#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define regOTG1_OTG_INTERRUPT_CONTROL 0x1bda
#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define regOTG1_OTG_UPDATE_LOCK 0x1bdb
#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2
#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdc
#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regOTG1_OTG_MASTER_EN 0x1bdd
#define regOTG1_OTG_MASTER_EN_BASE_IDX 2
#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1bdf
#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be0
#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be1
#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be2
#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be3
#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be4
#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define regOTG1_OTG_CRC_CNTL 0x1be5
#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2
#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1be6
#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1be7
#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1be8
#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1be9
#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define regOTG1_OTG_CRC0_DATA_RG 0x1bea
#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2
#define regOTG1_OTG_CRC0_DATA_B 0x1beb
#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2
#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bec
#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bed
#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bee
#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bef
#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define regOTG1_OTG_CRC1_DATA_RG 0x1bf0
#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2
#define regOTG1_OTG_CRC1_DATA_B 0x1bf1
#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2
#define regOTG1_OTG_CRC2_DATA_RG 0x1bf2
#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2
#define regOTG1_OTG_CRC2_DATA_B 0x1bf3
#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2
#define regOTG1_OTG_CRC3_DATA_RG 0x1bf4
#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2
#define regOTG1_OTG_CRC3_DATA_B 0x1bf5
#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2
#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bf6
#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bf7
#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1bf8
#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1bf9
#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1bfa
#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1bfb
#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1bfc
#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1bfd
#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1bfe
#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1bff
#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c00
#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c01
#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c02
#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c03
#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define regOTG1_OTG_CLOCK_CONTROL 0x1c04
#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2
#define regOTG1_OTG_VSTARTUP_PARAM 0x1c05
#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define regOTG1_OTG_VUPDATE_PARAM 0x1c06
#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2
#define regOTG1_OTG_VREADY_PARAM 0x1c07
#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2
#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c08
#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c09
#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define regOTG1_OTG_GSL_CONTROL 0x1c0a
#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2
#define regOTG1_OTG_GSL_WINDOW_X 0x1c0b
#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2
#define regOTG1_OTG_GSL_WINDOW_Y 0x1c0c
#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0d
#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c0e
#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c0f
#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c10
#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c11
#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c12
#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2
#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c13
#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c14
#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c15
#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c16
#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c17
#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c18
#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
#define regOTG1_OTG_DRR_CONTROL 0x1c19
#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2
#define regOTG1_OTG_DRR_CONTOL2 0x1c1a
#define regOTG1_OTG_DRR_CONTOL2_BASE_IDX 2
#define regOTG1_OTG_M_CONST_DTO0 0x1c1b
#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2
#define regOTG1_OTG_M_CONST_DTO1 0x1c1c
#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2
#define regOTG1_OTG_REQUEST_CONTROL 0x1c1d
#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2
#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1e
#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
#define regOTG1_OTG_PSTATE_REGISTER 0x1c1f
#define regOTG1_OTG_PSTATE_REGISTER_BASE_IDX 2
#define regOTG1_OTG_SPARE_REGISTER 0x1c21
#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dcn_dcec_optc_otg2_dispdec
// base address: 0x400
#define regOTG2_OTG_H_TOTAL 0x1c2a
#define regOTG2_OTG_H_TOTAL_BASE_IDX 2
#define regOTG2_OTG_H_BLANK_START_END 0x1c2b
#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2
#define regOTG2_OTG_H_SYNC_A 0x1c2c
#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2
#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d
#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define regOTG2_OTG_H_TIMING_CNTL 0x1c2e
#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2
#define regOTG2_OTG_V_TOTAL 0x1c2f
#define regOTG2_OTG_V_TOTAL_BASE_IDX 2
#define regOTG2_OTG_V_TOTAL_MIN 0x1c30
#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2
#define regOTG2_OTG_V_TOTAL_MAX 0x1c31
#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2
#define regOTG2_OTG_V_TOTAL_MID 0x1c32
#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2
#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33
#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define regOTG2_OTG_V_COUNT_STOP_CONTROL 0x1c34
#define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2
#define regOTG2_OTG_V_COUNT_STOP_CONTROL2 0x1c35
#define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2
#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c36
#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c37
#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define regOTG2_OTG_V_BLANK_START_END 0x1c38
#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2
#define regOTG2_OTG_V_SYNC_A 0x1c39
#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2
#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c3a
#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define regOTG2_OTG_TRIGA_CNTL 0x1c3b
#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2
#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3c
#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define regOTG2_OTG_TRIGB_CNTL 0x1c3d
#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2
#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3e
#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3f
#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define regOTG2_OTG_FLOW_CONTROL 0x1c40
#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2
#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c41
#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define regOTG2_OTG_CONTROL 0x1c43
#define regOTG2_OTG_CONTROL_BASE_IDX 2
#define regOTG2_OTG_DLPC_CONTROL 0x1c44
#define regOTG2_OTG_DLPC_CONTROL_BASE_IDX 2
#define regOTG2_OTG_INTERLACE_CONTROL 0x1c45
#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define regOTG2_OTG_INTERLACE_STATUS 0x1c46
#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2
#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47
#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48
#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define regOTG2_OTG_STATUS 0x1c49
#define regOTG2_OTG_STATUS_BASE_IDX 2
#define regOTG2_OTG_STATUS_POSITION 0x1c4a
#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2
#define regOTG2_OTG_LONG_VBLANK_STATUS 0x1c4b
#define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX 2
#define regOTG2_OTG_NOM_VERT_POSITION 0x1c4c
#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4d
#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define regOTG2_OTG_STATUS_VF_COUNT 0x1c4e
#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define regOTG2_OTG_STATUS_HV_COUNT 0x1c4f
#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define regOTG2_OTG_COUNT_CONTROL 0x1c50
#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2
#define regOTG2_OTG_COUNT_RESET 0x1c51
#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2
#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c52
#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c53
#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define regOTG2_OTG_STEREO_STATUS 0x1c54
#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2
#define regOTG2_OTG_STEREO_CONTROL 0x1c55
#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2
#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c56
#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c57
#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c58
#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c59
#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c5a
#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define regOTG2_OTG_UPDATE_LOCK 0x1c5b
#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2
#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5c
#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regOTG2_OTG_MASTER_EN 0x1c5d
#define regOTG2_OTG_MASTER_EN_BASE_IDX 2
#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c5f
#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c60
#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c61
#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c62
#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c63
#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c64
#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define regOTG2_OTG_CRC_CNTL 0x1c65
#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2
#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c66
#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c67
#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c68
#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c69
#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define regOTG2_OTG_CRC0_DATA_RG 0x1c6a
#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2
#define regOTG2_OTG_CRC0_DATA_B 0x1c6b
#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2
#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c6c
#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c6d
#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c6e
#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c6f
#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define regOTG2_OTG_CRC1_DATA_RG 0x1c70
#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2
#define regOTG2_OTG_CRC1_DATA_B 0x1c71
#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2
#define regOTG2_OTG_CRC2_DATA_RG 0x1c72
#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2
#define regOTG2_OTG_CRC2_DATA_B 0x1c73
#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2
#define regOTG2_OTG_CRC3_DATA_RG 0x1c74
#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2
#define regOTG2_OTG_CRC3_DATA_B 0x1c75
#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2
#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c76
#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c77
#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1c78
#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1c79
#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1c7a
#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1c7b
#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1c7c
#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1c7d
#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1c7e
#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1c7f
#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c80
#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c81
#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c82
#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c83
#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define regOTG2_OTG_CLOCK_CONTROL 0x1c84
#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2
#define regOTG2_OTG_VSTARTUP_PARAM 0x1c85
#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define regOTG2_OTG_VUPDATE_PARAM 0x1c86
#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2
#define regOTG2_OTG_VREADY_PARAM 0x1c87
#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2
#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c88
#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c89
#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define regOTG2_OTG_GSL_CONTROL 0x1c8a
#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2
#define regOTG2_OTG_GSL_WINDOW_X 0x1c8b
#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2
#define regOTG2_OTG_GSL_WINDOW_Y 0x1c8c
#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8d
#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define regOTG2_OTG_GLOBAL_CONTROL0 0x1c8e
#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define regOTG2_OTG_GLOBAL_CONTROL1 0x1c8f
#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define regOTG2_OTG_GLOBAL_CONTROL2 0x1c90
#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define regOTG2_OTG_GLOBAL_CONTROL3 0x1c91
#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define regOTG2_OTG_GLOBAL_CONTROL4 0x1c92
#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2
#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c93
#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c94
#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c95
#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c96
#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c97
#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c98
#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
#define regOTG2_OTG_DRR_CONTROL 0x1c99
#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2
#define regOTG2_OTG_DRR_CONTOL2 0x1c9a
#define regOTG2_OTG_DRR_CONTOL2_BASE_IDX 2
#define regOTG2_OTG_M_CONST_DTO0 0x1c9b
#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2
#define regOTG2_OTG_M_CONST_DTO1 0x1c9c
#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2
#define regOTG2_OTG_REQUEST_CONTROL 0x1c9d
#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2
#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9e
#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
#define regOTG2_OTG_PSTATE_REGISTER 0x1c9f
#define regOTG2_OTG_PSTATE_REGISTER_BASE_IDX 2
#define regOTG2_OTG_SPARE_REGISTER 0x1ca1
#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dcn_dcec_optc_otg3_dispdec
// base address: 0x600
#define regOTG3_OTG_H_TOTAL 0x1caa
#define regOTG3_OTG_H_TOTAL_BASE_IDX 2
#define regOTG3_OTG_H_BLANK_START_END 0x1cab
#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2
#define regOTG3_OTG_H_SYNC_A 0x1cac
#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2
#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad
#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define regOTG3_OTG_H_TIMING_CNTL 0x1cae
#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2
#define regOTG3_OTG_V_TOTAL 0x1caf
#define regOTG3_OTG_V_TOTAL_BASE_IDX 2
#define regOTG3_OTG_V_TOTAL_MIN 0x1cb0
#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2
#define regOTG3_OTG_V_TOTAL_MAX 0x1cb1
#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2
#define regOTG3_OTG_V_TOTAL_MID 0x1cb2
#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2
#define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3
#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define regOTG3_OTG_V_COUNT_STOP_CONTROL 0x1cb4
#define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2
#define regOTG3_OTG_V_COUNT_STOP_CONTROL2 0x1cb5
#define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2
#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb6
#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb7
#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define regOTG3_OTG_V_BLANK_START_END 0x1cb8
#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2
#define regOTG3_OTG_V_SYNC_A 0x1cb9
#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2
#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cba
#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define regOTG3_OTG_TRIGA_CNTL 0x1cbb
#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2
#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cbc
#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define regOTG3_OTG_TRIGB_CNTL 0x1cbd
#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2
#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbe
#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbf
#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define regOTG3_OTG_FLOW_CONTROL 0x1cc0
#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2
#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cc1
#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define regOTG3_OTG_CONTROL 0x1cc3
#define regOTG3_OTG_CONTROL_BASE_IDX 2
#define regOTG3_OTG_DLPC_CONTROL 0x1cc4
#define regOTG3_OTG_DLPC_CONTROL_BASE_IDX 2
#define regOTG3_OTG_INTERLACE_CONTROL 0x1cc5
#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define regOTG3_OTG_INTERLACE_STATUS 0x1cc6
#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2
#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7
#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8
#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define regOTG3_OTG_STATUS 0x1cc9
#define regOTG3_OTG_STATUS_BASE_IDX 2
#define regOTG3_OTG_STATUS_POSITION 0x1cca
#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2
#define regOTG3_OTG_LONG_VBLANK_STATUS 0x1ccb
#define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX 2
#define regOTG3_OTG_NOM_VERT_POSITION 0x1ccc
#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccd
#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define regOTG3_OTG_STATUS_VF_COUNT 0x1cce
#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define regOTG3_OTG_STATUS_HV_COUNT 0x1ccf
#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define regOTG3_OTG_COUNT_CONTROL 0x1cd0
#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2
#define regOTG3_OTG_COUNT_RESET 0x1cd1
#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2
#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd2
#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd3
#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define regOTG3_OTG_STEREO_STATUS 0x1cd4
#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2
#define regOTG3_OTG_STEREO_CONTROL 0x1cd5
#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2
#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd6
#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd7
#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd8
#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd9
#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cda
#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define regOTG3_OTG_UPDATE_LOCK 0x1cdb
#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2
#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdc
#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regOTG3_OTG_MASTER_EN 0x1cdd
#define regOTG3_OTG_MASTER_EN_BASE_IDX 2
#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1cdf
#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce0
#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce1
#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce2
#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce3
#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce4
#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define regOTG3_OTG_CRC_CNTL 0x1ce5
#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2
#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1ce6
#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ce7
#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1ce8
#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ce9
#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define regOTG3_OTG_CRC0_DATA_RG 0x1cea
#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2
#define regOTG3_OTG_CRC0_DATA_B 0x1ceb
#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2
#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cec
#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1ced
#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cee
#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cef
#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define regOTG3_OTG_CRC1_DATA_RG 0x1cf0
#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2
#define regOTG3_OTG_CRC1_DATA_B 0x1cf1
#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2
#define regOTG3_OTG_CRC2_DATA_RG 0x1cf2
#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2
#define regOTG3_OTG_CRC2_DATA_B 0x1cf3
#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2
#define regOTG3_OTG_CRC3_DATA_RG 0x1cf4
#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2
#define regOTG3_OTG_CRC3_DATA_B 0x1cf5
#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2
#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cf6
#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cf7
#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1cf8
#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1cf9
#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1cfa
#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1cfb
#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1cfc
#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1cfd
#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1cfe
#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2
#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1cff
#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2
#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d00
#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d01
#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d02
#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d03
#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define regOTG3_OTG_CLOCK_CONTROL 0x1d04
#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2
#define regOTG3_OTG_VSTARTUP_PARAM 0x1d05
#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define regOTG3_OTG_VUPDATE_PARAM 0x1d06
#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2
#define regOTG3_OTG_VREADY_PARAM 0x1d07
#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2
#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d08
#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d09
#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define regOTG3_OTG_GSL_CONTROL 0x1d0a
#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2
#define regOTG3_OTG_GSL_WINDOW_X 0x1d0b
#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2
#define regOTG3_OTG_GSL_WINDOW_Y 0x1d0c
#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0d
#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d0e
#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d0f
#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d10
#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d11
#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d12
#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2
#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d13
#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d14
#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d15
#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d16
#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d17
#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d18
#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
#define regOTG3_OTG_DRR_CONTROL 0x1d19
#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2
#define regOTG3_OTG_DRR_CONTOL2 0x1d1a
#define regOTG3_OTG_DRR_CONTOL2_BASE_IDX 2
#define regOTG3_OTG_M_CONST_DTO0 0x1d1b
#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2
#define regOTG3_OTG_M_CONST_DTO1 0x1d1c
#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2
#define regOTG3_OTG_REQUEST_CONTROL 0x1d1d
#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2
#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1e
#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
#define regOTG3_OTG_PSTATE_REGISTER 0x1d1f
#define regOTG3_OTG_PSTATE_REGISTER_BASE_IDX 2
#define regOTG3_OTG_SPARE_REGISTER 0x1d21
#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dcn_dcec_optc_optc_misc_dispdec
// base address: 0x0
#define regGSL_SOURCE_SELECT 0x1e2b
#define regGSL_SOURCE_SELECT_BASE_IDX 2
#define regOPTC_DLPC_CONTROL 0x1e2c
#define regOPTC_DLPC_CONTROL_BASE_IDX 2
#define regOPTC_CLOCK_CONTROL 0x1e2d
#define regOPTC_CLOCK_CONTROL_BASE_IDX 2
#define regODM_MEM_PWR_CTRL 0x1e2e
#define regODM_MEM_PWR_CTRL_BASE_IDX 2
#define regODM_MEM_PWR_CTRL2 0x1e2f
#define regODM_MEM_PWR_CTRL2_BASE_IDX 2
#define regODM_MEM_PWR_CTRL3 0x1e30
#define regODM_MEM_PWR_CTRL3_BASE_IDX 2
#define regODM_MEM_PWR_STATUS 0x1e31
#define regODM_MEM_PWR_STATUS_BASE_IDX 2
#define regOPTC_MISC_SPARE_REGISTER 0x1e32
#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dp0_dispdec
// base address: 0x0
#define regDP0_DP_LINK_CNTL 0x211e
#define regDP0_DP_LINK_CNTL_BASE_IDX 2
#define regDP0_DP_PIXEL_FORMAT 0x211f
#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2
#define regDP0_DP_MSA_COLORIMETRY 0x2120
#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
#define regDP0_DP_CONFIG 0x2121
#define regDP0_DP_CONFIG_BASE_IDX 2
#define regDP0_DP_VID_STREAM_CNTL 0x2122
#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
#define regDP0_DP_STEER_FIFO 0x2123
#define regDP0_DP_STEER_FIFO_BASE_IDX 2
#define regDP0_DP_MSA_MISC 0x2124
#define regDP0_DP_MSA_MISC_BASE_IDX 2
#define regDP0_DP_DPHY_INTERNAL_CTRL 0x2125
#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
#define regDP0_DP_VID_TIMING 0x2126
#define regDP0_DP_VID_TIMING_BASE_IDX 2
#define regDP0_DP_VID_N 0x2127
#define regDP0_DP_VID_N_BASE_IDX 2
#define regDP0_DP_VID_M 0x2128
#define regDP0_DP_VID_M_BASE_IDX 2
#define regDP0_DP_LINK_FRAMING_CNTL 0x2129
#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define regDP0_DP_HBR2_EYE_PATTERN 0x212a
#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define regDP0_DP_VID_MSA_VBID 0x212b
#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2
#define regDP0_DP_VID_INTERRUPT_CNTL 0x212c
#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define regDP0_DP_DPHY_CNTL 0x212d
#define regDP0_DP_DPHY_CNTL_BASE_IDX 2
#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x212e
#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define regDP0_DP_DPHY_SYM0 0x212f
#define regDP0_DP_DPHY_SYM0_BASE_IDX 2
#define regDP0_DP_DPHY_SYM1 0x2130
#define regDP0_DP_DPHY_SYM1_BASE_IDX 2
#define regDP0_DP_DPHY_SYM2 0x2131
#define regDP0_DP_DPHY_SYM2_BASE_IDX 2
#define regDP0_DP_DPHY_8B10B_CNTL 0x2132
#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define regDP0_DP_DPHY_PRBS_CNTL 0x2133
#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define regDP0_DP_DPHY_SCRAM_CNTL 0x2134
#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define regDP0_DP_DPHY_CRC_EN 0x2135
#define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2
#define regDP0_DP_DPHY_CRC_CNTL 0x2136
#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define regDP0_DP_DPHY_CRC_RESULT 0x2137
#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define regDP0_DP_DPHY_CRC_MST_CNTL 0x2138
#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define regDP0_DP_DPHY_CRC_MST_STATUS 0x2139
#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define regDP0_DP_DPHY_FAST_TRAINING 0x213a
#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x213b
#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define regDP0_DP_TU_CNTL 0x213c
#define regDP0_DP_TU_CNTL_BASE_IDX 2
#define regDP0_DP_PIXEL_FORMAT_DB_CNTL 0x213d
#define regDP0_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2
#define regDP0_DP_CP_LINK_VERIFICATION_PATTERN 0x213e
#define regDP0_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX 2
#define regDP0_DP_SEC_CNTL 0x2141
#define regDP0_DP_SEC_CNTL_BASE_IDX 2
#define regDP0_DP_SEC_CNTL1 0x2142
#define regDP0_DP_SEC_CNTL1_BASE_IDX 2
#define regDP0_DP_SEC_FRAMING1 0x2143
#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2
#define regDP0_DP_SEC_FRAMING2 0x2144
#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2
#define regDP0_DP_SEC_FRAMING3 0x2145
#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2
#define regDP0_DP_SEC_FRAMING4 0x2146
#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2
#define regDP0_DP_SEC_AUD_N 0x2147
#define regDP0_DP_SEC_AUD_N_BASE_IDX 2
#define regDP0_DP_SEC_AUD_N_READBACK 0x2148
#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define regDP0_DP_SEC_AUD_M 0x2149
#define regDP0_DP_SEC_AUD_M_BASE_IDX 2
#define regDP0_DP_SEC_AUD_M_READBACK 0x214a
#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define regDP0_DP_SEC_TIMESTAMP 0x214b
#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
#define regDP0_DP_SEC_PACKET_CNTL 0x214c
#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define regDP0_DP_MSE_RATE_CNTL 0x214d
#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
#define regDP0_DP_CP_MSE_STATUS 0x214e
#define regDP0_DP_CP_MSE_STATUS_BASE_IDX 2
#define regDP0_DP_MSE_RATE_UPDATE 0x214f
#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define regDP0_DP_MSE_SAT0 0x2150
#define regDP0_DP_MSE_SAT0_BASE_IDX 2
#define regDP0_DP_MSE_SAT1 0x2151
#define regDP0_DP_MSE_SAT1_BASE_IDX 2
#define regDP0_DP_MSE_SAT2 0x2152
#define regDP0_DP_MSE_SAT2_BASE_IDX 2
#define regDP0_DP_MSE_SAT_UPDATE 0x2153
#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define regDP0_DP_MSE_LINK_TIMING 0x2154
#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
#define regDP0_DP_MSE_MISC_CNTL 0x2155
#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x215a
#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x215b
#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define regDP0_DP_MSE_SAT0_STATUS 0x215d
#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define regDP0_DP_MSE_SAT1_STATUS 0x215e
#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define regDP0_DP_MSE_SAT2_STATUS 0x215f
#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define regDP0_DP_DPIA_SPARE 0x2160
#define regDP0_DP_DPIA_SPARE_BASE_IDX 2
#define regDP0_DP_HBLANK_CONTROL 0x2161
#define regDP0_DP_HBLANK_CONTROL_BASE_IDX 2
#define regDP0_DP_MSA_TIMING_PARAM1 0x2162
#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define regDP0_DP_MSA_TIMING_PARAM2 0x2163
#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define regDP0_DP_MSA_TIMING_PARAM3 0x2164
#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define regDP0_DP_MSA_TIMING_PARAM4 0x2165
#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define regDP0_DP_MSO_CNTL 0x2166
#define regDP0_DP_MSO_CNTL_BASE_IDX 2
#define regDP0_DP_MSO_CNTL1 0x2167
#define regDP0_DP_MSO_CNTL1_BASE_IDX 2
#define regDP0_DP_STEER_FIFO_CNTL 0x2168
#define regDP0_DP_STEER_FIFO_CNTL_BASE_IDX 2
#define regDP0_DP_SEC_CNTL2 0x2169
#define regDP0_DP_SEC_CNTL2_BASE_IDX 2
#define regDP0_DP_SEC_CNTL3 0x216a
#define regDP0_DP_SEC_CNTL3_BASE_IDX 2
#define regDP0_DP_SEC_CNTL4 0x216b
#define regDP0_DP_SEC_CNTL4_BASE_IDX 2
#define regDP0_DP_SEC_CNTL5 0x216c
#define regDP0_DP_SEC_CNTL5_BASE_IDX 2
#define regDP0_DP_SEC_CNTL6 0x216d
#define regDP0_DP_SEC_CNTL6_BASE_IDX 2
#define regDP0_DP_SEC_CNTL7 0x216e
#define regDP0_DP_SEC_CNTL7_BASE_IDX 2
#define regDP0_DP_DB_CNTL 0x216f
#define regDP0_DP_DB_CNTL_BASE_IDX 2
#define regDP0_DP_MSA_VBID_MISC 0x2170
#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2
#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x2171
#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define regDP0_DP_ALPM_CNTL 0x2173
#define regDP0_DP_ALPM_CNTL_BASE_IDX 2
#define regDP0_DP_GSP8_CNTL 0x2174
#define regDP0_DP_GSP8_CNTL_BASE_IDX 2
#define regDP0_DP_GSP9_CNTL 0x2175
#define regDP0_DP_GSP9_CNTL_BASE_IDX 2
#define regDP0_DP_GSP10_CNTL 0x2176
#define regDP0_DP_GSP10_CNTL_BASE_IDX 2
#define regDP0_DP_GSP11_CNTL 0x2177
#define regDP0_DP_GSP11_CNTL_BASE_IDX 2
#define regDP0_DP_GSP_EN_DB_STATUS 0x2178
#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2
#define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2179
#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2
#define regDP0_DP_AUXLESS_ALPM_CNTL2 0x217a
#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2
#define regDP0_DP_AUXLESS_ALPM_CNTL3 0x217b
#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2
#define regDP0_DP_AUXLESS_ALPM_CNTL4 0x217c
#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2
#define regDP0_DP_AUXLESS_ALPM_CNTL5 0x217d
#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2
#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS 0x217e
#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2
#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL 0x217f
#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0 0x2180
#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2
#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1 0x2181
#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2
#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL 0x2182
#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x2183
#define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig0_dispdec
// base address: 0x0
#define regDIG0_DIG_FE_CNTL 0x2093
#define regDIG0_DIG_FE_CNTL_BASE_IDX 2
#define regDIG0_DIG_FE_CLK_CNTL 0x2094
#define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX 2
#define regDIG0_DIG_FE_EN_CNTL 0x2095
#define regDIG0_DIG_FE_EN_CNTL_BASE_IDX 2
#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x2096
#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x2097
#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define regDIG0_DIG_CLOCK_PATTERN 0x2098
#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
#define regDIG0_DIG_TEST_PATTERN 0x2099
#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2
#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x209a
#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define regDIG0_DIG_FIFO_CTRL0 0x209b
#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2
#define regDIG0_DIG_FIFO_CTRL1 0x209c
#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2
#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x209d
#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define regDIG0_HDMI_CONTROL 0x209e
#define regDIG0_HDMI_CONTROL_BASE_IDX 2
#define regDIG0_HDMI_STATUS 0x209f
#define regDIG0_HDMI_STATUS_BASE_IDX 2
#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x20a0
#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x20a1
#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x20a2
#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x20a3
#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define regDIG0_HDMI_INFOFRAME_CONTROL1 0x20a4
#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x20a5
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x20a6
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20a7
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
#define regDIG0_HDMI_GC 0x20a8
#define regDIG0_HDMI_GC_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x20a9
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20aa
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20ab
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20ac
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20ad
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20ae
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20af
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20b0
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
#define regDIG0_HDMI_DB_CONTROL 0x20b1
#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2
#define regDIG0_HDMI_ACR_32_0 0x20b2
#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2
#define regDIG0_HDMI_ACR_32_1 0x20b3
#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2
#define regDIG0_HDMI_ACR_44_0 0x20b4
#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2
#define regDIG0_HDMI_ACR_44_1 0x20b5
#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2
#define regDIG0_HDMI_ACR_48_0 0x20b6
#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2
#define regDIG0_HDMI_ACR_48_1 0x20b7
#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2
#define regDIG0_HDMI_ACR_STATUS_0 0x20b8
#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
#define regDIG0_HDMI_ACR_STATUS_1 0x20b9
#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
#define regDIG0_AFMT_CNTL 0x20ba
#define regDIG0_AFMT_CNTL_BASE_IDX 2
#define regDIG0_DIG_BE_CLK_CNTL 0x20bb
#define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX 2
#define regDIG0_DIG_BE_CNTL 0x20bc
#define regDIG0_DIG_BE_CNTL_BASE_IDX 2
#define regDIG0_DIG_BE_EN_CNTL 0x20bd
#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
#define regDIG0_TMDS_CNTL 0x20e4
#define regDIG0_TMDS_CNTL_BASE_IDX 2
#define regDIG0_TMDS_CONTROL_CHAR 0x20e5
#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20e6
#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20e7
#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20e8
#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20e9
#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define regDIG0_TMDS_CTL_BITS 0x20eb
#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2
#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20ec
#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20ed
#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20ee
#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20ef
#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define regDIG0_DIG_VERSION 0x20f1
#define regDIG0_DIG_VERSION_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dp1_dispdec
// base address: 0x490
#define regDP1_DP_LINK_CNTL 0x2242
#define regDP1_DP_LINK_CNTL_BASE_IDX 2
#define regDP1_DP_PIXEL_FORMAT 0x2243
#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2
#define regDP1_DP_MSA_COLORIMETRY 0x2244
#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
#define regDP1_DP_CONFIG 0x2245
#define regDP1_DP_CONFIG_BASE_IDX 2
#define regDP1_DP_VID_STREAM_CNTL 0x2246
#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
#define regDP1_DP_STEER_FIFO 0x2247
#define regDP1_DP_STEER_FIFO_BASE_IDX 2
#define regDP1_DP_MSA_MISC 0x2248
#define regDP1_DP_MSA_MISC_BASE_IDX 2
#define regDP1_DP_DPHY_INTERNAL_CTRL 0x2249
#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
#define regDP1_DP_VID_TIMING 0x224a
#define regDP1_DP_VID_TIMING_BASE_IDX 2
#define regDP1_DP_VID_N 0x224b
#define regDP1_DP_VID_N_BASE_IDX 2
#define regDP1_DP_VID_M 0x224c
#define regDP1_DP_VID_M_BASE_IDX 2
#define regDP1_DP_LINK_FRAMING_CNTL 0x224d
#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define regDP1_DP_HBR2_EYE_PATTERN 0x224e
#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define regDP1_DP_VID_MSA_VBID 0x224f
#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2
#define regDP1_DP_VID_INTERRUPT_CNTL 0x2250
#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define regDP1_DP_DPHY_CNTL 0x2251
#define regDP1_DP_DPHY_CNTL_BASE_IDX 2
#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2252
#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define regDP1_DP_DPHY_SYM0 0x2253
#define regDP1_DP_DPHY_SYM0_BASE_IDX 2
#define regDP1_DP_DPHY_SYM1 0x2254
#define regDP1_DP_DPHY_SYM1_BASE_IDX 2
#define regDP1_DP_DPHY_SYM2 0x2255
#define regDP1_DP_DPHY_SYM2_BASE_IDX 2
#define regDP1_DP_DPHY_8B10B_CNTL 0x2256
#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define regDP1_DP_DPHY_PRBS_CNTL 0x2257
#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define regDP1_DP_DPHY_SCRAM_CNTL 0x2258
#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define regDP1_DP_DPHY_CRC_EN 0x2259
#define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2
#define regDP1_DP_DPHY_CRC_CNTL 0x225a
#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define regDP1_DP_DPHY_CRC_RESULT 0x225b
#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define regDP1_DP_DPHY_CRC_MST_CNTL 0x225c
#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define regDP1_DP_DPHY_CRC_MST_STATUS 0x225d
#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define regDP1_DP_DPHY_FAST_TRAINING 0x225e
#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x225f
#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define regDP1_DP_TU_CNTL 0x2260
#define regDP1_DP_TU_CNTL_BASE_IDX 2
#define regDP1_DP_PIXEL_FORMAT_DB_CNTL 0x2261
#define regDP1_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2
#define regDP1_DP_CP_LINK_VERIFICATION_PATTERN 0x2262
#define regDP1_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX 2
#define regDP1_DP_SEC_CNTL 0x2265
#define regDP1_DP_SEC_CNTL_BASE_IDX 2
#define regDP1_DP_SEC_CNTL1 0x2266
#define regDP1_DP_SEC_CNTL1_BASE_IDX 2
#define regDP1_DP_SEC_FRAMING1 0x2267
#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2
#define regDP1_DP_SEC_FRAMING2 0x2268
#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2
#define regDP1_DP_SEC_FRAMING3 0x2269
#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2
#define regDP1_DP_SEC_FRAMING4 0x226a
#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2
#define regDP1_DP_SEC_AUD_N 0x226b
#define regDP1_DP_SEC_AUD_N_BASE_IDX 2
#define regDP1_DP_SEC_AUD_N_READBACK 0x226c
#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define regDP1_DP_SEC_AUD_M 0x226d
#define regDP1_DP_SEC_AUD_M_BASE_IDX 2
#define regDP1_DP_SEC_AUD_M_READBACK 0x226e
#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define regDP1_DP_SEC_TIMESTAMP 0x226f
#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
#define regDP1_DP_SEC_PACKET_CNTL 0x2270
#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define regDP1_DP_MSE_RATE_CNTL 0x2271
#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
#define regDP1_DP_CP_MSE_STATUS 0x2272
#define regDP1_DP_CP_MSE_STATUS_BASE_IDX 2
#define regDP1_DP_MSE_RATE_UPDATE 0x2273
#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define regDP1_DP_MSE_SAT0 0x2274
#define regDP1_DP_MSE_SAT0_BASE_IDX 2
#define regDP1_DP_MSE_SAT1 0x2275
#define regDP1_DP_MSE_SAT1_BASE_IDX 2
#define regDP1_DP_MSE_SAT2 0x2276
#define regDP1_DP_MSE_SAT2_BASE_IDX 2
#define regDP1_DP_MSE_SAT_UPDATE 0x2277
#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define regDP1_DP_MSE_LINK_TIMING 0x2278
#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
#define regDP1_DP_MSE_MISC_CNTL 0x2279
#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x227e
#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x227f
#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define regDP1_DP_MSE_SAT0_STATUS 0x2281
#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define regDP1_DP_MSE_SAT1_STATUS 0x2282
#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define regDP1_DP_MSE_SAT2_STATUS 0x2283
#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define regDP1_DP_DPIA_SPARE 0x2284
#define regDP1_DP_DPIA_SPARE_BASE_IDX 2
#define regDP1_DP_HBLANK_CONTROL 0x2285
#define regDP1_DP_HBLANK_CONTROL_BASE_IDX 2
#define regDP1_DP_MSA_TIMING_PARAM1 0x2286
#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define regDP1_DP_MSA_TIMING_PARAM2 0x2287
#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define regDP1_DP_MSA_TIMING_PARAM3 0x2288
#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define regDP1_DP_MSA_TIMING_PARAM4 0x2289
#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define regDP1_DP_MSO_CNTL 0x228a
#define regDP1_DP_MSO_CNTL_BASE_IDX 2
#define regDP1_DP_MSO_CNTL1 0x228b
#define regDP1_DP_MSO_CNTL1_BASE_IDX 2
#define regDP1_DP_STEER_FIFO_CNTL 0x228c
#define regDP1_DP_STEER_FIFO_CNTL_BASE_IDX 2
#define regDP1_DP_SEC_CNTL2 0x228d
#define regDP1_DP_SEC_CNTL2_BASE_IDX 2
#define regDP1_DP_SEC_CNTL3 0x228e
#define regDP1_DP_SEC_CNTL3_BASE_IDX 2
#define regDP1_DP_SEC_CNTL4 0x228f
#define regDP1_DP_SEC_CNTL4_BASE_IDX 2
#define regDP1_DP_SEC_CNTL5 0x2290
#define regDP1_DP_SEC_CNTL5_BASE_IDX 2
#define regDP1_DP_SEC_CNTL6 0x2291
#define regDP1_DP_SEC_CNTL6_BASE_IDX 2
#define regDP1_DP_SEC_CNTL7 0x2292
#define regDP1_DP_SEC_CNTL7_BASE_IDX 2
#define regDP1_DP_DB_CNTL 0x2293
#define regDP1_DP_DB_CNTL_BASE_IDX 2
#define regDP1_DP_MSA_VBID_MISC 0x2294
#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2
#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x2295
#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define regDP1_DP_ALPM_CNTL 0x2297
#define regDP1_DP_ALPM_CNTL_BASE_IDX 2
#define regDP1_DP_GSP8_CNTL 0x2298
#define regDP1_DP_GSP8_CNTL_BASE_IDX 2
#define regDP1_DP_GSP9_CNTL 0x2299
#define regDP1_DP_GSP9_CNTL_BASE_IDX 2
#define regDP1_DP_GSP10_CNTL 0x229a
#define regDP1_DP_GSP10_CNTL_BASE_IDX 2
#define regDP1_DP_GSP11_CNTL 0x229b
#define regDP1_DP_GSP11_CNTL_BASE_IDX 2
#define regDP1_DP_GSP_EN_DB_STATUS 0x229c
#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2
#define regDP1_DP_AUXLESS_ALPM_CNTL1 0x229d
#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2
#define regDP1_DP_AUXLESS_ALPM_CNTL2 0x229e
#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2
#define regDP1_DP_AUXLESS_ALPM_CNTL3 0x229f
#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2
#define regDP1_DP_AUXLESS_ALPM_CNTL4 0x22a0
#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2
#define regDP1_DP_AUXLESS_ALPM_CNTL5 0x22a1
#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2
#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS 0x22a2
#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2
#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL 0x22a3
#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0 0x22a4
#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2
#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1 0x22a5
#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2
#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL 0x22a6
#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x22a7
#define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig1_dispdec
// base address: 0x490
#define regDIG1_DIG_FE_CNTL 0x21b7
#define regDIG1_DIG_FE_CNTL_BASE_IDX 2
#define regDIG1_DIG_FE_CLK_CNTL 0x21b8
#define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX 2
#define regDIG1_DIG_FE_EN_CNTL 0x21b9
#define regDIG1_DIG_FE_EN_CNTL_BASE_IDX 2
#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x21ba
#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x21bb
#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define regDIG1_DIG_CLOCK_PATTERN 0x21bc
#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
#define regDIG1_DIG_TEST_PATTERN 0x21bd
#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2
#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x21be
#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define regDIG1_DIG_FIFO_CTRL0 0x21bf
#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2
#define regDIG1_DIG_FIFO_CTRL1 0x21c0
#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2
#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x21c1
#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define regDIG1_HDMI_CONTROL 0x21c2
#define regDIG1_HDMI_CONTROL_BASE_IDX 2
#define regDIG1_HDMI_STATUS 0x21c3
#define regDIG1_HDMI_STATUS_BASE_IDX 2
#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x21c4
#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x21c5
#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x21c6
#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x21c7
#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define regDIG1_HDMI_INFOFRAME_CONTROL1 0x21c8
#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x21c9
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x21ca
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21cb
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
#define regDIG1_HDMI_GC 0x21cc
#define regDIG1_HDMI_GC_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x21cd
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21ce
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21cf
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21d0
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21d1
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21d2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21d3
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21d4
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
#define regDIG1_HDMI_DB_CONTROL 0x21d5
#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2
#define regDIG1_HDMI_ACR_32_0 0x21d6
#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2
#define regDIG1_HDMI_ACR_32_1 0x21d7
#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2
#define regDIG1_HDMI_ACR_44_0 0x21d8
#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2
#define regDIG1_HDMI_ACR_44_1 0x21d9
#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2
#define regDIG1_HDMI_ACR_48_0 0x21da
#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2
#define regDIG1_HDMI_ACR_48_1 0x21db
#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2
#define regDIG1_HDMI_ACR_STATUS_0 0x21dc
#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
#define regDIG1_HDMI_ACR_STATUS_1 0x21dd
#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
#define regDIG1_AFMT_CNTL 0x21de
#define regDIG1_AFMT_CNTL_BASE_IDX 2
#define regDIG1_DIG_BE_CLK_CNTL 0x21df
#define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX 2
#define regDIG1_DIG_BE_CNTL 0x21e0
#define regDIG1_DIG_BE_CNTL_BASE_IDX 2
#define regDIG1_DIG_BE_EN_CNTL 0x21e1
#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
#define regDIG1_TMDS_CNTL 0x2208
#define regDIG1_TMDS_CNTL_BASE_IDX 2
#define regDIG1_TMDS_CONTROL_CHAR 0x2209
#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x220a
#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x220b
#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x220c
#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x220d
#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define regDIG1_TMDS_CTL_BITS 0x220f
#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2
#define regDIG1_TMDS_DCBALANCER_CONTROL 0x2210
#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x2211
#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x2212
#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x2213
#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define regDIG1_DIG_VERSION 0x2215
#define regDIG1_DIG_VERSION_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dp2_dispdec
// base address: 0x920
#define regDP2_DP_LINK_CNTL 0x2366
#define regDP2_DP_LINK_CNTL_BASE_IDX 2
#define regDP2_DP_PIXEL_FORMAT 0x2367
#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2
#define regDP2_DP_MSA_COLORIMETRY 0x2368
#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
#define regDP2_DP_CONFIG 0x2369
#define regDP2_DP_CONFIG_BASE_IDX 2
#define regDP2_DP_VID_STREAM_CNTL 0x236a
#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
#define regDP2_DP_STEER_FIFO 0x236b
#define regDP2_DP_STEER_FIFO_BASE_IDX 2
#define regDP2_DP_MSA_MISC 0x236c
#define regDP2_DP_MSA_MISC_BASE_IDX 2
#define regDP2_DP_DPHY_INTERNAL_CTRL 0x236d
#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
#define regDP2_DP_VID_TIMING 0x236e
#define regDP2_DP_VID_TIMING_BASE_IDX 2
#define regDP2_DP_VID_N 0x236f
#define regDP2_DP_VID_N_BASE_IDX 2
#define regDP2_DP_VID_M 0x2370
#define regDP2_DP_VID_M_BASE_IDX 2
#define regDP2_DP_LINK_FRAMING_CNTL 0x2371
#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define regDP2_DP_HBR2_EYE_PATTERN 0x2372
#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define regDP2_DP_VID_MSA_VBID 0x2373
#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2
#define regDP2_DP_VID_INTERRUPT_CNTL 0x2374
#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define regDP2_DP_DPHY_CNTL 0x2375
#define regDP2_DP_DPHY_CNTL_BASE_IDX 2
#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2376
#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define regDP2_DP_DPHY_SYM0 0x2377
#define regDP2_DP_DPHY_SYM0_BASE_IDX 2
#define regDP2_DP_DPHY_SYM1 0x2378
#define regDP2_DP_DPHY_SYM1_BASE_IDX 2
#define regDP2_DP_DPHY_SYM2 0x2379
#define regDP2_DP_DPHY_SYM2_BASE_IDX 2
#define regDP2_DP_DPHY_8B10B_CNTL 0x237a
#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define regDP2_DP_DPHY_PRBS_CNTL 0x237b
#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define regDP2_DP_DPHY_SCRAM_CNTL 0x237c
#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define regDP2_DP_DPHY_CRC_EN 0x237d
#define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2
#define regDP2_DP_DPHY_CRC_CNTL 0x237e
#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define regDP2_DP_DPHY_CRC_RESULT 0x237f
#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define regDP2_DP_DPHY_CRC_MST_CNTL 0x2380
#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define regDP2_DP_DPHY_CRC_MST_STATUS 0x2381
#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define regDP2_DP_DPHY_FAST_TRAINING 0x2382
#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2383
#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define regDP2_DP_TU_CNTL 0x2384
#define regDP2_DP_TU_CNTL_BASE_IDX 2
#define regDP2_DP_PIXEL_FORMAT_DB_CNTL 0x2385
#define regDP2_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2
#define regDP2_DP_CP_LINK_VERIFICATION_PATTERN 0x2386
#define regDP2_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX 2
#define regDP2_DP_SEC_CNTL 0x2389
#define regDP2_DP_SEC_CNTL_BASE_IDX 2
#define regDP2_DP_SEC_CNTL1 0x238a
#define regDP2_DP_SEC_CNTL1_BASE_IDX 2
#define regDP2_DP_SEC_FRAMING1 0x238b
#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2
#define regDP2_DP_SEC_FRAMING2 0x238c
#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2
#define regDP2_DP_SEC_FRAMING3 0x238d
#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2
#define regDP2_DP_SEC_FRAMING4 0x238e
#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2
#define regDP2_DP_SEC_AUD_N 0x238f
#define regDP2_DP_SEC_AUD_N_BASE_IDX 2
#define regDP2_DP_SEC_AUD_N_READBACK 0x2390
#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define regDP2_DP_SEC_AUD_M 0x2391
#define regDP2_DP_SEC_AUD_M_BASE_IDX 2
#define regDP2_DP_SEC_AUD_M_READBACK 0x2392
#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define regDP2_DP_SEC_TIMESTAMP 0x2393
#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
#define regDP2_DP_SEC_PACKET_CNTL 0x2394
#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define regDP2_DP_MSE_RATE_CNTL 0x2395
#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
#define regDP2_DP_CP_MSE_STATUS 0x2396
#define regDP2_DP_CP_MSE_STATUS_BASE_IDX 2
#define regDP2_DP_MSE_RATE_UPDATE 0x2397
#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define regDP2_DP_MSE_SAT0 0x2398
#define regDP2_DP_MSE_SAT0_BASE_IDX 2
#define regDP2_DP_MSE_SAT1 0x2399
#define regDP2_DP_MSE_SAT1_BASE_IDX 2
#define regDP2_DP_MSE_SAT2 0x239a
#define regDP2_DP_MSE_SAT2_BASE_IDX 2
#define regDP2_DP_MSE_SAT_UPDATE 0x239b
#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define regDP2_DP_MSE_LINK_TIMING 0x239c
#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
#define regDP2_DP_MSE_MISC_CNTL 0x239d
#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x23a2
#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x23a3
#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define regDP2_DP_MSE_SAT0_STATUS 0x23a5
#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define regDP2_DP_MSE_SAT1_STATUS 0x23a6
#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define regDP2_DP_MSE_SAT2_STATUS 0x23a7
#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define regDP2_DP_DPIA_SPARE 0x23a8
#define regDP2_DP_DPIA_SPARE_BASE_IDX 2
#define regDP2_DP_HBLANK_CONTROL 0x23a9
#define regDP2_DP_HBLANK_CONTROL_BASE_IDX 2
#define regDP2_DP_MSA_TIMING_PARAM1 0x23aa
#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define regDP2_DP_MSA_TIMING_PARAM2 0x23ab
#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define regDP2_DP_MSA_TIMING_PARAM3 0x23ac
#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define regDP2_DP_MSA_TIMING_PARAM4 0x23ad
#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define regDP2_DP_MSO_CNTL 0x23ae
#define regDP2_DP_MSO_CNTL_BASE_IDX 2
#define regDP2_DP_MSO_CNTL1 0x23af
#define regDP2_DP_MSO_CNTL1_BASE_IDX 2
#define regDP2_DP_STEER_FIFO_CNTL 0x23b0
#define regDP2_DP_STEER_FIFO_CNTL_BASE_IDX 2
#define regDP2_DP_SEC_CNTL2 0x23b1
#define regDP2_DP_SEC_CNTL2_BASE_IDX 2
#define regDP2_DP_SEC_CNTL3 0x23b2
#define regDP2_DP_SEC_CNTL3_BASE_IDX 2
#define regDP2_DP_SEC_CNTL4 0x23b3
#define regDP2_DP_SEC_CNTL4_BASE_IDX 2
#define regDP2_DP_SEC_CNTL5 0x23b4
#define regDP2_DP_SEC_CNTL5_BASE_IDX 2
#define regDP2_DP_SEC_CNTL6 0x23b5
#define regDP2_DP_SEC_CNTL6_BASE_IDX 2
#define regDP2_DP_SEC_CNTL7 0x23b6
#define regDP2_DP_SEC_CNTL7_BASE_IDX 2
#define regDP2_DP_DB_CNTL 0x23b7
#define regDP2_DP_DB_CNTL_BASE_IDX 2
#define regDP2_DP_MSA_VBID_MISC 0x23b8
#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2
#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x23b9
#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define regDP2_DP_ALPM_CNTL 0x23bb
#define regDP2_DP_ALPM_CNTL_BASE_IDX 2
#define regDP2_DP_GSP8_CNTL 0x23bc
#define regDP2_DP_GSP8_CNTL_BASE_IDX 2
#define regDP2_DP_GSP9_CNTL 0x23bd
#define regDP2_DP_GSP9_CNTL_BASE_IDX 2
#define regDP2_DP_GSP10_CNTL 0x23be
#define regDP2_DP_GSP10_CNTL_BASE_IDX 2
#define regDP2_DP_GSP11_CNTL 0x23bf
#define regDP2_DP_GSP11_CNTL_BASE_IDX 2
#define regDP2_DP_GSP_EN_DB_STATUS 0x23c0
#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2
#define regDP2_DP_AUXLESS_ALPM_CNTL1 0x23c1
#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2
#define regDP2_DP_AUXLESS_ALPM_CNTL2 0x23c2
#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2
#define regDP2_DP_AUXLESS_ALPM_CNTL3 0x23c3
#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2
#define regDP2_DP_AUXLESS_ALPM_CNTL4 0x23c4
#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2
#define regDP2_DP_AUXLESS_ALPM_CNTL5 0x23c5
#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2
#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS 0x23c6
#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2
#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL 0x23c7
#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0 0x23c8
#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2
#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1 0x23c9
#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2
#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL 0x23ca
#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x23cb
#define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig2_dispdec
// base address: 0x920
#define regDIG2_DIG_FE_CNTL 0x22db
#define regDIG2_DIG_FE_CNTL_BASE_IDX 2
#define regDIG2_DIG_FE_CLK_CNTL 0x22dc
#define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX 2
#define regDIG2_DIG_FE_EN_CNTL 0x22dd
#define regDIG2_DIG_FE_EN_CNTL_BASE_IDX 2
#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x22de
#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x22df
#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define regDIG2_DIG_CLOCK_PATTERN 0x22e0
#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
#define regDIG2_DIG_TEST_PATTERN 0x22e1
#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2
#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x22e2
#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define regDIG2_DIG_FIFO_CTRL0 0x22e3
#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2
#define regDIG2_DIG_FIFO_CTRL1 0x22e4
#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2
#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x22e5
#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define regDIG2_HDMI_CONTROL 0x22e6
#define regDIG2_HDMI_CONTROL_BASE_IDX 2
#define regDIG2_HDMI_STATUS 0x22e7
#define regDIG2_HDMI_STATUS_BASE_IDX 2
#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x22e8
#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x22e9
#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x22ea
#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x22eb
#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define regDIG2_HDMI_INFOFRAME_CONTROL1 0x22ec
#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x22ed
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x22ee
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22ef
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
#define regDIG2_HDMI_GC 0x22f0
#define regDIG2_HDMI_GC_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x22f1
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22f2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22f3
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22f4
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22f5
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22f6
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22f7
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22f8
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
#define regDIG2_HDMI_DB_CONTROL 0x22f9
#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2
#define regDIG2_HDMI_ACR_32_0 0x22fa
#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2
#define regDIG2_HDMI_ACR_32_1 0x22fb
#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2
#define regDIG2_HDMI_ACR_44_0 0x22fc
#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2
#define regDIG2_HDMI_ACR_44_1 0x22fd
#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2
#define regDIG2_HDMI_ACR_48_0 0x22fe
#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2
#define regDIG2_HDMI_ACR_48_1 0x22ff
#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2
#define regDIG2_HDMI_ACR_STATUS_0 0x2300
#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
#define regDIG2_HDMI_ACR_STATUS_1 0x2301
#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
#define regDIG2_AFMT_CNTL 0x2302
#define regDIG2_AFMT_CNTL_BASE_IDX 2
#define regDIG2_DIG_BE_CLK_CNTL 0x2303
#define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX 2
#define regDIG2_DIG_BE_CNTL 0x2304
#define regDIG2_DIG_BE_CNTL_BASE_IDX 2
#define regDIG2_DIG_BE_EN_CNTL 0x2305
#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
#define regDIG2_TMDS_CNTL 0x232c
#define regDIG2_TMDS_CNTL_BASE_IDX 2
#define regDIG2_TMDS_CONTROL_CHAR 0x232d
#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x232e
#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x232f
#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x2330
#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x2331
#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define regDIG2_TMDS_CTL_BITS 0x2333
#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2
#define regDIG2_TMDS_DCBALANCER_CONTROL 0x2334
#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x2335
#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x2336
#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x2337
#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define regDIG2_DIG_VERSION 0x2339
#define regDIG2_DIG_VERSION_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dp3_dispdec
// base address: 0xdb0
#define regDP3_DP_LINK_CNTL 0x248a
#define regDP3_DP_LINK_CNTL_BASE_IDX 2
#define regDP3_DP_PIXEL_FORMAT 0x248b
#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2
#define regDP3_DP_MSA_COLORIMETRY 0x248c
#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
#define regDP3_DP_CONFIG 0x248d
#define regDP3_DP_CONFIG_BASE_IDX 2
#define regDP3_DP_VID_STREAM_CNTL 0x248e
#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
#define regDP3_DP_STEER_FIFO 0x248f
#define regDP3_DP_STEER_FIFO_BASE_IDX 2
#define regDP3_DP_MSA_MISC 0x2490
#define regDP3_DP_MSA_MISC_BASE_IDX 2
#define regDP3_DP_DPHY_INTERNAL_CTRL 0x2491
#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
#define regDP3_DP_VID_TIMING 0x2492
#define regDP3_DP_VID_TIMING_BASE_IDX 2
#define regDP3_DP_VID_N 0x2493
#define regDP3_DP_VID_N_BASE_IDX 2
#define regDP3_DP_VID_M 0x2494
#define regDP3_DP_VID_M_BASE_IDX 2
#define regDP3_DP_LINK_FRAMING_CNTL 0x2495
#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define regDP3_DP_HBR2_EYE_PATTERN 0x2496
#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define regDP3_DP_VID_MSA_VBID 0x2497
#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2
#define regDP3_DP_VID_INTERRUPT_CNTL 0x2498
#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define regDP3_DP_DPHY_CNTL 0x2499
#define regDP3_DP_DPHY_CNTL_BASE_IDX 2
#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x249a
#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define regDP3_DP_DPHY_SYM0 0x249b
#define regDP3_DP_DPHY_SYM0_BASE_IDX 2
#define regDP3_DP_DPHY_SYM1 0x249c
#define regDP3_DP_DPHY_SYM1_BASE_IDX 2
#define regDP3_DP_DPHY_SYM2 0x249d
#define regDP3_DP_DPHY_SYM2_BASE_IDX 2
#define regDP3_DP_DPHY_8B10B_CNTL 0x249e
#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define regDP3_DP_DPHY_PRBS_CNTL 0x249f
#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define regDP3_DP_DPHY_SCRAM_CNTL 0x24a0
#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define regDP3_DP_DPHY_CRC_EN 0x24a1
#define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2
#define regDP3_DP_DPHY_CRC_CNTL 0x24a2
#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define regDP3_DP_DPHY_CRC_RESULT 0x24a3
#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define regDP3_DP_DPHY_CRC_MST_CNTL 0x24a4
#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define regDP3_DP_DPHY_CRC_MST_STATUS 0x24a5
#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define regDP3_DP_DPHY_FAST_TRAINING 0x24a6
#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x24a7
#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define regDP3_DP_TU_CNTL 0x24a8
#define regDP3_DP_TU_CNTL_BASE_IDX 2
#define regDP3_DP_PIXEL_FORMAT_DB_CNTL 0x24a9
#define regDP3_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2
#define regDP3_DP_CP_LINK_VERIFICATION_PATTERN 0x24aa
#define regDP3_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX 2
#define regDP3_DP_SEC_CNTL 0x24ad
#define regDP3_DP_SEC_CNTL_BASE_IDX 2
#define regDP3_DP_SEC_CNTL1 0x24ae
#define regDP3_DP_SEC_CNTL1_BASE_IDX 2
#define regDP3_DP_SEC_FRAMING1 0x24af
#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2
#define regDP3_DP_SEC_FRAMING2 0x24b0
#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2
#define regDP3_DP_SEC_FRAMING3 0x24b1
#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2
#define regDP3_DP_SEC_FRAMING4 0x24b2
#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2
#define regDP3_DP_SEC_AUD_N 0x24b3
#define regDP3_DP_SEC_AUD_N_BASE_IDX 2
#define regDP3_DP_SEC_AUD_N_READBACK 0x24b4
#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define regDP3_DP_SEC_AUD_M 0x24b5
#define regDP3_DP_SEC_AUD_M_BASE_IDX 2
#define regDP3_DP_SEC_AUD_M_READBACK 0x24b6
#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define regDP3_DP_SEC_TIMESTAMP 0x24b7
#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
#define regDP3_DP_SEC_PACKET_CNTL 0x24b8
#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define regDP3_DP_MSE_RATE_CNTL 0x24b9
#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
#define regDP3_DP_CP_MSE_STATUS 0x24ba
#define regDP3_DP_CP_MSE_STATUS_BASE_IDX 2
#define regDP3_DP_MSE_RATE_UPDATE 0x24bb
#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define regDP3_DP_MSE_SAT0 0x24bc
#define regDP3_DP_MSE_SAT0_BASE_IDX 2
#define regDP3_DP_MSE_SAT1 0x24bd
#define regDP3_DP_MSE_SAT1_BASE_IDX 2
#define regDP3_DP_MSE_SAT2 0x24be
#define regDP3_DP_MSE_SAT2_BASE_IDX 2
#define regDP3_DP_MSE_SAT_UPDATE 0x24bf
#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define regDP3_DP_MSE_LINK_TIMING 0x24c0
#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
#define regDP3_DP_MSE_MISC_CNTL 0x24c1
#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x24c6
#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x24c7
#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define regDP3_DP_MSE_SAT0_STATUS 0x24c9
#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define regDP3_DP_MSE_SAT1_STATUS 0x24ca
#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define regDP3_DP_MSE_SAT2_STATUS 0x24cb
#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define regDP3_DP_DPIA_SPARE 0x24cc
#define regDP3_DP_DPIA_SPARE_BASE_IDX 2
#define regDP3_DP_HBLANK_CONTROL 0x24cd
#define regDP3_DP_HBLANK_CONTROL_BASE_IDX 2
#define regDP3_DP_MSA_TIMING_PARAM1 0x24ce
#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define regDP3_DP_MSA_TIMING_PARAM2 0x24cf
#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define regDP3_DP_MSA_TIMING_PARAM3 0x24d0
#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define regDP3_DP_MSA_TIMING_PARAM4 0x24d1
#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define regDP3_DP_MSO_CNTL 0x24d2
#define regDP3_DP_MSO_CNTL_BASE_IDX 2
#define regDP3_DP_MSO_CNTL1 0x24d3
#define regDP3_DP_MSO_CNTL1_BASE_IDX 2
#define regDP3_DP_STEER_FIFO_CNTL 0x24d4
#define regDP3_DP_STEER_FIFO_CNTL_BASE_IDX 2
#define regDP3_DP_SEC_CNTL2 0x24d5
#define regDP3_DP_SEC_CNTL2_BASE_IDX 2
#define regDP3_DP_SEC_CNTL3 0x24d6
#define regDP3_DP_SEC_CNTL3_BASE_IDX 2
#define regDP3_DP_SEC_CNTL4 0x24d7
#define regDP3_DP_SEC_CNTL4_BASE_IDX 2
#define regDP3_DP_SEC_CNTL5 0x24d8
#define regDP3_DP_SEC_CNTL5_BASE_IDX 2
#define regDP3_DP_SEC_CNTL6 0x24d9
#define regDP3_DP_SEC_CNTL6_BASE_IDX 2
#define regDP3_DP_SEC_CNTL7 0x24da
#define regDP3_DP_SEC_CNTL7_BASE_IDX 2
#define regDP3_DP_DB_CNTL 0x24db
#define regDP3_DP_DB_CNTL_BASE_IDX 2
#define regDP3_DP_MSA_VBID_MISC 0x24dc
#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2
#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x24dd
#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define regDP3_DP_ALPM_CNTL 0x24df
#define regDP3_DP_ALPM_CNTL_BASE_IDX 2
#define regDP3_DP_GSP8_CNTL 0x24e0
#define regDP3_DP_GSP8_CNTL_BASE_IDX 2
#define regDP3_DP_GSP9_CNTL 0x24e1
#define regDP3_DP_GSP9_CNTL_BASE_IDX 2
#define regDP3_DP_GSP10_CNTL 0x24e2
#define regDP3_DP_GSP10_CNTL_BASE_IDX 2
#define regDP3_DP_GSP11_CNTL 0x24e3
#define regDP3_DP_GSP11_CNTL_BASE_IDX 2
#define regDP3_DP_GSP_EN_DB_STATUS 0x24e4
#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2
#define regDP3_DP_AUXLESS_ALPM_CNTL1 0x24e5
#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2
#define regDP3_DP_AUXLESS_ALPM_CNTL2 0x24e6
#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2
#define regDP3_DP_AUXLESS_ALPM_CNTL3 0x24e7
#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2
#define regDP3_DP_AUXLESS_ALPM_CNTL4 0x24e8
#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2
#define regDP3_DP_AUXLESS_ALPM_CNTL5 0x24e9
#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2
#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS 0x24ea
#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2
#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL 0x24eb
#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0 0x24ec
#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2
#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1 0x24ed
#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2
#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL 0x24ee
#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x24ef
#define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig3_dispdec
// base address: 0xdb0
#define regDIG3_DIG_FE_CNTL 0x23ff
#define regDIG3_DIG_FE_CNTL_BASE_IDX 2
#define regDIG3_DIG_FE_CLK_CNTL 0x2400
#define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX 2
#define regDIG3_DIG_FE_EN_CNTL 0x2401
#define regDIG3_DIG_FE_EN_CNTL_BASE_IDX 2
#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x2402
#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x2403
#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define regDIG3_DIG_CLOCK_PATTERN 0x2404
#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
#define regDIG3_DIG_TEST_PATTERN 0x2405
#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2
#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2406
#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define regDIG3_DIG_FIFO_CTRL0 0x2407
#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2
#define regDIG3_DIG_FIFO_CTRL1 0x2408
#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2
#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2409
#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define regDIG3_HDMI_CONTROL 0x240a
#define regDIG3_HDMI_CONTROL_BASE_IDX 2
#define regDIG3_HDMI_STATUS 0x240b
#define regDIG3_HDMI_STATUS_BASE_IDX 2
#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x240c
#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x240d
#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x240e
#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x240f
#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2410
#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2411
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x2412
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x2413
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
#define regDIG3_HDMI_GC 0x2414
#define regDIG3_HDMI_GC_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2415
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2416
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2417
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2418
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x2419
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x241a
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x241b
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x241c
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
#define regDIG3_HDMI_DB_CONTROL 0x241d
#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2
#define regDIG3_HDMI_ACR_32_0 0x241e
#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2
#define regDIG3_HDMI_ACR_32_1 0x241f
#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2
#define regDIG3_HDMI_ACR_44_0 0x2420
#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2
#define regDIG3_HDMI_ACR_44_1 0x2421
#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2
#define regDIG3_HDMI_ACR_48_0 0x2422
#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2
#define regDIG3_HDMI_ACR_48_1 0x2423
#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2
#define regDIG3_HDMI_ACR_STATUS_0 0x2424
#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
#define regDIG3_HDMI_ACR_STATUS_1 0x2425
#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
#define regDIG3_AFMT_CNTL 0x2426
#define regDIG3_AFMT_CNTL_BASE_IDX 2
#define regDIG3_DIG_BE_CLK_CNTL 0x2427
#define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX 2
#define regDIG3_DIG_BE_CNTL 0x2428
#define regDIG3_DIG_BE_CNTL_BASE_IDX 2
#define regDIG3_DIG_BE_EN_CNTL 0x2429
#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
#define regDIG3_TMDS_CNTL 0x2450
#define regDIG3_TMDS_CNTL_BASE_IDX 2
#define regDIG3_TMDS_CONTROL_CHAR 0x2451
#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x2452
#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x2453
#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x2454
#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x2455
#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define regDIG3_TMDS_CTL_BITS 0x2457
#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2
#define regDIG3_TMDS_DCBALANCER_CONTROL 0x2458
#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x2459
#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x245a
#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x245b
#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define regDIG3_DIG_VERSION 0x245d
#define regDIG3_DIG_VERSION_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig0_afmt_afmt_dispdec
// base address: 0x154cc
#define regAFMT0_AFMT_ACP 0x2073
#define regAFMT0_AFMT_ACP_BASE_IDX 2
#define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074
#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075
#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define regAFMT0_AFMT_AUDIO_INFO0 0x2076
#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2
#define regAFMT0_AFMT_AUDIO_INFO1 0x2077
#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2
#define regAFMT0_AFMT_60958_0 0x2078
#define regAFMT0_AFMT_60958_0_BASE_IDX 2
#define regAFMT0_AFMT_60958_1 0x2079
#define regAFMT0_AFMT_60958_1_BASE_IDX 2
#define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a
#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define regAFMT0_AFMT_RAMP_CONTROL0 0x207b
#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define regAFMT0_AFMT_RAMP_CONTROL1 0x207c
#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define regAFMT0_AFMT_RAMP_CONTROL2 0x207d
#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define regAFMT0_AFMT_RAMP_CONTROL3 0x207e
#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define regAFMT0_AFMT_60958_2 0x207f
#define regAFMT0_AFMT_60958_2_BASE_IDX 2
#define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080
#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define regAFMT0_AFMT_STATUS 0x2081
#define regAFMT0_AFMT_STATUS_BASE_IDX 2
#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082
#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083
#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084
#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085
#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define regAFMT0_AFMT_AUDIO_DBG_DTO_CNTL 0x2086
#define regAFMT0_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX 2
#define regAFMT0_AFMT_MEM_PWR 0x2087
#define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig1_afmt_afmt_dispdec
// base address: 0x1595c
#define regAFMT1_AFMT_ACP 0x2197
#define regAFMT1_AFMT_ACP_BASE_IDX 2
#define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2198
#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2199
#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define regAFMT1_AFMT_AUDIO_INFO0 0x219a
#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2
#define regAFMT1_AFMT_AUDIO_INFO1 0x219b
#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2
#define regAFMT1_AFMT_60958_0 0x219c
#define regAFMT1_AFMT_60958_0_BASE_IDX 2
#define regAFMT1_AFMT_60958_1 0x219d
#define regAFMT1_AFMT_60958_1_BASE_IDX 2
#define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x219e
#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define regAFMT1_AFMT_RAMP_CONTROL0 0x219f
#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define regAFMT1_AFMT_RAMP_CONTROL1 0x21a0
#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define regAFMT1_AFMT_RAMP_CONTROL2 0x21a1
#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define regAFMT1_AFMT_RAMP_CONTROL3 0x21a2
#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define regAFMT1_AFMT_60958_2 0x21a3
#define regAFMT1_AFMT_60958_2_BASE_IDX 2
#define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x21a4
#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define regAFMT1_AFMT_STATUS 0x21a5
#define regAFMT1_AFMT_STATUS_BASE_IDX 2
#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x21a6
#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x21a7
#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define regAFMT1_AFMT_INTERRUPT_STATUS 0x21a8
#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x21a9
#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define regAFMT1_AFMT_AUDIO_DBG_DTO_CNTL 0x21aa
#define regAFMT1_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX 2
#define regAFMT1_AFMT_MEM_PWR 0x21ab
#define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig2_afmt_afmt_dispdec
// base address: 0x15dec
#define regAFMT2_AFMT_ACP 0x22bb
#define regAFMT2_AFMT_ACP_BASE_IDX 2
#define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x22bc
#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x22bd
#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define regAFMT2_AFMT_AUDIO_INFO0 0x22be
#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2
#define regAFMT2_AFMT_AUDIO_INFO1 0x22bf
#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2
#define regAFMT2_AFMT_60958_0 0x22c0
#define regAFMT2_AFMT_60958_0_BASE_IDX 2
#define regAFMT2_AFMT_60958_1 0x22c1
#define regAFMT2_AFMT_60958_1_BASE_IDX 2
#define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x22c2
#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define regAFMT2_AFMT_RAMP_CONTROL0 0x22c3
#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define regAFMT2_AFMT_RAMP_CONTROL1 0x22c4
#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define regAFMT2_AFMT_RAMP_CONTROL2 0x22c5
#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define regAFMT2_AFMT_RAMP_CONTROL3 0x22c6
#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define regAFMT2_AFMT_60958_2 0x22c7
#define regAFMT2_AFMT_60958_2_BASE_IDX 2
#define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x22c8
#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define regAFMT2_AFMT_STATUS 0x22c9
#define regAFMT2_AFMT_STATUS_BASE_IDX 2
#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x22ca
#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x22cb
#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define regAFMT2_AFMT_INTERRUPT_STATUS 0x22cc
#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x22cd
#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define regAFMT2_AFMT_AUDIO_DBG_DTO_CNTL 0x22ce
#define regAFMT2_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX 2
#define regAFMT2_AFMT_MEM_PWR 0x22cf
#define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig3_afmt_afmt_dispdec
// base address: 0x1627c
#define regAFMT3_AFMT_ACP 0x23df
#define regAFMT3_AFMT_ACP_BASE_IDX 2
#define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x23e0
#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x23e1
#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define regAFMT3_AFMT_AUDIO_INFO0 0x23e2
#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2
#define regAFMT3_AFMT_AUDIO_INFO1 0x23e3
#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2
#define regAFMT3_AFMT_60958_0 0x23e4
#define regAFMT3_AFMT_60958_0_BASE_IDX 2
#define regAFMT3_AFMT_60958_1 0x23e5
#define regAFMT3_AFMT_60958_1_BASE_IDX 2
#define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x23e6
#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define regAFMT3_AFMT_RAMP_CONTROL0 0x23e7
#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define regAFMT3_AFMT_RAMP_CONTROL1 0x23e8
#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define regAFMT3_AFMT_RAMP_CONTROL2 0x23e9
#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define regAFMT3_AFMT_RAMP_CONTROL3 0x23ea
#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define regAFMT3_AFMT_60958_2 0x23eb
#define regAFMT3_AFMT_60958_2_BASE_IDX 2
#define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x23ec
#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define regAFMT3_AFMT_STATUS 0x23ed
#define regAFMT3_AFMT_STATUS_BASE_IDX 2
#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x23ee
#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x23ef
#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define regAFMT3_AFMT_INTERRUPT_STATUS 0x23f0
#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x23f1
#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define regAFMT3_AFMT_AUDIO_DBG_DTO_CNTL 0x23f2
#define regAFMT3_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX 2
#define regAFMT3_AFMT_MEM_PWR 0x23f3
#define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig0_dme_dme_dispdec
// base address: 0x15544
#define regDME0_DME_CONTROL 0x2091
#define regDME0_DME_CONTROL_BASE_IDX 2
#define regDME0_DME_MEMORY_CONTROL 0x2092
#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig0_vpg_vpg_dispdec
// base address: 0x154a0
#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068
#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069
#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a
#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b
#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define regVPG0_VPG_GENERIC_STATUS 0x206c
#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2
#define regVPG0_VPG_MEM_PWR 0x206d
#define regVPG0_VPG_MEM_PWR_BASE_IDX 2
#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e
#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define regVPG0_VPG_ISRC1_2_DATA 0x206f
#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2
#define regVPG0_VPG_MPEG_INFO0 0x2070
#define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2
#define regVPG0_VPG_MPEG_INFO1 0x2071
#define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig1_dme_dme_dispdec
// base address: 0x159d4
#define regDME1_DME_CONTROL 0x21b5
#define regDME1_DME_CONTROL_BASE_IDX 2
#define regDME1_DME_MEMORY_CONTROL 0x21b6
#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig1_vpg_vpg_dispdec
// base address: 0x15930
#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x218c
#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define regVPG1_VPG_GENERIC_PACKET_DATA 0x218d
#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x218e
#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x218f
#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define regVPG1_VPG_GENERIC_STATUS 0x2190
#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2
#define regVPG1_VPG_MEM_PWR 0x2191
#define regVPG1_VPG_MEM_PWR_BASE_IDX 2
#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x2192
#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define regVPG1_VPG_ISRC1_2_DATA 0x2193
#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2
#define regVPG1_VPG_MPEG_INFO0 0x2194
#define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2
#define regVPG1_VPG_MPEG_INFO1 0x2195
#define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig2_dme_dme_dispdec
// base address: 0x15e64
#define regDME2_DME_CONTROL 0x22d9
#define regDME2_DME_CONTROL_BASE_IDX 2
#define regDME2_DME_MEMORY_CONTROL 0x22da
#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig2_vpg_vpg_dispdec
// base address: 0x15dc0
#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x22b0
#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define regVPG2_VPG_GENERIC_PACKET_DATA 0x22b1
#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x22b2
#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x22b3
#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define regVPG2_VPG_GENERIC_STATUS 0x22b4
#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2
#define regVPG2_VPG_MEM_PWR 0x22b5
#define regVPG2_VPG_MEM_PWR_BASE_IDX 2
#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x22b6
#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define regVPG2_VPG_ISRC1_2_DATA 0x22b7
#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2
#define regVPG2_VPG_MPEG_INFO0 0x22b8
#define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2
#define regVPG2_VPG_MPEG_INFO1 0x22b9
#define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig3_dme_dme_dispdec
// base address: 0x162f4
#define regDME3_DME_CONTROL 0x23fd
#define regDME3_DME_CONTROL_BASE_IDX 2
#define regDME3_DME_MEMORY_CONTROL 0x23fe
#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig3_vpg_vpg_dispdec
// base address: 0x16250
#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x23d4
#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define regVPG3_VPG_GENERIC_PACKET_DATA 0x23d5
#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x23d6
#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x23d7
#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define regVPG3_VPG_GENERIC_STATUS 0x23d8
#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2
#define regVPG3_VPG_MEM_PWR 0x23d9
#define regVPG3_VPG_MEM_PWR_BASE_IDX 2
#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x23da
#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define regVPG3_VPG_ISRC1_2_DATA 0x23db
#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2
#define regVPG3_VPG_MPEG_INFO0 0x23dc
#define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2
#define regVPG3_VPG_MPEG_INFO1 0x23dd
#define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dcn_dcec_dio_hdcp1kp_dispdec
// base address: 0x14cd8
// addressBlock: dcn_dcec_dio_dout_i2c_dispdec
// base address: 0x0
#define regDC_I2C_CONTROL 0x1e98
#define regDC_I2C_CONTROL_BASE_IDX 2
#define regDC_I2C_ARBITRATION 0x1e99
#define regDC_I2C_ARBITRATION_BASE_IDX 2
#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a
#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
#define regDC_I2C_SW_STATUS 0x1e9b
#define regDC_I2C_SW_STATUS_BASE_IDX 2
#define regDC_I2C_DDC1_HW_STATUS 0x1e9c
#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
#define regDC_I2C_DDC2_HW_STATUS 0x1e9d
#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
#define regDC_I2C_DDC3_HW_STATUS 0x1e9e
#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
#define regDC_I2C_DDC4_HW_STATUS 0x1e9f
#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
#define regDC_I2C_DDC5_HW_STATUS 0x1ea0
#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
#define regDC_I2C_DDC6_HW_STATUS 0x1ea1
#define regDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
#define regDC_I2C_DDC1_SPEED 0x1ea2
#define regDC_I2C_DDC1_SPEED_BASE_IDX 2
#define regDC_I2C_DDC1_SETUP 0x1ea3
#define regDC_I2C_DDC1_SETUP_BASE_IDX 2
#define regDC_I2C_DDC2_SPEED 0x1ea4
#define regDC_I2C_DDC2_SPEED_BASE_IDX 2
#define regDC_I2C_DDC2_SETUP 0x1ea5
#define regDC_I2C_DDC2_SETUP_BASE_IDX 2
#define regDC_I2C_DDC3_SPEED 0x1ea6
#define regDC_I2C_DDC3_SPEED_BASE_IDX 2
#define regDC_I2C_DDC3_SETUP 0x1ea7
#define regDC_I2C_DDC3_SETUP_BASE_IDX 2
#define regDC_I2C_DDC4_SPEED 0x1ea8
#define regDC_I2C_DDC4_SPEED_BASE_IDX 2
#define regDC_I2C_DDC4_SETUP 0x1ea9
#define regDC_I2C_DDC4_SETUP_BASE_IDX 2
#define regDC_I2C_DDC5_SPEED 0x1eaa
#define regDC_I2C_DDC5_SPEED_BASE_IDX 2
#define regDC_I2C_DDC5_SETUP 0x1eab
#define regDC_I2C_DDC5_SETUP_BASE_IDX 2
#define regDC_I2C_DDC6_SPEED 0x1eac
#define regDC_I2C_DDC6_SPEED_BASE_IDX 2
#define regDC_I2C_DDC6_SETUP 0x1ead
#define regDC_I2C_DDC6_SETUP_BASE_IDX 2
#define regDC_I2C_TRANSACTION0 0x1eae
#define regDC_I2C_TRANSACTION0_BASE_IDX 2
#define regDC_I2C_TRANSACTION1 0x1eaf
#define regDC_I2C_TRANSACTION1_BASE_IDX 2
#define regDC_I2C_TRANSACTION2 0x1eb0
#define regDC_I2C_TRANSACTION2_BASE_IDX 2
#define regDC_I2C_TRANSACTION3 0x1eb1
#define regDC_I2C_TRANSACTION3_BASE_IDX 2
#define regDC_I2C_DATA 0x1eb2
#define regDC_I2C_DATA_BASE_IDX 2
#define regDC_I2C_DDCVGA_HW_STATUS 0x1eb3
#define regDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2
#define regDC_I2C_DDCVGA_SPEED 0x1eb4
#define regDC_I2C_DDCVGA_SPEED_BASE_IDX 2
#define regDC_I2C_DDCVGA_SETUP 0x1eb5
#define regDC_I2C_DDCVGA_SETUP_BASE_IDX 2
#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6
#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7
#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dio_misc_dispdec
// base address: 0x0
#define regDIO_DCN_STATUS 0x1ec3
#define regDIO_DCN_STATUS_BASE_IDX 2
#define regDIO_SCRATCH0 0x1eca
#define regDIO_SCRATCH0_BASE_IDX 2
#define regDIO_SCRATCH1 0x1ecb
#define regDIO_SCRATCH1_BASE_IDX 2
#define regDIO_SCRATCH2 0x1ecc
#define regDIO_SCRATCH2_BASE_IDX 2
#define regDIO_SCRATCH3 0x1ecd
#define regDIO_SCRATCH3_BASE_IDX 2
#define regDIO_SCRATCH4 0x1ece
#define regDIO_SCRATCH4_BASE_IDX 2
#define regDIO_SCRATCH5 0x1ecf
#define regDIO_SCRATCH5_BASE_IDX 2
#define regDIO_SCRATCH6 0x1ed0
#define regDIO_SCRATCH6_BASE_IDX 2
#define regDIO_SCRATCH7 0x1ed1
#define regDIO_SCRATCH7_BASE_IDX 2
#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3
#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2
#define regDIO_MEM_PWR_STATUS 0x1edd
#define regDIO_MEM_PWR_STATUS_BASE_IDX 2
#define regDIO_MEM_PWR_CTRL 0x1ede
#define regDIO_MEM_PWR_CTRL_BASE_IDX 2
#define regDIO_MEM_PWR_CTRL2 0x1edf
#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2
#define regDIO_CLK_CNTL 0x1ee0
#define regDIO_CLK_CNTL_BASE_IDX 2
#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4
#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
#define regDIO_STEREOSYNC_SEL 0x1eea
#define regDIO_STEREOSYNC_SEL_BASE_IDX 2
#define regDIO_SOFT_RESET 0x1eed
#define regDIO_SOFT_RESET_BASE_IDX 2
#define regHDCP_CLK_STATUS 0x1ef4
#define regHDCP_CLK_STATUS_BASE_IDX 2
#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff
#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
#define regDIO_PSP_INTERRUPT_STATUS 0x1f00
#define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2
#define regDIO_PSP_INTERRUPT_CLEAR 0x1f01
#define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
#define regDIO_STATUS 0x1f02
#define regDIO_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dio_dig_stream_mapper_dispdec
// base address: 0x0
#define regDIG0_STREAM_MAPPER_CONTROL 0x1f0d
#define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX 2
#define regDIG1_STREAM_MAPPER_CONTROL 0x1f0e
#define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX 2
#define regDIG2_STREAM_MAPPER_CONTROL 0x1f0f
#define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX 2
#define regDIG3_STREAM_MAPPER_CONTROL 0x1f10
#define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX 2
#define regDIG4_STREAM_MAPPER_CONTROL 0x1f11
#define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX 2
#define regDIG5_STREAM_MAPPER_CONTROL 0x1f12
#define regDIG5_STREAM_MAPPER_CONTROL_BASE_IDX 2
#define regDIG6_STREAM_MAPPER_CONTROL 0x1f13
#define regDIG6_STREAM_MAPPER_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dcio_dcio_dispdec
// base address: 0x0
#define regDC_GENERICA 0x2868
#define regDC_GENERICA_BASE_IDX 2
#define regDC_GENERICB 0x2869
#define regDC_GENERICB_BASE_IDX 2
#define regDCIO_CLOCK_CNTL 0x286a
#define regDCIO_CLOCK_CNTL_BASE_IDX 2
#define regDC_REF_CLK_CNTL 0x286b
#define regDC_REF_CLK_CNTL_BASE_IDX 2
#define regUNIPHYA_LINK_CNTL 0x286d
#define regUNIPHYA_LINK_CNTL_BASE_IDX 2
#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYB_LINK_CNTL 0x286f
#define regUNIPHYB_LINK_CNTL_BASE_IDX 2
#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYC_LINK_CNTL 0x2871
#define regUNIPHYC_LINK_CNTL_BASE_IDX 2
#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYD_LINK_CNTL 0x2873
#define regUNIPHYD_LINK_CNTL_BASE_IDX 2
#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYE_LINK_CNTL 0x2875
#define regUNIPHYE_LINK_CNTL_BASE_IDX 2
#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYF_LINK_CNTL 0x2877
#define regUNIPHYF_LINK_CNTL_BASE_IDX 2
#define regUNIPHYF_CHANNEL_XBAR_CNTL 0x2878
#define regUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYG_LINK_CNTL 0x2879
#define regUNIPHYG_LINK_CNTL_BASE_IDX 2
#define regUNIPHYG_CHANNEL_XBAR_CNTL 0x287a
#define regUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regDCIO_WRCMD_DELAY 0x287e
#define regDCIO_WRCMD_DELAY_BASE_IDX 2
#define regDC_PINSTRAPS 0x2880
#define regDC_PINSTRAPS_BASE_IDX 2
#define regCC_DC_MISC_STRAPS 0x2881
#define regCC_DC_MISC_STRAPS_BASE_IDX 2
#define regDCIO_SPARE 0x2882
#define regDCIO_SPARE_BASE_IDX 2
#define regINTERCEPT_STATE 0x2884
#define regINTERCEPT_STATE_BASE_IDX 2
#define regDCIO_PATTERN_GEN_PAT 0x2886
#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2
#define regDCIO_PATTERN_GEN_EN 0x2887
#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2
#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c
#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
#define regDBG_OUT_CNTL 0x289c
#define regDBG_OUT_CNTL_BASE_IDX 2
#define regDCIO_SOFT_RESET 0x289e
#define regDCIO_SOFT_RESET_BASE_IDX 2
// addressBlock: dcn_dcec_dcio_dcio_chip_dispdec
// base address: 0x0
#define regDC_GPIO_GENERIC_MASK 0x28c8
#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2
#define regDC_GPIO_GENERIC_A 0x28c9
#define regDC_GPIO_GENERIC_A_BASE_IDX 2
#define regDC_GPIO_GENERIC_EN 0x28ca
#define regDC_GPIO_GENERIC_EN_BASE_IDX 2
#define regDC_GPIO_GENERIC_Y 0x28cb
#define regDC_GPIO_GENERIC_Y_BASE_IDX 2
#define regDC_GPIO_DDC1_MASK 0x28d0
#define regDC_GPIO_DDC1_MASK_BASE_IDX 2
#define regDC_GPIO_DDC1_A 0x28d1
#define regDC_GPIO_DDC1_A_BASE_IDX 2
#define regDC_GPIO_DDC1_EN 0x28d2
#define regDC_GPIO_DDC1_EN_BASE_IDX 2
#define regDC_GPIO_DDC1_Y 0x28d3
#define regDC_GPIO_DDC1_Y_BASE_IDX 2
#define regDC_GPIO_DDC2_MASK 0x28d4
#define regDC_GPIO_DDC2_MASK_BASE_IDX 2
#define regDC_GPIO_DDC2_A 0x28d5
#define regDC_GPIO_DDC2_A_BASE_IDX 2
#define regDC_GPIO_DDC2_EN 0x28d6
#define regDC_GPIO_DDC2_EN_BASE_IDX 2
#define regDC_GPIO_DDC2_Y 0x28d7
#define regDC_GPIO_DDC2_Y_BASE_IDX 2
#define regDC_GPIO_DDC3_MASK 0x28d8
#define regDC_GPIO_DDC3_MASK_BASE_IDX 2
#define regDC_GPIO_DDC3_A 0x28d9
#define regDC_GPIO_DDC3_A_BASE_IDX 2
#define regDC_GPIO_DDC3_EN 0x28da
#define regDC_GPIO_DDC3_EN_BASE_IDX 2
#define regDC_GPIO_DDC3_Y 0x28db
#define regDC_GPIO_DDC3_Y_BASE_IDX 2
#define regDC_GPIO_DDC4_MASK 0x28dc
#define regDC_GPIO_DDC4_MASK_BASE_IDX 2
#define regDC_GPIO_DDC4_A 0x28dd
#define regDC_GPIO_DDC4_A_BASE_IDX 2
#define regDC_GPIO_DDC4_EN 0x28de
#define regDC_GPIO_DDC4_EN_BASE_IDX 2
#define regDC_GPIO_DDC4_Y 0x28df
#define regDC_GPIO_DDC4_Y_BASE_IDX 2
#define regDC_GPIO_DDC5_MASK 0x28e0
#define regDC_GPIO_DDC5_MASK_BASE_IDX 2
#define regDC_GPIO_DDC5_A 0x28e1
#define regDC_GPIO_DDC5_A_BASE_IDX 2
#define regDC_GPIO_DDC5_EN 0x28e2
#define regDC_GPIO_DDC5_EN_BASE_IDX 2
#define regDC_GPIO_DDC5_Y 0x28e3
#define regDC_GPIO_DDC5_Y_BASE_IDX 2
#define regDC_GPIO_DDC6_MASK 0x28e4
#define regDC_GPIO_DDC6_MASK_BASE_IDX 2
#define regDC_GPIO_DDC6_A 0x28e5
#define regDC_GPIO_DDC6_A_BASE_IDX 2
#define regDC_GPIO_DDC6_EN 0x28e6
#define regDC_GPIO_DDC6_EN_BASE_IDX 2
#define regDC_GPIO_DDC6_Y 0x28e7
#define regDC_GPIO_DDC6_Y_BASE_IDX 2
#define regDC_GPIO_DDCVGA_MASK 0x28e8
#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2
#define regDC_GPIO_DDCVGA_A 0x28e9
#define regDC_GPIO_DDCVGA_A_BASE_IDX 2
#define regDC_GPIO_DDCVGA_EN 0x28ea
#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2
#define regDC_GPIO_DDCVGA_Y 0x28eb
#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2
#define regDC_GPIO_SYNCA_MASK 0x28ec
#define regDC_GPIO_SYNCA_MASK_BASE_IDX 2
#define regDC_GPIO_GENLK_MASK 0x28f0
#define regDC_GPIO_GENLK_MASK_BASE_IDX 2
#define regDC_GPIO_GENLK_A 0x28f1
#define regDC_GPIO_GENLK_A_BASE_IDX 2
#define regDC_GPIO_GENLK_EN 0x28f2
#define regDC_GPIO_GENLK_EN_BASE_IDX 2
#define regDC_GPIO_GENLK_Y 0x28f3
#define regDC_GPIO_GENLK_Y_BASE_IDX 2
#define regDC_GPIO_HPD_MASK 0x28f4
#define regDC_GPIO_HPD_MASK_BASE_IDX 2
#define regDC_GPIO_HPD_A 0x28f5
#define regDC_GPIO_HPD_A_BASE_IDX 2
#define regDC_GPIO_HPD_EN 0x28f6
#define regDC_GPIO_HPD_EN_BASE_IDX 2
#define regDC_GPIO_HPD_Y 0x28f7
#define regDC_GPIO_HPD_Y_BASE_IDX 2
#define regDC_GPIO_DRIVE_STRENGTH_S0 0x28f8
#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX 2
#define regDC_GPIO_DRIVE_STRENGTH_S1 0x28f9
#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX 2
#define regDC_GPIO_PWRSEQ0_EN 0x28fa
#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2
#define regDC_GPIO_PAD_STRENGTH_1 0x28fc
#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
#define regDC_GPIO_RESERVED 0x28fe
#define regDC_GPIO_RESERVED_BASE_IDX 2
#define regPHY_AUX_CNTL 0x28ff
#define regPHY_AUX_CNTL_BASE_IDX 2
#define regDC_GPIO_DRIVE_TXIMPSEL 0x2900
#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX 2
#define regDC_GPIO_PWRSEQ1_EN 0x2902
#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2
#define regDC_GPIO_I2S_SPDIF_MASK 0x2910
#define regDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2
#define regDC_GPIO_I2S_SPDIF_A 0x2911
#define regDC_GPIO_I2S_SPDIF_A_BASE_IDX 2
#define regDC_GPIO_I2S_SPDIF_EN 0x2912
#define regDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2
#define regDC_GPIO_I2S_SPDIF_Y 0x2913
#define regDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2
#define regDC_GPIO_I2S_SPDIF_STRENGTH 0x2914
#define regDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2
#define regDC_GPIO_TX12_EN 0x2915
#define regDC_GPIO_TX12_EN_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_0 0x2916
#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_1 0x2917
#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2
#define regDC_GPIO_RXEN 0x2919
#define regDC_GPIO_RXEN_BASE_IDX 2
#define regDC_GPIO_PULLUPEN 0x291a
#define regDC_GPIO_PULLUPEN_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_3 0x291b
#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_4 0x291c
#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_5 0x291d
#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2
#define regAUXI2C_PAD_ALL_PWR_OK 0x291e
#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
// addressBlock: dcn_dcec_dcio_dcio_uniphy0_dispdec
// base address: 0x0
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961
#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
// addressBlock: dcn_dcec_dcio_dcio_uniphy1_dispdec
// base address: 0x360
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
// addressBlock: dcn_dcec_dcio_dcio_uniphy2_dispdec
// base address: 0x6c0
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
// addressBlock: dcn_dcec_dcio_dcio_uniphy3_dispdec
// base address: 0xa20
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
// addressBlock: dcn_dcec_pwrseq0_dispdec_pwrseq_dispdec
// base address: 0x0
#define regDC_GPIO_PWRSEQ_EN 0x2f10
#define regDC_GPIO_PWRSEQ_EN_BASE_IDX 2
#define regDC_GPIO_PWRSEQ_CTRL 0x2f11
#define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX 2
#define regDC_GPIO_PWRSEQ_MASK 0x2f12
#define regDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
#define regDC_GPIO_PWRSEQ_A_Y 0x2f13
#define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX 2
#define regPANEL_PWRSEQ_CNTL 0x2f14
#define regPANEL_PWRSEQ_CNTL_BASE_IDX 2
#define regPANEL_PWRSEQ_STATE 0x2f15
#define regPANEL_PWRSEQ_STATE_BASE_IDX 2
#define regPANEL_PWRSEQ_DELAY1 0x2f16
#define regPANEL_PWRSEQ_DELAY1_BASE_IDX 2
#define regPANEL_PWRSEQ_DELAY2 0x2f17
#define regPANEL_PWRSEQ_DELAY2_BASE_IDX 2
#define regPANEL_PWRSEQ_REF_DIV1 0x2f18
#define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX 2
#define regBL_PWM_CNTL 0x2f19
#define regBL_PWM_CNTL_BASE_IDX 2
#define regBL_PWM_CNTL2 0x2f1a
#define regBL_PWM_CNTL2_BASE_IDX 2
#define regBL_PWM_PERIOD_CNTL 0x2f1b
#define regBL_PWM_PERIOD_CNTL_BASE_IDX 2
#define regBL_PWM_GRP1_REG_LOCK 0x2f1c
#define regBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
#define regPANEL_PWRSEQ_REF_DIV2 0x2f1d
#define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX 2
#define regPWRSEQ_DBG_SEL 0x2f20
#define regPWRSEQ_DBG_SEL_BASE_IDX 2
#define regPWRSEQ_SPARE 0x2f21
#define regPWRSEQ_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_dsc0_dispdec_dscc_dispdec
// base address: 0x0
#define regDSCC0_DSCC_CONFIG0 0x300a
#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2
#define regDSCC0_DSCC_CONFIG1 0x300b
#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2
#define regDSCC0_DSCC_CONFIG2 0x300c
#define regDSCC0_DSCC_CONFIG2_BASE_IDX 2
#define regDSCC0_DSCC_STATUS 0x300d
#define regDSCC0_DSCC_STATUS_BASE_IDX 2
#define regDSCC0_DSCC_INTERRUPT_CONTROL0 0x300e
#define regDSCC0_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2
#define regDSCC0_DSCC_INTERRUPT_CONTROL1 0x300f
#define regDSCC0_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2
#define regDSCC0_DSCC_INTERRUPT_STATUS0 0x3010
#define regDSCC0_DSCC_INTERRUPT_STATUS0_BASE_IDX 2
#define regDSCC0_DSCC_INTERRUPT_STATUS1 0x3011
#define regDSCC0_DSCC_INTERRUPT_STATUS1_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG0 0x3012
#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG1 0x3013
#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG2 0x3014
#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG3 0x3015
#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG4 0x3016
#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG5 0x3017
#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG6 0x3018
#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG7 0x3019
#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG8 0x301a
#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG9 0x301b
#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG10 0x301c
#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG11 0x301d
#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG12 0x301e
#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG13 0x301f
#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG14 0x3020
#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG15 0x3021
#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG16 0x3022
#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG17 0x3023
#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG18 0x3024
#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG19 0x3025
#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG20 0x3026
#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG21 0x3027
#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2
#define regDSCC0_DSCC_PPS_CONFIG22 0x3028
#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2
#define regDSCC0_DSCC_MEM_POWER_CONTROL0 0x3029
#define regDSCC0_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2
#define regDSCC0_DSCC_MEM_POWER_CONTROL1 0x302a
#define regDSCC0_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2
#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x302b
#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x302c
#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x302d
#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x302e
#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302f
#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3030
#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x3031
#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x3032
#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x3033
#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2
#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3034
#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2
#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3035
#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2
#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x3036
#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2
#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x3037
#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2
#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x3038
#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2
#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x3039
#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2
#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x303a
#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2
#define regDSCC0_DSCC_TEST_DEBUG_INDEX0 0x303b
#define regDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define regDSCC0_DSCC_TEST_DEBUG_INDEX1 0x303c
#define regDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define regDSCC0_DSCC_TEST_DEBUG_INDEX2 0x303d
#define regDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define regDSCC0_DSCC_TEST_DEBUG_INDEX3 0x303e
#define regDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303f
#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define regDSCC0_DSCC_TEST_DEBUG_DATA0 0x3040
#define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define regDSCC0_DSCC_TEST_DEBUG_DATA1 0x3041
#define regDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define regDSCC0_DSCC_TEST_DEBUG_DATA2 0x3042
#define regDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define regDSCC0_DSCC_TEST_DEBUG_DATA3 0x3043
#define regDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x3044
#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2
#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x3045
#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2
// addressBlock: dcn_dcec_dsc0_dispdec_dsccif_dispdec
// base address: 0x0
#define regDSCCIF0_DSCCIF_CONFIG0 0x3005
#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2
// addressBlock: dcn_dcec_dsc0_dispdec_dsc_top_dispdec
// base address: 0x0
#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000
#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2
#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001
#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2
#define regDSC_TOP0_DSC_SPARE_DEBUG 0x3002
#define regDSC_TOP0_DSC_SPARE_DEBUG_BASE_IDX 2
#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX 0x3003
#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2
#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA 0x3004
#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dsc1_dispdec_dscc_dispdec
// base address: 0x170
#define regDSCC1_DSCC_CONFIG0 0x3066
#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2
#define regDSCC1_DSCC_CONFIG1 0x3067
#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2
#define regDSCC1_DSCC_CONFIG2 0x3068
#define regDSCC1_DSCC_CONFIG2_BASE_IDX 2
#define regDSCC1_DSCC_STATUS 0x3069
#define regDSCC1_DSCC_STATUS_BASE_IDX 2
#define regDSCC1_DSCC_INTERRUPT_CONTROL0 0x306a
#define regDSCC1_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2
#define regDSCC1_DSCC_INTERRUPT_CONTROL1 0x306b
#define regDSCC1_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2
#define regDSCC1_DSCC_INTERRUPT_STATUS0 0x306c
#define regDSCC1_DSCC_INTERRUPT_STATUS0_BASE_IDX 2
#define regDSCC1_DSCC_INTERRUPT_STATUS1 0x306d
#define regDSCC1_DSCC_INTERRUPT_STATUS1_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG0 0x306e
#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG1 0x306f
#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG2 0x3070
#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG3 0x3071
#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG4 0x3072
#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG5 0x3073
#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG6 0x3074
#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG7 0x3075
#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG8 0x3076
#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG9 0x3077
#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG10 0x3078
#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG11 0x3079
#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG12 0x307a
#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG13 0x307b
#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG14 0x307c
#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG15 0x307d
#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG16 0x307e
#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG17 0x307f
#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG18 0x3080
#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG19 0x3081
#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG20 0x3082
#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG21 0x3083
#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2
#define regDSCC1_DSCC_PPS_CONFIG22 0x3084
#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2
#define regDSCC1_DSCC_MEM_POWER_CONTROL0 0x3085
#define regDSCC1_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2
#define regDSCC1_DSCC_MEM_POWER_CONTROL1 0x3086
#define regDSCC1_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2
#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3087
#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3088
#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3089
#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x308a
#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x308b
#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x308c
#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x308d
#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x308e
#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x308f
#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2
#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3090
#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2
#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3091
#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2
#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x3092
#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2
#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x3093
#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2
#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x3094
#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2
#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x3095
#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2
#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x3096
#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2
#define regDSCC1_DSCC_TEST_DEBUG_INDEX0 0x3097
#define regDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define regDSCC1_DSCC_TEST_DEBUG_INDEX1 0x3098
#define regDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define regDSCC1_DSCC_TEST_DEBUG_INDEX2 0x3099
#define regDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define regDSCC1_DSCC_TEST_DEBUG_INDEX3 0x309a
#define regDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x309b
#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define regDSCC1_DSCC_TEST_DEBUG_DATA0 0x309c
#define regDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define regDSCC1_DSCC_TEST_DEBUG_DATA1 0x309d
#define regDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define regDSCC1_DSCC_TEST_DEBUG_DATA2 0x309e
#define regDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define regDSCC1_DSCC_TEST_DEBUG_DATA3 0x309f
#define regDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x30a0
#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2
#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x30a1
#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2
// addressBlock: dcn_dcec_dsc1_dispdec_dsccif_dispdec
// base address: 0x170
#define regDSCCIF1_DSCCIF_CONFIG0 0x3061
#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2
// addressBlock: dcn_dcec_dsc1_dispdec_dsc_top_dispdec
// base address: 0x170
#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c
#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2
#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d
#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2
#define regDSC_TOP1_DSC_SPARE_DEBUG 0x305e
#define regDSC_TOP1_DSC_SPARE_DEBUG_BASE_IDX 2
#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX 0x305f
#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2
#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA 0x3060
#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dsc2_dispdec_dscc_dispdec
// base address: 0x2e0
#define regDSCC2_DSCC_CONFIG0 0x30c2
#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2
#define regDSCC2_DSCC_CONFIG1 0x30c3
#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2
#define regDSCC2_DSCC_CONFIG2 0x30c4
#define regDSCC2_DSCC_CONFIG2_BASE_IDX 2
#define regDSCC2_DSCC_STATUS 0x30c5
#define regDSCC2_DSCC_STATUS_BASE_IDX 2
#define regDSCC2_DSCC_INTERRUPT_CONTROL0 0x30c6
#define regDSCC2_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2
#define regDSCC2_DSCC_INTERRUPT_CONTROL1 0x30c7
#define regDSCC2_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2
#define regDSCC2_DSCC_INTERRUPT_STATUS0 0x30c8
#define regDSCC2_DSCC_INTERRUPT_STATUS0_BASE_IDX 2
#define regDSCC2_DSCC_INTERRUPT_STATUS1 0x30c9
#define regDSCC2_DSCC_INTERRUPT_STATUS1_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG0 0x30ca
#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG1 0x30cb
#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG2 0x30cc
#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG3 0x30cd
#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG4 0x30ce
#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG5 0x30cf
#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG6 0x30d0
#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG7 0x30d1
#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG8 0x30d2
#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG9 0x30d3
#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG10 0x30d4
#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG11 0x30d5
#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG12 0x30d6
#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG13 0x30d7
#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG14 0x30d8
#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG15 0x30d9
#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG16 0x30da
#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG17 0x30db
#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG18 0x30dc
#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG19 0x30dd
#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG20 0x30de
#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG21 0x30df
#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2
#define regDSCC2_DSCC_PPS_CONFIG22 0x30e0
#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2
#define regDSCC2_DSCC_MEM_POWER_CONTROL0 0x30e1
#define regDSCC2_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2
#define regDSCC2_DSCC_MEM_POWER_CONTROL1 0x30e2
#define regDSCC2_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2
#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30e3
#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30e4
#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e5
#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e6
#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e7
#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e8
#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e9
#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30ea
#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x30eb
#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2
#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x30ec
#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2
#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x30ed
#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2
#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x30ee
#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2
#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x30ef
#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2
#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x30f0
#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2
#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x30f1
#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2
#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x30f2
#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2
#define regDSCC2_DSCC_TEST_DEBUG_INDEX0 0x30f3
#define regDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define regDSCC2_DSCC_TEST_DEBUG_INDEX1 0x30f4
#define regDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define regDSCC2_DSCC_TEST_DEBUG_INDEX2 0x30f5
#define regDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define regDSCC2_DSCC_TEST_DEBUG_INDEX3 0x30f6
#define regDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f7
#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define regDSCC2_DSCC_TEST_DEBUG_DATA0 0x30f8
#define regDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define regDSCC2_DSCC_TEST_DEBUG_DATA1 0x30f9
#define regDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define regDSCC2_DSCC_TEST_DEBUG_DATA2 0x30fa
#define regDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define regDSCC2_DSCC_TEST_DEBUG_DATA3 0x30fb
#define regDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x30fc
#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2
#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x30fd
#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2
// addressBlock: dcn_dcec_dsc2_dispdec_dsccif_dispdec
// base address: 0x2e0
#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd
#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2
// addressBlock: dcn_dcec_dsc2_dispdec_dsc_top_dispdec
// base address: 0x2e0
#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8
#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2
#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9
#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2
#define regDSC_TOP2_DSC_SPARE_DEBUG 0x30ba
#define regDSC_TOP2_DSC_SPARE_DEBUG_BASE_IDX 2
#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX 0x30bb
#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2
#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA 0x30bc
#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dsc3_dispdec_dscc_dispdec
// base address: 0x450
#define regDSCC3_DSCC_CONFIG0 0x311e
#define regDSCC3_DSCC_CONFIG0_BASE_IDX 2
#define regDSCC3_DSCC_CONFIG1 0x311f
#define regDSCC3_DSCC_CONFIG1_BASE_IDX 2
#define regDSCC3_DSCC_CONFIG2 0x3120
#define regDSCC3_DSCC_CONFIG2_BASE_IDX 2
#define regDSCC3_DSCC_STATUS 0x3121
#define regDSCC3_DSCC_STATUS_BASE_IDX 2
#define regDSCC3_DSCC_INTERRUPT_CONTROL0 0x3122
#define regDSCC3_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2
#define regDSCC3_DSCC_INTERRUPT_CONTROL1 0x3123
#define regDSCC3_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2
#define regDSCC3_DSCC_INTERRUPT_STATUS0 0x3124
#define regDSCC3_DSCC_INTERRUPT_STATUS0_BASE_IDX 2
#define regDSCC3_DSCC_INTERRUPT_STATUS1 0x3125
#define regDSCC3_DSCC_INTERRUPT_STATUS1_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG0 0x3126
#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG1 0x3127
#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG2 0x3128
#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG3 0x3129
#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG4 0x312a
#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG5 0x312b
#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG6 0x312c
#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG7 0x312d
#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG8 0x312e
#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG9 0x312f
#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG10 0x3130
#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG11 0x3131
#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG12 0x3132
#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG13 0x3133
#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG14 0x3134
#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG15 0x3135
#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG16 0x3136
#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG17 0x3137
#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG18 0x3138
#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG19 0x3139
#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG20 0x313a
#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG21 0x313b
#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2
#define regDSCC3_DSCC_PPS_CONFIG22 0x313c
#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2
#define regDSCC3_DSCC_MEM_POWER_CONTROL0 0x313d
#define regDSCC3_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2
#define regDSCC3_DSCC_MEM_POWER_CONTROL1 0x313e
#define regDSCC3_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2
#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313f
#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3140
#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3141
#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3142
#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3143
#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3144
#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
#define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3145
#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
#define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3146
#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x3147
#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2
#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3148
#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2
#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3149
#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2
#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x314a
#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2
#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x314b
#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2
#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x314c
#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2
#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x314d
#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2
#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x314e
#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2
#define regDSCC3_DSCC_TEST_DEBUG_INDEX0 0x314f
#define regDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2
#define regDSCC3_DSCC_TEST_DEBUG_INDEX1 0x3150
#define regDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2
#define regDSCC3_DSCC_TEST_DEBUG_INDEX2 0x3151
#define regDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2
#define regDSCC3_DSCC_TEST_DEBUG_INDEX3 0x3152
#define regDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2
#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x3153
#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
#define regDSCC3_DSCC_TEST_DEBUG_DATA0 0x3154
#define regDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2
#define regDSCC3_DSCC_TEST_DEBUG_DATA1 0x3155
#define regDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2
#define regDSCC3_DSCC_TEST_DEBUG_DATA2 0x3156
#define regDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2
#define regDSCC3_DSCC_TEST_DEBUG_DATA3 0x3157
#define regDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2
#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x3158
#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2
#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x3159
#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2
// addressBlock: dcn_dcec_dsc3_dispdec_dsccif_dispdec
// base address: 0x450
#define regDSCCIF3_DSCCIF_CONFIG0 0x3119
#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2
// addressBlock: dcn_dcec_dsc3_dispdec_dsc_top_dispdec
// base address: 0x450
#define regDSC_TOP3_DSC_TOP_CONTROL 0x3114
#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2
#define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115
#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2
#define regDSC_TOP3_DSC_SPARE_DEBUG 0x3116
#define regDSC_TOP3_DSC_SPARE_DEBUG_BASE_IDX 2
#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX 0x3117
#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2
#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA 0x3118
#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_dcoh_top_dispdec
// base address: 0x0
#define regDCOH_TOP_CLOCK_CONTROL 0x17af
#define regDCOH_TOP_CLOCK_CONTROL_BASE_IDX 2
#define regDCOH_TOP_SPARE 0x17b3
#define regDCOH_TOP_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_phy_mux0_dispdec
// base address: 0x13168
#define regPHY_MUX0_PHY_MUX_CONTROL 0x179a
#define regPHY_MUX0_PHY_MUX_CONTROL_BASE_IDX 2
#define regPHY_MUX0_PORT_TYPE 0x179b
#define regPHY_MUX0_PORT_TYPE_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_phy_mux1_dispdec
// base address: 0x13174
#define regPHY_MUX1_PHY_MUX_CONTROL 0x179d
#define regPHY_MUX1_PHY_MUX_CONTROL_BASE_IDX 2
#define regPHY_MUX1_PORT_TYPE 0x179e
#define regPHY_MUX1_PORT_TYPE_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_phy_mux2_dispdec
// base address: 0x13180
#define regPHY_MUX2_PHY_MUX_CONTROL 0x17a0
#define regPHY_MUX2_PHY_MUX_CONTROL_BASE_IDX 2
#define regPHY_MUX2_PORT_TYPE 0x17a1
#define regPHY_MUX2_PORT_TYPE_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_phy_mux3_dispdec
// base address: 0x1318c
#define regPHY_MUX3_PHY_MUX_CONTROL 0x17a3
#define regPHY_MUX3_PHY_MUX_CONTROL_BASE_IDX 2
#define regPHY_MUX3_PORT_TYPE 0x17a4
#define regPHY_MUX3_PORT_TYPE_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_dp_aux0_dispdec
// base address: 0x0
#define regDP_AUX0_AUX_CONTROL 0x16b2
#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2
#define regDP_AUX0_AUX_SW_CONTROL 0x16b3
#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
#define regDP_AUX0_AUX_ARB_CONTROL 0x16b4
#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x16b5
#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define regDP_AUX0_AUX_SW_STATUS 0x16b6
#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
#define regDP_AUX0_AUX_LS_STATUS 0x16b7
#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
#define regDP_AUX0_AUX_SW_DATA 0x16b8
#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2
#define regDP_AUX0_AUX_LS_DATA 0x16b9
#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2
#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x16ba
#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x16bb
#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x16bc
#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x16bd
#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x16be
#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x16bf
#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x16c1
#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2
#define regDP_AUX0_AUX_PHY_WAKE_STATUS 0x16c2
#define regDP_AUX0_AUX_PHY_WAKE_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_dp_aux1_dispdec
// base address: 0x70
#define regDP_AUX1_AUX_CONTROL 0x16ce
#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2
#define regDP_AUX1_AUX_SW_CONTROL 0x16cf
#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
#define regDP_AUX1_AUX_ARB_CONTROL 0x16d0
#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x16d1
#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define regDP_AUX1_AUX_SW_STATUS 0x16d2
#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
#define regDP_AUX1_AUX_LS_STATUS 0x16d3
#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
#define regDP_AUX1_AUX_SW_DATA 0x16d4
#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2
#define regDP_AUX1_AUX_LS_DATA 0x16d5
#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2
#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x16d6
#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x16d7
#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x16d8
#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x16d9
#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x16da
#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x16db
#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x16dd
#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2
#define regDP_AUX1_AUX_PHY_WAKE_STATUS 0x16de
#define regDP_AUX1_AUX_PHY_WAKE_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_dp_aux2_dispdec
// base address: 0xe0
#define regDP_AUX2_AUX_CONTROL 0x16ea
#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2
#define regDP_AUX2_AUX_SW_CONTROL 0x16eb
#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
#define regDP_AUX2_AUX_ARB_CONTROL 0x16ec
#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x16ed
#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define regDP_AUX2_AUX_SW_STATUS 0x16ee
#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
#define regDP_AUX2_AUX_LS_STATUS 0x16ef
#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
#define regDP_AUX2_AUX_SW_DATA 0x16f0
#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2
#define regDP_AUX2_AUX_LS_DATA 0x16f1
#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2
#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x16f2
#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x16f3
#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x16f4
#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x16f5
#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x16f6
#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x16f7
#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x16f9
#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2
#define regDP_AUX2_AUX_PHY_WAKE_STATUS 0x16fa
#define regDP_AUX2_AUX_PHY_WAKE_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_dp_aux3_dispdec
// base address: 0x150
#define regDP_AUX3_AUX_CONTROL 0x1706
#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2
#define regDP_AUX3_AUX_SW_CONTROL 0x1707
#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
#define regDP_AUX3_AUX_ARB_CONTROL 0x1708
#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1709
#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define regDP_AUX3_AUX_SW_STATUS 0x170a
#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
#define regDP_AUX3_AUX_LS_STATUS 0x170b
#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
#define regDP_AUX3_AUX_SW_DATA 0x170c
#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2
#define regDP_AUX3_AUX_LS_DATA 0x170d
#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2
#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x170e
#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x170f
#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1710
#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1711
#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1712
#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1713
#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1715
#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2
#define regDP_AUX3_AUX_PHY_WAKE_STATUS 0x1716
#define regDP_AUX3_AUX_PHY_WAKE_STATUS_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_hpd0_dispdec
// base address: 0x0
#define regHPD0_DC_HPD_INT_STATUS 0x175a
#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
#define regHPD0_DC_HPD_INT_CONTROL 0x175b
#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
#define regHPD0_DC_HPD_CONTROL 0x175c
#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2
#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x175d
#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x175e
#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_hpd1_dispdec
// base address: 0x20
#define regHPD1_DC_HPD_INT_STATUS 0x1762
#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
#define regHPD1_DC_HPD_INT_CONTROL 0x1763
#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
#define regHPD1_DC_HPD_CONTROL 0x1764
#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2
#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1765
#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1766
#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_hpd2_dispdec
// base address: 0x40
#define regHPD2_DC_HPD_INT_STATUS 0x176a
#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
#define regHPD2_DC_HPD_INT_CONTROL 0x176b
#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
#define regHPD2_DC_HPD_CONTROL 0x176c
#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2
#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x176d
#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x176e
#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dcn_dcec_dcoh_hpd3_dispdec
// base address: 0x60
#define regHPD3_DC_HPD_INT_STATUS 0x1772
#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
#define regHPD3_DC_HPD_INT_CONTROL 0x1773
#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
#define regHPD3_DC_HPD_CONTROL 0x1774
#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2
#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1775
#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1776
#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_hpo_top_dispdec
// base address: 0x2790c
#define regHPO_TOP_CLOCK_CONTROL 0x0e43
#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3
#define regHPO_TOP_HW_CONTROL 0x0e44
#define regHPO_TOP_HW_CONTROL_BASE_IDX 3
// addressBlock: dcn_dcec_hpo_dp_stream_mapper_dispdec
// base address: 0x27958
#define regDP_STREAM_MAPPER_CONTROL0 0x0e56
#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3
#define regDP_STREAM_MAPPER_CONTROL1 0x0e57
#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3
#define regDP_STREAM_MAPPER_CONTROL2 0x0e58
#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3
#define regDP_STREAM_MAPPER_CONTROL3 0x0e59
#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3
#define regDP_STREAM_MAPPER_CONTROL4 0x0e5a
#define regDP_STREAM_MAPPER_CONTROL4_BASE_IDX 3
#define regDP_STREAM_MAPPER_CONTROL5 0x0e5b
#define regDP_STREAM_MAPPER_CONTROL5_BASE_IDX 3
// addressBlock: dcn_dcec_hpo_hdmi_link_enc0_dispdec
// base address: 0x2656c
#define regHDMI_LINK_ENC_CONTROL 0x095b
#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3
#define regHDMI_LINK_ENC_CLK_CTRL 0x095c
#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3
// addressBlock: dcn_dcec_hpo_hdmi_frl_enc0_dispdec
// base address: 0x26594
#define regHDMI_FRL_ENC_CONFIG 0x0965
#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3
#define regHDMI_FRL_ENC_CONFIG2 0x0966
#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3
#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967
#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3
#define regHDMI_FRL_ENC_MEM_CTRL 0x0968
#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3
// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dispdec
// base address: 0x2634c
#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3
#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3
#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5
#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3
// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
// base address: 0x2646c
#define regAFMT4_AFMT_ACP 0x091b
#define regAFMT4_AFMT_ACP_BASE_IDX 3
#define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x091c
#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3
#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x091d
#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3
#define regAFMT4_AFMT_AUDIO_INFO0 0x091e
#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 3
#define regAFMT4_AFMT_AUDIO_INFO1 0x091f
#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 3
#define regAFMT4_AFMT_60958_0 0x0920
#define regAFMT4_AFMT_60958_0_BASE_IDX 3
#define regAFMT4_AFMT_60958_1 0x0921
#define regAFMT4_AFMT_60958_1_BASE_IDX 3
#define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x0922
#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3
#define regAFMT4_AFMT_RAMP_CONTROL0 0x0923
#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 3
#define regAFMT4_AFMT_RAMP_CONTROL1 0x0924
#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 3
#define regAFMT4_AFMT_RAMP_CONTROL2 0x0925
#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 3
#define regAFMT4_AFMT_RAMP_CONTROL3 0x0926
#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 3
#define regAFMT4_AFMT_60958_2 0x0927
#define regAFMT4_AFMT_60958_2_BASE_IDX 3
#define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x0928
#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3
#define regAFMT4_AFMT_STATUS 0x0929
#define regAFMT4_AFMT_STATUS_BASE_IDX 3
#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x092a
#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3
#define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x092b
#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3
#define regAFMT4_AFMT_INTERRUPT_STATUS 0x092c
#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 3
#define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x092d
#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3
#define regAFMT4_AFMT_AUDIO_DBG_DTO_CNTL 0x092e
#define regAFMT4_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX 3
#define regAFMT4_AFMT_MEM_PWR 0x092f
#define regAFMT4_AFMT_MEM_PWR_BASE_IDX 3
// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dme_dme_dispdec
// base address: 0x264f0
#define regDME4_DME_CONTROL 0x093c
#define regDME4_DME_CONTROL_BASE_IDX 3
#define regDME4_DME_MEMORY_CONTROL 0x093d
#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 3
// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
// base address: 0x264c4
#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931
#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3
#define regVPG4_VPG_GENERIC_PACKET_DATA 0x0932
#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 3
#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x0933
#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3
#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934
#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3
#define regVPG4_VPG_GENERIC_STATUS 0x0935
#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 3
#define regVPG4_VPG_MEM_PWR 0x0936
#define regVPG4_VPG_MEM_PWR_BASE_IDX 3
#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x0937
#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3
#define regVPG4_VPG_ISRC1_2_DATA 0x0938
#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 3
#define regVPG4_VPG_MPEG_INFO0 0x0939
#define regVPG4_VPG_MPEG_INFO0_BASE_IDX 3
#define regVPG4_VPG_MPEG_INFO1 0x093a
#define regVPG4_VPG_MPEG_INFO1_BASE_IDX 3
// addressBlock: dcn_dcec_hpo_hdmi_tb_enc0_dispdec
// base address: 0x2637c
#define regHDMI_TB_ENC_CONTROL 0x08df
#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3
#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0
#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3
#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1
#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3
#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2
#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3
#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3
#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3
#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4
#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3
#define regHDMI_TB_ENC_GC_CONTROL 0x08e5
#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9
#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea
#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb
#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec
#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed
#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee
#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef
#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3
#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0
#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3
#define regHDMI_TB_ENC_DB_CONTROL 0x08f1
#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3
#define regHDMI_TB_ENC_ACR_32_0 0x08f2
#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3
#define regHDMI_TB_ENC_ACR_32_1 0x08f3
#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3
#define regHDMI_TB_ENC_ACR_44_0 0x08f4
#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3
#define regHDMI_TB_ENC_ACR_44_1 0x08f5
#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3
#define regHDMI_TB_ENC_ACR_48_0 0x08f6
#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3
#define regHDMI_TB_ENC_ACR_48_1 0x08f7
#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3
#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8
#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3
#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9
#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3
#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb
#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3
#define regHDMI_TB_ENC_MEM_CTRL 0x08fe
#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3
#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff
#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3
#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900
#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3
#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901
#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3
#define regHDMI_TB_ENC_CRC_CNTL 0x0903
#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3
#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904
#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3
#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907
#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3
#define regHDMI_TB_ENC_MODE 0x0908
#define regHDMI_TB_ENC_MODE_BASE_IDX 3
#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909
#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3
#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a
#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3
// addressBlock: dcn_dcec_hpo_dp_stream_enc0_dispdec
// base address: 0x1ab8c
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624
#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625
#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2
#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628
#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc0_apg_apg_dispdec
// base address: 0x1abc0
#define regAPG0_APG_CONTROL 0x3630
#define regAPG0_APG_CONTROL_BASE_IDX 2
#define regAPG0_APG_CONTROL2 0x3631
#define regAPG0_APG_CONTROL2_BASE_IDX 2
#define regAPG0_APG_DBG_GEN_CONTROL 0x3632
#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2
#define regAPG0_APG_PACKET_CONTROL 0x3633
#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2
#define regAPG0_APG_DBG_ACP 0x3634
#define regAPG0_APG_DBG_ACP_BASE_IDX 2
#define regAPG0_APG_AUDIO_INFO 0x3635
#define regAPG0_APG_AUDIO_INFO_BASE_IDX 2
#define regAPG0_APG_DBG_AUDIO_INFO 0x3636
#define regAPG0_APG_DBG_AUDIO_INFO_BASE_IDX 2
#define regAPG0_APG_DBG_60958_0 0x3637
#define regAPG0_APG_DBG_60958_0_BASE_IDX 2
#define regAPG0_APG_DBG_60958_1 0x3638
#define regAPG0_APG_DBG_60958_1_BASE_IDX 2
#define regAPG0_APG_DBG_60958_2 0x3639
#define regAPG0_APG_DBG_60958_2_BASE_IDX 2
#define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a
#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2
#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b
#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2
#define regAPG0_APG_AUDIO_CRC_RESULT 0x363c
#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2
#define regAPG0_APG_DBG_RAMP_CONTROL0 0x363d
#define regAPG0_APG_DBG_RAMP_CONTROL0_BASE_IDX 2
#define regAPG0_APG_DBG_RAMP_CONTROL1 0x363e
#define regAPG0_APG_DBG_RAMP_CONTROL1_BASE_IDX 2
#define regAPG0_APG_DBG_RAMP_CONTROL2 0x363f
#define regAPG0_APG_DBG_RAMP_CONTROL2_BASE_IDX 2
#define regAPG0_APG_DBG_RAMP_CONTROL3 0x3640
#define regAPG0_APG_DBG_RAMP_CONTROL3_BASE_IDX 2
#define regAPG0_APG_STATUS 0x3641
#define regAPG0_APG_STATUS_BASE_IDX 2
#define regAPG0_APG_STATUS2 0x3642
#define regAPG0_APG_STATUS2_BASE_IDX 2
#define regAPG0_APG_DBG_AUDIO_DTO_CNTL 0x3643
#define regAPG0_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2
#define regAPG0_APG_MEM_PWR 0x3644
#define regAPG0_APG_MEM_PWR_BASE_IDX 2
#define regAPG0_APG_SPARE 0x3646
#define regAPG0_APG_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc0_dme_dme_dispdec
// base address: 0x1ac38
#define regDME5_DME_CONTROL 0x364e
#define regDME5_DME_CONTROL_BASE_IDX 2
#define regDME5_DME_MEMORY_CONTROL 0x364f
#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc0_vpg_vpg_dispdec
// base address: 0x1ac44
#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651
#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define regVPG5_VPG_GENERIC_PACKET_DATA 0x3652
#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x3653
#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654
#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define regVPG5_VPG_GENERIC_STATUS 0x3655
#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 2
#define regVPG5_VPG_MEM_PWR 0x3656
#define regVPG5_VPG_MEM_PWR_BASE_IDX 2
#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x3657
#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define regVPG5_VPG_ISRC1_2_DATA 0x3658
#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 2
#define regVPG5_VPG_MPEG_INFO0 0x3659
#define regVPG5_VPG_MPEG_INFO0_BASE_IDX 2
#define regVPG5_VPG_MPEG_INFO1 0x365a
#define regVPG5_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_sym32_enc0_dispdec
// base address: 0x1ac74
#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d
#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b
#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING 0x367f
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0 0x3680
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1 0x3681
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL 0x3682
#define regDP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x368b
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x368c
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x368d
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x368e
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x368f
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL 0x3690
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x3691
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS 0x3692
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL 0x3693
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x3694
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x3695
#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3696
#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x3697
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc1_dispdec
// base address: 0x1aedc
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8
#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9
#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2
#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc
#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc1_apg_apg_dispdec
// base address: 0x1af10
#define regAPG1_APG_CONTROL 0x3704
#define regAPG1_APG_CONTROL_BASE_IDX 2
#define regAPG1_APG_CONTROL2 0x3705
#define regAPG1_APG_CONTROL2_BASE_IDX 2
#define regAPG1_APG_DBG_GEN_CONTROL 0x3706
#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2
#define regAPG1_APG_PACKET_CONTROL 0x3707
#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2
#define regAPG1_APG_DBG_ACP 0x3708
#define regAPG1_APG_DBG_ACP_BASE_IDX 2
#define regAPG1_APG_AUDIO_INFO 0x3709
#define regAPG1_APG_AUDIO_INFO_BASE_IDX 2
#define regAPG1_APG_DBG_AUDIO_INFO 0x370a
#define regAPG1_APG_DBG_AUDIO_INFO_BASE_IDX 2
#define regAPG1_APG_DBG_60958_0 0x370b
#define regAPG1_APG_DBG_60958_0_BASE_IDX 2
#define regAPG1_APG_DBG_60958_1 0x370c
#define regAPG1_APG_DBG_60958_1_BASE_IDX 2
#define regAPG1_APG_DBG_60958_2 0x370d
#define regAPG1_APG_DBG_60958_2_BASE_IDX 2
#define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e
#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2
#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f
#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2
#define regAPG1_APG_AUDIO_CRC_RESULT 0x3710
#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2
#define regAPG1_APG_DBG_RAMP_CONTROL0 0x3711
#define regAPG1_APG_DBG_RAMP_CONTROL0_BASE_IDX 2
#define regAPG1_APG_DBG_RAMP_CONTROL1 0x3712
#define regAPG1_APG_DBG_RAMP_CONTROL1_BASE_IDX 2
#define regAPG1_APG_DBG_RAMP_CONTROL2 0x3713
#define regAPG1_APG_DBG_RAMP_CONTROL2_BASE_IDX 2
#define regAPG1_APG_DBG_RAMP_CONTROL3 0x3714
#define regAPG1_APG_DBG_RAMP_CONTROL3_BASE_IDX 2
#define regAPG1_APG_STATUS 0x3715
#define regAPG1_APG_STATUS_BASE_IDX 2
#define regAPG1_APG_STATUS2 0x3716
#define regAPG1_APG_STATUS2_BASE_IDX 2
#define regAPG1_APG_DBG_AUDIO_DTO_CNTL 0x3717
#define regAPG1_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2
#define regAPG1_APG_MEM_PWR 0x3718
#define regAPG1_APG_MEM_PWR_BASE_IDX 2
#define regAPG1_APG_SPARE 0x371a
#define regAPG1_APG_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc1_dme_dme_dispdec
// base address: 0x1af88
#define regDME6_DME_CONTROL 0x3722
#define regDME6_DME_CONTROL_BASE_IDX 2
#define regDME6_DME_MEMORY_CONTROL 0x3723
#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc1_vpg_vpg_dispdec
// base address: 0x1af94
#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725
#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3726
#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3727
#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728
#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define regVPG6_VPG_GENERIC_STATUS 0x3729
#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2
#define regVPG6_VPG_MEM_PWR 0x372a
#define regVPG6_VPG_MEM_PWR_BASE_IDX 2
#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x372b
#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define regVPG6_VPG_ISRC1_2_DATA 0x372c
#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2
#define regVPG6_VPG_MPEG_INFO0 0x372d
#define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2
#define regVPG6_VPG_MPEG_INFO1 0x372e
#define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_sym32_enc1_dispdec
// base address: 0x1afc4
#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731
#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f
#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING 0x3753
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0 0x3754
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1 0x3755
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL 0x3756
#define regDP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x375f
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3760
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x3761
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x3762
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x3763
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL 0x3764
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x3765
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS 0x3766
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL 0x3767
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x3768
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x3769
#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x376a
#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x376b
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc2_dispdec
// base address: 0x1b22c
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc
#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd
#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2
#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0
#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc2_apg_apg_dispdec
// base address: 0x1b260
#define regAPG2_APG_CONTROL 0x37d8
#define regAPG2_APG_CONTROL_BASE_IDX 2
#define regAPG2_APG_CONTROL2 0x37d9
#define regAPG2_APG_CONTROL2_BASE_IDX 2
#define regAPG2_APG_DBG_GEN_CONTROL 0x37da
#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2
#define regAPG2_APG_PACKET_CONTROL 0x37db
#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2
#define regAPG2_APG_DBG_ACP 0x37dc
#define regAPG2_APG_DBG_ACP_BASE_IDX 2
#define regAPG2_APG_AUDIO_INFO 0x37dd
#define regAPG2_APG_AUDIO_INFO_BASE_IDX 2
#define regAPG2_APG_DBG_AUDIO_INFO 0x37de
#define regAPG2_APG_DBG_AUDIO_INFO_BASE_IDX 2
#define regAPG2_APG_DBG_60958_0 0x37df
#define regAPG2_APG_DBG_60958_0_BASE_IDX 2
#define regAPG2_APG_DBG_60958_1 0x37e0
#define regAPG2_APG_DBG_60958_1_BASE_IDX 2
#define regAPG2_APG_DBG_60958_2 0x37e1
#define regAPG2_APG_DBG_60958_2_BASE_IDX 2
#define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2
#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2
#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3
#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2
#define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4
#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2
#define regAPG2_APG_DBG_RAMP_CONTROL0 0x37e5
#define regAPG2_APG_DBG_RAMP_CONTROL0_BASE_IDX 2
#define regAPG2_APG_DBG_RAMP_CONTROL1 0x37e6
#define regAPG2_APG_DBG_RAMP_CONTROL1_BASE_IDX 2
#define regAPG2_APG_DBG_RAMP_CONTROL2 0x37e7
#define regAPG2_APG_DBG_RAMP_CONTROL2_BASE_IDX 2
#define regAPG2_APG_DBG_RAMP_CONTROL3 0x37e8
#define regAPG2_APG_DBG_RAMP_CONTROL3_BASE_IDX 2
#define regAPG2_APG_STATUS 0x37e9
#define regAPG2_APG_STATUS_BASE_IDX 2
#define regAPG2_APG_STATUS2 0x37ea
#define regAPG2_APG_STATUS2_BASE_IDX 2
#define regAPG2_APG_DBG_AUDIO_DTO_CNTL 0x37eb
#define regAPG2_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2
#define regAPG2_APG_MEM_PWR 0x37ec
#define regAPG2_APG_MEM_PWR_BASE_IDX 2
#define regAPG2_APG_SPARE 0x37ee
#define regAPG2_APG_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc2_dme_dme_dispdec
// base address: 0x1b2d8
#define regDME7_DME_CONTROL 0x37f6
#define regDME7_DME_CONTROL_BASE_IDX 2
#define regDME7_DME_MEMORY_CONTROL 0x37f7
#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc2_vpg_vpg_dispdec
// base address: 0x1b2e4
#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9
#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define regVPG7_VPG_GENERIC_PACKET_DATA 0x37fa
#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb
#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc
#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define regVPG7_VPG_GENERIC_STATUS 0x37fd
#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2
#define regVPG7_VPG_MEM_PWR 0x37fe
#define regVPG7_VPG_MEM_PWR_BASE_IDX 2
#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x37ff
#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define regVPG7_VPG_ISRC1_2_DATA 0x3800
#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2
#define regVPG7_VPG_MPEG_INFO0 0x3801
#define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2
#define regVPG7_VPG_MPEG_INFO1 0x3802
#define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_sym32_enc2_dispdec
// base address: 0x1b314
#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805
#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813
#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING 0x3827
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0 0x3828
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1 0x3829
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL 0x382a
#define regDP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3833
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3834
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x3835
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x3836
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x3837
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL 0x3838
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x3839
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS 0x383a
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL 0x383b
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x383c
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x383d
#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x383e
#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x383f
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc3_dispdec
// base address: 0x1b57c
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0
#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1
#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4
#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc3_apg_apg_dispdec
// base address: 0x1b5b0
#define regAPG3_APG_CONTROL 0x38ac
#define regAPG3_APG_CONTROL_BASE_IDX 2
#define regAPG3_APG_CONTROL2 0x38ad
#define regAPG3_APG_CONTROL2_BASE_IDX 2
#define regAPG3_APG_DBG_GEN_CONTROL 0x38ae
#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2
#define regAPG3_APG_PACKET_CONTROL 0x38af
#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2
#define regAPG3_APG_DBG_ACP 0x38b0
#define regAPG3_APG_DBG_ACP_BASE_IDX 2
#define regAPG3_APG_AUDIO_INFO 0x38b1
#define regAPG3_APG_AUDIO_INFO_BASE_IDX 2
#define regAPG3_APG_DBG_AUDIO_INFO 0x38b2
#define regAPG3_APG_DBG_AUDIO_INFO_BASE_IDX 2
#define regAPG3_APG_DBG_60958_0 0x38b3
#define regAPG3_APG_DBG_60958_0_BASE_IDX 2
#define regAPG3_APG_DBG_60958_1 0x38b4
#define regAPG3_APG_DBG_60958_1_BASE_IDX 2
#define regAPG3_APG_DBG_60958_2 0x38b5
#define regAPG3_APG_DBG_60958_2_BASE_IDX 2
#define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6
#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2
#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7
#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2
#define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8
#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2
#define regAPG3_APG_DBG_RAMP_CONTROL0 0x38b9
#define regAPG3_APG_DBG_RAMP_CONTROL0_BASE_IDX 2
#define regAPG3_APG_DBG_RAMP_CONTROL1 0x38ba
#define regAPG3_APG_DBG_RAMP_CONTROL1_BASE_IDX 2
#define regAPG3_APG_DBG_RAMP_CONTROL2 0x38bb
#define regAPG3_APG_DBG_RAMP_CONTROL2_BASE_IDX 2
#define regAPG3_APG_DBG_RAMP_CONTROL3 0x38bc
#define regAPG3_APG_DBG_RAMP_CONTROL3_BASE_IDX 2
#define regAPG3_APG_STATUS 0x38bd
#define regAPG3_APG_STATUS_BASE_IDX 2
#define regAPG3_APG_STATUS2 0x38be
#define regAPG3_APG_STATUS2_BASE_IDX 2
#define regAPG3_APG_DBG_AUDIO_DTO_CNTL 0x38bf
#define regAPG3_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2
#define regAPG3_APG_MEM_PWR 0x38c0
#define regAPG3_APG_MEM_PWR_BASE_IDX 2
#define regAPG3_APG_SPARE 0x38c2
#define regAPG3_APG_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc3_dme_dme_dispdec
// base address: 0x1b628
#define regDME8_DME_CONTROL 0x38ca
#define regDME8_DME_CONTROL_BASE_IDX 2
#define regDME8_DME_MEMORY_CONTROL 0x38cb
#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_stream_enc3_vpg_vpg_dispdec
// base address: 0x1b634
#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd
#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define regVPG8_VPG_GENERIC_PACKET_DATA 0x38ce
#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf
#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0
#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define regVPG8_VPG_GENERIC_STATUS 0x38d1
#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2
#define regVPG8_VPG_MEM_PWR 0x38d2
#define regVPG8_VPG_MEM_PWR_BASE_IDX 2
#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x38d3
#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define regVPG8_VPG_ISRC1_2_DATA 0x38d4
#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2
#define regVPG8_VPG_MPEG_INFO0 0x38d5
#define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2
#define regVPG8_VPG_MPEG_INFO1 0x38d6
#define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_sym32_enc3_dispdec
// base address: 0x1b664
#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9
#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7
#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING 0x38fb
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0 0x38fc
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1 0x38fd
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL 0x38fe
#define regDP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3907
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3908
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x3909
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x390a
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x390b
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL 0x390c
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x390d
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS 0x390e
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL 0x390f
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x3910
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x3911
#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3912
#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3913
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_link_enc0_dispdec
// base address: 0x1ad7c
#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x369f
#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2
#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x36a0
#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_dphy_sym320_dispdec
// base address: 0x1add0
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36b4
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36b5
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0 0x36b6
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG1 0x36b7
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36b8
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36b9
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36ba
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36bb
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36bc
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4 0x36bd
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5 0x36be
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36bf
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36c0
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36c1
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36c2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4 0x36c3
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5 0x36c4
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36c5
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36c6
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36c7
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36c8
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4 0x36c9
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5 0x36ca
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0 0x36cb
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0 0x36cc
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1 0x36cd
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2 0x36ce
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3 0x36cf
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x36d0
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x36d1
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 0x36d2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL 0x36d3
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d4
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d5
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d6
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36d7
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36d8
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36d9
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36da
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36db
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36dc
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36dd
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36de
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36df
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e0
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e1
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e3
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e4
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e5
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 0x36e6
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x36e8
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x36e9
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x36ea
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_link_enc1_dispdec
// base address: 0x1b0cc
#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x3773
#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2
#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x3774
#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_dphy_sym321_dispdec
// base address: 0x1b120
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3788
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3789
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0 0x378a
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG1 0x378b
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x378c
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x378d
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x378e
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x378f
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3790
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4 0x3791
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5 0x3792
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x3793
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x3794
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x3795
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x3796
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4 0x3797
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5 0x3798
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x3799
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x379a
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x379b
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x379c
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4 0x379d
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5 0x379e
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0 0x379f
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0 0x37a0
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1 0x37a1
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2 0x37a2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3 0x37a3
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x37a4
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x37a5
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 0x37a6
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL 0x37a7
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37a8
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37a9
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37aa
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ab
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37ac
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37ad
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37ae
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37af
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b0
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b1
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b3
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b4
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b5
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b6
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37b7
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37b8
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37b9
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 0x37ba
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x37bc
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x37bd
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x37be
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_link_enc2_dispdec
// base address: 0x1b41c
#define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL 0x3847
#define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2
#define regDP_LINK_ENC2_DP_LINK_ENC_SPARE 0x3848
#define regDP_LINK_ENC2_DP_LINK_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_dphy_sym322_dispdec
// base address: 0x1b470
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL 0x385c
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS 0x385d
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0 0x385e
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG1 0x385f
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE 0x3860
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3861
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1 0x3862
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2 0x3863
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3864
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4 0x3865
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5 0x3866
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0 0x3867
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1 0x3868
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2 0x3869
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3 0x386a
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4 0x386b
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5 0x386c
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0 0x386d
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1 0x386e
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2 0x386f
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3 0x3870
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4 0x3871
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5 0x3872
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0 0x3873
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0 0x3874
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1 0x3875
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2 0x3876
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3 0x3877
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x3878
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x3879
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 0x387a
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL 0x387b
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG 0x387c
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0 0x387d
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1 0x387e
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2 0x387f
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3 0x3880
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE 0x3881
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0 0x3882
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1 0x3883
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2 0x3884
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3 0x3885
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4 0x3886
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5 0x3887
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6 0x3888
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7 0x3889
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8 0x388a
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9 0x388b
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10 0x388c
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS 0x388d
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 0x388e
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x3890
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x3891
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x3892
#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_link_enc3_dispdec
// base address: 0x1b76c
#define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL 0x391b
#define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2
#define regDP_LINK_ENC3_DP_LINK_ENC_SPARE 0x391c
#define regDP_LINK_ENC3_DP_LINK_ENC_SPARE_BASE_IDX 2
// addressBlock: dcn_dcec_hpo_dp_dphy_sym323_dispdec
// base address: 0x1b7c0
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL 0x3930
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS 0x3931
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0 0x3932
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG1 0x3933
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE 0x3934
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3935
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1 0x3936
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2 0x3937
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3938
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4 0x3939
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5 0x393a
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0 0x393b
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1 0x393c
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2 0x393d
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3 0x393e
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4 0x393f
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5 0x3940
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0 0x3941
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1 0x3942
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2 0x3943
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3 0x3944
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4 0x3945
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5 0x3946
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0 0x3947
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0 0x3948
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1 0x3949
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2 0x394a
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3 0x394b
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x394c
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x394d
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 0x394e
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL 0x394f
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG 0x3950
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0 0x3951
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1 0x3952
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2 0x3953
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3 0x3954
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE 0x3955
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0 0x3956
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1 0x3957
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2 0x3958
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3 0x3959
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4 0x395a
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5 0x395b
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6 0x395c
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7 0x395d
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8 0x395e
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9 0x395f
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10 0x3960
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS 0x3961
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 0x3962
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x3964
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x3965
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x3966
#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2
// addressBlock: dcn_dcec_dlpc_dlpc_dispdec
// base address: 0x0
#define regDLPC_ENABLE 0x2fe8
#define regDLPC_ENABLE_BASE_IDX 2
#define regDLPC_CURRENT_COUNT 0x2fe9
#define regDLPC_CURRENT_COUNT_BASE_IDX 2
#define regDLPC_OPTC_SNAPSHOT 0x2fea
#define regDLPC_OPTC_SNAPSHOT_BASE_IDX 2
#define regDLPC_PWRUP 0x2feb
#define regDLPC_PWRUP_BASE_IDX 2
#define regDLPC_OTG_RESYNC 0x2fec
#define regDLPC_OTG_RESYNC_BASE_IDX 2
#define regDLPC_DCN_ZSC_LONO_PWRUP 0x2fed
#define regDLPC_DCN_ZSC_LONO_PWRUP_BASE_IDX 2
#define regDLPC_SPARE 0x2fee
#define regDLPC_SPARE_BASE_IDX 2
#define regDLPC_COUNTER_INIT_VALUE 0x2fef
#define regDLPC_COUNTER_INIT_VALUE_BASE_IDX 2
// addressBlock: dcn_dpcssys_dpcssys_cr0_dispdec
// base address: 0x0
#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2
#define regDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
#define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dcn_dpcssys_dpcssys_cr1_dispdec
// base address: 0x360
#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2
#define regDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
#define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dcn_dpcssys_dpcssys_cr2_dispdec
// base address: 0x6c0
#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2
#define regDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
#define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dcn_dpcssys_dpcssys_cr3_dispdec
// base address: 0xa20
#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc
#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2
#define regDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd
#define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dcn_dpcssys_dpcs0_rdpcstx0_dispdec
// base address: 0x0
#define regRDPCSTX0_RDPCSTX_CNTL 0x2930
#define regRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
#define regRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932
#define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA 0x2933
#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2
#define regRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934
#define regRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define regRDPCSTX0_RDPCS_TX_CR_DATA 0x2935
#define regRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2
#define regRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936
#define regRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_SCRATCH0 0x2937
#define regRDPCSTX0_RDPCSTX_SCRATCH0_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_SPARE 0x2938
#define regRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_CNTL2 0x2939
#define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE 0x293a
#define regRDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL 0x293b
#define regRDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_CNTL4 0x293c
#define regRDPCSTX0_RDPCSTX_CNTL4_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d
#define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940
#define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941
#define regRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942
#define regRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943
#define regRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944
#define regRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945
#define regRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946
#define regRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947
#define regRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948
#define regRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949
#define regRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a
#define regRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b
#define regRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c
#define regRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d
#define regRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e
#define regRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f
#define regRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950
#define regRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951
#define regRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952
#define regRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953
#define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_SCRATCH1 0x2954
#define regRDPCSTX0_RDPCSTX_SCRATCH1_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_SCRATCH2 0x2955
#define regRDPCSTX0_RDPCSTX_SCRATCH2_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL15 0x2958
#define regRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL16 0x2959
#define regRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_PHY_CNTL17 0x295a
#define regRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX 2
#define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2 0x295b
#define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
#define regRDPCSTX0_RDPCS_CNTL3 0x295c
#define regRDPCSTX0_RDPCS_CNTL3_BASE_IDX 2
#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x295d
#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2
#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x295e
#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2
// addressBlock: dcn_dpcssys_dpcs0_rdpcstx1_dispdec
// base address: 0x360
#define regRDPCSTX1_RDPCSTX_CNTL 0x2a08
#define regRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09
#define regRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a
#define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA 0x2a0b
#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2
#define regRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c
#define regRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define regRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d
#define regRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2
#define regRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e
#define regRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_SCRATCH0 0x2a0f
#define regRDPCSTX1_RDPCSTX_SCRATCH0_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_SPARE 0x2a10
#define regRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_CNTL2 0x2a11
#define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE 0x2a12
#define regRDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL 0x2a13
#define regRDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_CNTL4 0x2a14
#define regRDPCSTX1_RDPCSTX_CNTL4_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15
#define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18
#define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19
#define regRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a
#define regRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b
#define regRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c
#define regRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d
#define regRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e
#define regRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f
#define regRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20
#define regRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21
#define regRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22
#define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23
#define regRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24
#define regRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25
#define regRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26
#define regRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27
#define regRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28
#define regRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29
#define regRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a
#define regRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b
#define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_SCRATCH1 0x2a2c
#define regRDPCSTX1_RDPCSTX_SCRATCH1_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_SCRATCH2 0x2a2d
#define regRDPCSTX1_RDPCSTX_SCRATCH2_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL15 0x2a30
#define regRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL16 0x2a31
#define regRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_PHY_CNTL17 0x2a32
#define regRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX 2
#define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2 0x2a33
#define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
#define regRDPCSTX1_RDPCS_CNTL3 0x2a34
#define regRDPCSTX1_RDPCS_CNTL3_BASE_IDX 2
#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2a35
#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2
#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2a36
#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2
// addressBlock: dcn_dpcssys_dpcs0_rdpcstx2_dispdec
// base address: 0x6c0
#define regRDPCSTX2_RDPCSTX_CNTL 0x2ae0
#define regRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1
#define regRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2
#define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA 0x2ae3
#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2
#define regRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4
#define regRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define regRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5
#define regRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2
#define regRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6
#define regRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_SCRATCH0 0x2ae7
#define regRDPCSTX2_RDPCSTX_SCRATCH0_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_SPARE 0x2ae8
#define regRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_CNTL2 0x2ae9
#define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE 0x2aea
#define regRDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL 0x2aeb
#define regRDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_CNTL4 0x2aec
#define regRDPCSTX2_RDPCSTX_CNTL4_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed
#define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0
#define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1
#define regRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3
#define regRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4
#define regRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5
#define regRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6
#define regRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7
#define regRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8
#define regRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9
#define regRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa
#define regRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb
#define regRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc
#define regRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd
#define regRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe
#define regRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff
#define regRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00
#define regRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01
#define regRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02
#define regRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03
#define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_SCRATCH1 0x2b04
#define regRDPCSTX2_RDPCSTX_SCRATCH1_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_SCRATCH2 0x2b05
#define regRDPCSTX2_RDPCSTX_SCRATCH2_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL15 0x2b08
#define regRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL16 0x2b09
#define regRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_PHY_CNTL17 0x2b0a
#define regRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX 2
#define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2 0x2b0b
#define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
#define regRDPCSTX2_RDPCS_CNTL3 0x2b0c
#define regRDPCSTX2_RDPCS_CNTL3_BASE_IDX 2
#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2b0d
#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2
#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2b0e
#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2
// addressBlock: dcn_dpcssys_dpcs0_rdpcstx3_dispdec
// base address: 0xa20
#define regRDPCSTX3_RDPCSTX_CNTL 0x2bb8
#define regRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9
#define regRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba
#define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA 0x2bbb
#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2
#define regRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc
#define regRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define regRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd
#define regRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2
#define regRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe
#define regRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_SCRATCH0 0x2bbf
#define regRDPCSTX3_RDPCSTX_SCRATCH0_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_SPARE 0x2bc0
#define regRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_CNTL2 0x2bc1
#define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE 0x2bc2
#define regRDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL 0x2bc3
#define regRDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_CNTL4 0x2bc4
#define regRDPCSTX3_RDPCSTX_CNTL4_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5
#define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8
#define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9
#define regRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca
#define regRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb
#define regRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc
#define regRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd
#define regRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce
#define regRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf
#define regRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0
#define regRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1
#define regRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3
#define regRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4
#define regRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5
#define regRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6
#define regRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7
#define regRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8
#define regRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9
#define regRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda
#define regRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb
#define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_SCRATCH1 0x2bdc
#define regRDPCSTX3_RDPCSTX_SCRATCH1_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_SCRATCH2 0x2bdd
#define regRDPCSTX3_RDPCSTX_SCRATCH2_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL15 0x2be0
#define regRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL16 0x2be1
#define regRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL17 0x2be2
#define regRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX 2
#define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2 0x2be3
#define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
#define regRDPCSTX3_RDPCS_CNTL3 0x2be4
#define regRDPCSTX3_RDPCS_CNTL3_BASE_IDX 2
#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2be5
#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2
#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2be6
#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2
// addressBlock: dcn_dcec_host_hda_azcontroller_azdec
// base address: 0x0
#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x0000
#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 0
#define regAZCONTROLLER0_CORB_READ_POINTER 0x0000
#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 0
#define regAZCONTROLLER0_CORB_CONTROL 0x0001
#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 0
#define regAZCONTROLLER0_CORB_STATUS 0x0001
#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 0
#define regAZCONTROLLER0_CORB_SIZE 0x0001
#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x0002
#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x0003
#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x0004
#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 0
#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x0004
#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_CONTROL 0x0005
#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_STATUS 0x0005
#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_SIZE 0x0005
#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x0008
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0
#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a
#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b
#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x074c
#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
// addressBlock: dcn_dcec_host_hda_azendpoint_azdec
// base address: 0x0
#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
// addressBlock: dcn_dcec_host_hda_azinputendpoint_azdec
// base address: 0x0
#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
// addressBlock: dcn_dcec_host_hda_azroot_azdec
// base address: 0x0
#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
// addressBlock: dcn_dcec_host_hda_azstream0_azdec
// base address: 0x0
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dcn_dcec_host_hda_azstream1_azdec
// base address: 0x20
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dcn_dcec_host_hda_azstream2_azdec
// base address: 0x40
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dcn_dcec_host_hda_azstream3_azdec
// base address: 0x60
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dcn_dcec_host_hda_azstream4_azdec
// base address: 0x80
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dcn_dcec_host_hda_azstream5_azdec
// base address: 0xa0
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dcn_dcec_host_hda_azstream6_azdec
// base address: 0xc0
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dcn_dcec_host_hda_azstream7_azdec
// base address: 0xe0
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dcn_dcec_hda_azcontroller_azdec
// base address: 0x1300000
#define regGLOBAL_CAPABILITIES 0x4b7000
#define regGLOBAL_CAPABILITIES_BASE_IDX 3
#define regMINOR_VERSION 0x4b7000
#define regMINOR_VERSION_BASE_IDX 3
#define regMAJOR_VERSION 0x4b7000
#define regMAJOR_VERSION_BASE_IDX 3
#define regOUTPUT_PAYLOAD_CAPABILITY 0x4b7001
#define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3
#define regINPUT_PAYLOAD_CAPABILITY 0x4b7001
#define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX 3
#define regGLOBAL_CONTROL 0x4b7002
#define regGLOBAL_CONTROL_BASE_IDX 3
#define regWAKE_ENABLE 0x4b7003
#define regWAKE_ENABLE_BASE_IDX 3
#define regSTATE_CHANGE_STATUS 0x4b7003
#define regSTATE_CHANGE_STATUS_BASE_IDX 3
#define regGLOBAL_STATUS 0x4b7004
#define regGLOBAL_STATUS_BASE_IDX 3
#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006
#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3
#define regINPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006
#define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3
#define regINTERRUPT_CONTROL 0x4b7008
#define regINTERRUPT_CONTROL_BASE_IDX 3
#define regINTERRUPT_STATUS 0x4b7009
#define regINTERRUPT_STATUS_BASE_IDX 3
#define regWALL_CLOCK_COUNTER 0x4b700c
#define regWALL_CLOCK_COUNTER_BASE_IDX 3
#define regSTREAM_SYNCHRONIZATION 0x4b700e
#define regSTREAM_SYNCHRONIZATION_BASE_IDX 3
#define regCORB_LOWER_BASE_ADDRESS 0x4b7010
#define regCORB_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regCORB_UPPER_BASE_ADDRESS 0x4b7011
#define regCORB_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZCONTROLLER1_CORB_WRITE_POINTER 0x4b7012
#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 3
#define regAZCONTROLLER1_CORB_READ_POINTER 0x4b7012
#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 3
#define regAZCONTROLLER1_CORB_CONTROL 0x4b7013
#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 3
#define regAZCONTROLLER1_CORB_STATUS 0x4b7013
#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 3
#define regAZCONTROLLER1_CORB_SIZE 0x4b7013
#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 3
#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x4b7014
#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x4b7015
#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x4b7016
#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 3
#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x4b7016
#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3
#define regAZCONTROLLER1_RIRB_CONTROL 0x4b7017
#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 3
#define regAZCONTROLLER1_RIRB_STATUS 0x4b7017
#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 3
#define regAZCONTROLLER1_RIRB_SIZE 0x4b7017
#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 3
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3
#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019
#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x4b701a
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3
#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c
#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d
#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x4b780c
#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azendpoint_azdec
// base address: 0x1300000
#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018
#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3
#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018
#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azinputendpoint_azdec
// base address: 0x1300000
#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018
#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3
#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018
#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azroot_azdec
// base address: 0x1300000
#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018
#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3
#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018
#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azstream0_azdec
// base address: 0x1300000
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7020
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7021
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7022
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7023
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7024
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7024
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7026
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7027
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7821
#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azstream1_azdec
// base address: 0x1300020
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7028
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7029
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b702a
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b702b
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b702c
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b702c
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b702e
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b702f
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7829
#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azstream2_azdec
// base address: 0x1300040
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7030
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7031
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7032
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7033
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7034
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7034
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7036
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7037
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7831
#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azstream3_azdec
// base address: 0x1300060
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7038
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7039
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b703a
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b703b
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b703c
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b703c
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b703e
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b703f
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7839
#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azstream4_azdec
// base address: 0x1300080
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7040
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7041
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7042
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7043
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7044
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7044
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7046
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7047
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7841
#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azstream5_azdec
// base address: 0x13000a0
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7048
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7049
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b704a
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b704b
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b704c
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b704c
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b704e
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b704f
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7849
#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azstream6_azdec
// base address: 0x13000c0
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7050
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7051
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7052
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7053
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7054
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7054
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7056
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7057
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7851
#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3
// addressBlock: dcn_dcec_hda_azstream7_azdec
// base address: 0x13000e0
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7058
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7059
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b705a
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b705b
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b705c
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b705c
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b705e
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b705f
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7859
#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3
// addressBlock: dcn_dcec_dio_hdcp1kp_pkdbdec
// base address: 0x32000000
// addressBlock: cnvc_cfg_cnvc_cfgdebugind
// base address: 0x0
#define ixID2_CNVC_FLOW_CONTROL 0x0002
#define ixID4_CNVC_FLOW_CONTROL_2 0x0004
#define ixID5_CNVC_REG_TO_FP_INPUT 0x0005
#define ixID6_CNVC_REG_TO_FP_OUTPUT_UPPER_0 0x0006
#define ixID7_CNVC_REG_TO_FP_OUTPUT_LOWER_0 0x0007
#define ixID8_CNVC_REG_TO_FP_OUTPUT_UPPER_1 0x0008
#define ixID9_CNVC_REG_TO_FP_OUTPUT_LOWER_1 0x0009
// addressBlock: cm_cmdebugind
// base address: 0x0
#define ixID1_CM_FLOW_CONTROL 0x0001
#define ixID2_CM_BYPASS 0x0002
#define ixID3_CM_REG_TO_FP_CSC_INPUT 0x0003
#define ixID4_CM_REG_TO_FP_CSC_OUTPUT_UPPER_0 0x0004
#define ixID5_CM_REG_TO_FP_CSC_OUTPUT_LOWER_0 0x0005
#define ixID6_CM_REG_TO_FP_BIAS_INPUT 0x0006
#define ixID7_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_0 0x0007
#define ixID8_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_0 0x0008
#define ixID9_CM_STATUS 0x0009
#define ixIDA_CM_REG_TO_FP_CSC_OUTPUT_UPPER_1 0x000a
#define ixIDB_CM_REG_TO_FP_CSC_OUTPUT_LOWER_1 0x000b
#define ixIDC_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_1 0x000c
#define ixIDD_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_1 0x000d
// addressBlock: mcif_wb0_mcif_wbdebugind
// base address: 0x0
#define ixID01_WB_FMT_DBG 0x0001
#define ixID02_WB_FMT_DBG 0x0002
#define ixID03_WB_FMT_DBG 0x0003
#define ixID04_WB_MGR_DBG 0x0004
#define ixID05_WB_MGR_DBG 0x0005
#define ixID06_WB_MGR_DBG 0x0006
#define ixID07_WB_MGR_DBG 0x0007
#define ixID08_WB_ARB_DBG 0x0008
#define ixID09_WB_ARB_DBG 0x0009
#define ixID0A_WB_ARB_DBG 0x000a
#define ixID0B_WB_ARB_DBG 0x000b
#define ixID0C_WB_ARB_DBG 0x000c
#define ixID0D_WB_ARB_DBG 0x000d
#define ixID0E_WB_ARB_DBG 0x000e
#define ixID0F_P010_WB_FMT_DBG_Y 0x000f
#define ixID10_P010_WB_FMT_DBG_C 0x0010
#define ixID11_WB_ARB_P010_DBG 0x0011
#define ixID12_WB_ARB_P010_DBG 0x0012
// addressBlock: mpc_ocsc_mpc_ocscdebugind
// base address: 0x0
#define ixID1_MPC_OUT0_CSC_MODE_DB 0x0001
#define ixID2_MPC_OUT1_CSC_MODE_DB 0x0002
#define ixID3_MPC_OUT2_CSC_MODE_DB 0x0003
#define ixID4_MPC_OUT3_CSC_MODE_DB 0x0004
// addressBlock: mpcc0_mpccdebugind
// base address: 0x0
#define ixMPCC0_ID01_MPCC_SEL_DB 0x0001
#define ixMPCC0_ID02_MPCC_TOP_GAIN_DB 0x0002
#define ixMPCC0_ID03_MPCC_BOT_GAIN_INSIDE_DB 0x0003
#define ixMPCC0_ID04_MPCC_BOT_GAIN_OUTSIDE_DB 0x0004
#define ixMPCC0_ID05_MPCC_BG_R_CR_DB 0x0005
#define ixMPCC0_ID06_MPCC_BG_G_Y_DB 0x0006
#define ixMPCC0_ID07_MPCC_BG_B_CB_DB 0x0007
#define ixMPCC0_ID08_MPCC_CONTROL_DB 0x0008
#define ixMPCC0_ID09_MPCC_SM_CONTROL_DB 0x0009
#define ixMPCC0_ID17_MPCC_TOP_PIX 0x0011
#define ixMPCC0_ID18_MPCC_recout_start 0x0012
#define ixMPCC0_ID19_MPCC_recout_size 0x0013
#define ixMPCC0_ID20_MPCC_mpc_size 0x0014
#define ixMPCC0_ID21_MPCC_TOP_sideband 0x0015
#define ixMPCC0_ID22_MPCC_BOT_PIX 0x0016
#define ixMPCC0_ID23_MPCC_BOT_sideband 0x0017
#define ixMPCC0_ID24_MPCC_OPP_PIX 0x0018
#define ixMPCC0_ID25_MPCC_OPP_sideband 0x0019
// addressBlock: mpcc1_mpccdebugind
// base address: 0x0
#define ixMPCC1_ID01_MPCC_SEL_DB 0x0001
#define ixMPCC1_ID02_MPCC_TOP_GAIN_DB 0x0002
#define ixMPCC1_ID03_MPCC_BOT_GAIN_INSIDE_DB 0x0003
#define ixMPCC1_ID04_MPCC_BOT_GAIN_OUTSIDE_DB 0x0004
#define ixMPCC1_ID05_MPCC_BG_R_CR_DB 0x0005
#define ixMPCC1_ID06_MPCC_BG_G_Y_DB 0x0006
#define ixMPCC1_ID07_MPCC_BG_B_CB_DB 0x0007
#define ixMPCC1_ID08_MPCC_CONTROL_DB 0x0008
#define ixMPCC1_ID09_MPCC_SM_CONTROL_DB 0x0009
#define ixMPCC1_ID17_MPCC_TOP_PIX 0x0011
#define ixMPCC1_ID18_MPCC_recout_start 0x0012
#define ixMPCC1_ID19_MPCC_recout_size 0x0013
#define ixMPCC1_ID20_MPCC_mpc_size 0x0014
#define ixMPCC1_ID21_MPCC_TOP_sideband 0x0015
#define ixMPCC1_ID22_MPCC_BOT_PIX 0x0016
#define ixMPCC1_ID23_MPCC_BOT_sideband 0x0017
#define ixMPCC1_ID24_MPCC_OPP_PIX 0x0018
#define ixMPCC1_ID25_MPCC_OPP_sideband 0x0019
// addressBlock: mpcc2_mpccdebugind
// base address: 0x0
#define ixMPCC2_ID01_MPCC_SEL_DB 0x0001
#define ixMPCC2_ID02_MPCC_TOP_GAIN_DB 0x0002
#define ixMPCC2_ID03_MPCC_BOT_GAIN_INSIDE_DB 0x0003
#define ixMPCC2_ID04_MPCC_BOT_GAIN_OUTSIDE_DB 0x0004
#define ixMPCC2_ID05_MPCC_BG_R_CR_DB 0x0005
#define ixMPCC2_ID06_MPCC_BG_G_Y_DB 0x0006
#define ixMPCC2_ID07_MPCC_BG_B_CB_DB 0x0007
#define ixMPCC2_ID08_MPCC_CONTROL_DB 0x0008
#define ixMPCC2_ID09_MPCC_SM_CONTROL_DB 0x0009
#define ixMPCC2_ID17_MPCC_TOP_PIX 0x0011
#define ixMPCC2_ID18_MPCC_recout_start 0x0012
#define ixMPCC2_ID19_MPCC_recout_size 0x0013
#define ixMPCC2_ID20_MPCC_mpc_size 0x0014
#define ixMPCC2_ID21_MPCC_TOP_sideband 0x0015
#define ixMPCC2_ID22_MPCC_BOT_PIX 0x0016
#define ixMPCC2_ID23_MPCC_BOT_sideband 0x0017
#define ixMPCC2_ID24_MPCC_OPP_PIX 0x0018
#define ixMPCC2_ID25_MPCC_OPP_sideband 0x0019
// addressBlock: mpcc3_mpccdebugind
// base address: 0x0
#define ixMPCC3_ID01_MPCC_SEL_DB 0x0001
#define ixMPCC3_ID02_MPCC_TOP_GAIN_DB 0x0002
#define ixMPCC3_ID03_MPCC_BOT_GAIN_INSIDE_DB 0x0003
#define ixMPCC3_ID04_MPCC_BOT_GAIN_OUTSIDE_DB 0x0004
#define ixMPCC3_ID05_MPCC_BG_R_CR_DB 0x0005
#define ixMPCC3_ID06_MPCC_BG_G_Y_DB 0x0006
#define ixMPCC3_ID07_MPCC_BG_B_CB_DB 0x0007
#define ixMPCC3_ID08_MPCC_CONTROL_DB 0x0008
#define ixMPCC3_ID09_MPCC_SM_CONTROL_DB 0x0009
#define ixMPCC3_ID17_MPCC_TOP_PIX 0x0011
#define ixMPCC3_ID18_MPCC_recout_start 0x0012
#define ixMPCC3_ID19_MPCC_recout_size 0x0013
#define ixMPCC3_ID20_MPCC_mpc_size 0x0014
#define ixMPCC3_ID21_MPCC_TOP_sideband 0x0015
#define ixMPCC3_ID22_MPCC_BOT_PIX 0x0016
#define ixMPCC3_ID23_MPCC_BOT_sideband 0x0017
#define ixMPCC3_ID24_MPCC_OPP_PIX 0x0018
#define ixMPCC3_ID25_MPCC_OPP_sideband 0x0019
// addressBlock: mpcc_ogam0_mpcc_ogamdebugind
// base address: 0x0
#define ixMPCC_OGAM0_ID01_MPCC_OGAM_CONTROL 0x0001
// addressBlock: mpcc_mcm0_mpcc_mcmdebugind
// base address: 0x0
#define ixMPCC_MCM0_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER 0x0008
#define ixMPCC_MCM0_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER 0x0009
#define ixMPCC_MCM0_ID10_MPCC_MCM_R2F_3DLUT 0x000a
#define ixMPCC_MCM0_ID11_MPCC_MCM_FIRST_GAMUT_REMAP 0x000b
#define ixMPCC_MCM0_ID12_MPCC_MCM_SECOND_GAMUT_REMAP 0x000c
// addressBlock: mpcc_ogam1_mpcc_ogamdebugind
// base address: 0x0
#define ixMPCC_OGAM1_ID01_MPCC_OGAM_CONTROL 0x0001
// addressBlock: mpcc_mcm1_mpcc_mcmdebugind
// base address: 0x0
#define ixMPCC_MCM1_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER 0x0008
#define ixMPCC_MCM1_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER 0x0009
#define ixMPCC_MCM1_ID10_MPCC_MCM_R2F_3DLUT 0x000a
#define ixMPCC_MCM1_ID11_MPCC_MCM_FIRST_GAMUT_REMAP 0x000b
#define ixMPCC_MCM1_ID12_MPCC_MCM_SECOND_GAMUT_REMAP 0x000c
// addressBlock: mpcc_ogam2_mpcc_ogamdebugind
// base address: 0x0
#define ixMPCC_OGAM2_ID01_MPCC_OGAM_CONTROL 0x0001
// addressBlock: mpcc_mcm2_mpcc_mcmdebugind
// base address: 0x0
#define ixMPCC_MCM2_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER 0x0008
#define ixMPCC_MCM2_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER 0x0009
#define ixMPCC_MCM2_ID10_MPCC_MCM_R2F_3DLUT 0x000a
#define ixMPCC_MCM2_ID11_MPCC_MCM_FIRST_GAMUT_REMAP 0x000b
#define ixMPCC_MCM2_ID12_MPCC_MCM_SECOND_GAMUT_REMAP 0x000c
// addressBlock: mpcc_ogam3_mpcc_ogamdebugind
// base address: 0x0
#define ixMPCC_OGAM3_ID01_MPCC_OGAM_CONTROL 0x0001
// addressBlock: mpcc_mcm3_mpcc_mcmdebugind
// base address: 0x0
#define ixMPCC_MCM3_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER 0x0008
#define ixMPCC_MCM3_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER 0x0009
#define ixMPCC_MCM3_ID10_MPCC_MCM_R2F_3DLUT 0x000a
#define ixMPCC_MCM3_ID11_MPCC_MCM_FIRST_GAMUT_REMAP 0x000b
#define ixMPCC_MCM3_ID12_MPCC_MCM_SECOND_GAMUT_REMAP 0x000c
// addressBlock: otg0_otgdebugind
// base address: 0x0
#define ixOTG0_OTG_DBG_DATA1 0x0001
#define ixOTG0_OTG_DBG_DATA2 0x0002
#define ixOTG0_OTG_DBG_DATA3 0x0003
#define ixOTG0_OTG_DBG_DATA4 0x0004
#define ixOTG0_OTG_DBG_DATA5 0x0005
#define ixOTG0_OTG_DBG_DATA6 0x0006
#define ixOTG0_OTG_DBG_DATA7 0x0007
#define ixOTG0_OTG_DBG_DATA8 0x0008
#define ixOTG0_OTG_DBG_DATA9 0x0009
#define ixOTG0_OTG_DBG_DATA10 0x000a
#define ixOTG0_OTG_SCL_INTERFACE 0x0042
#define ixOTG0_OTG_DOUT_INTERFACE_01_A 0x0043
#define ixOTG0_OTG_DOUT_INTERFACE_01_B 0x0044
#define ixOTG0_OTG_DOUT_INTERFACE_02 0x0045
// addressBlock: otg1_otgdebugind
// base address: 0x0
#define ixOTG1_OTG_DBG_DATA1 0x0001
#define ixOTG1_OTG_DBG_DATA2 0x0002
#define ixOTG1_OTG_DBG_DATA3 0x0003
#define ixOTG1_OTG_DBG_DATA4 0x0004
#define ixOTG1_OTG_DBG_DATA5 0x0005
#define ixOTG1_OTG_DBG_DATA6 0x0006
#define ixOTG1_OTG_DBG_DATA7 0x0007
#define ixOTG1_OTG_DBG_DATA8 0x0008
#define ixOTG1_OTG_DBG_DATA9 0x0009
#define ixOTG1_OTG_DBG_DATA10 0x000a
#define ixOTG1_OTG_SCL_INTERFACE 0x0042
#define ixOTG1_OTG_DOUT_INTERFACE_01_A 0x0043
#define ixOTG1_OTG_DOUT_INTERFACE_01_B 0x0044
#define ixOTG1_OTG_DOUT_INTERFACE_02 0x0045
// addressBlock: otg2_otgdebugind
// base address: 0x0
#define ixOTG2_OTG_DBG_DATA1 0x0001
#define ixOTG2_OTG_DBG_DATA2 0x0002
#define ixOTG2_OTG_DBG_DATA3 0x0003
#define ixOTG2_OTG_DBG_DATA4 0x0004
#define ixOTG2_OTG_DBG_DATA5 0x0005
#define ixOTG2_OTG_DBG_DATA6 0x0006
#define ixOTG2_OTG_DBG_DATA7 0x0007
#define ixOTG2_OTG_DBG_DATA8 0x0008
#define ixOTG2_OTG_DBG_DATA9 0x0009
#define ixOTG2_OTG_DBG_DATA10 0x000a
#define ixOTG2_OTG_SCL_INTERFACE 0x0042
#define ixOTG2_OTG_DOUT_INTERFACE_01_A 0x0043
#define ixOTG2_OTG_DOUT_INTERFACE_01_B 0x0044
#define ixOTG2_OTG_DOUT_INTERFACE_02 0x0045
#define ixDCIO_DEBUG_ID 0x0000
#define ixDCIO_DEBUG1B 0x001b
#define ixDCIO_DEBUG1C 0x001c
#define ixDCIO_DEBUG1D 0x001d
#define ixDCIO_DEBUG1E 0x001e
#define ixDCIO_DEBUG1F 0x001f
#define ixDCIO_DEBUG20 0x0020
#define ixDCIO_DEBUG21 0x0021
#define ixDCIO_DEBUG22 0x0022
// addressBlock: otg3_otgdebugind
// base address: 0x0
#define ixOTG3_OTG_DBG_DATA1 0x0001
#define ixOTG3_OTG_DBG_DATA2 0x0002
#define ixOTG3_OTG_DBG_DATA3 0x0003
#define ixOTG3_OTG_DBG_DATA4 0x0004
#define ixOTG3_OTG_DBG_DATA5 0x0005
#define ixOTG3_OTG_DBG_DATA6 0x0006
#define ixOTG3_OTG_DBG_DATA7 0x0007
#define ixOTG3_OTG_DBG_DATA8 0x0008
#define ixOTG3_OTG_DBG_DATA9 0x0009
#define ixOTG3_OTG_DBG_DATA10 0x000a
#define ixOTG3_OTG_SCL_INTERFACE 0x0042
#define ixOTG3_OTG_DOUT_INTERFACE_01_A 0x0043
#define ixOTG3_OTG_DOUT_INTERFACE_01_B 0x0044
#define ixOTG3_OTG_DOUT_INTERFACE_02 0x0045
// addressBlock: azendpoint_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
#define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX 0x3774
#define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA 0x3775
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
// addressBlock: azendpoint_descriptorind
// base address: 0x0
#define ixAUDIO_DESCRIPTOR0 0x0001
#define ixAUDIO_DESCRIPTOR1 0x0002
#define ixAUDIO_DESCRIPTOR2 0x0003
#define ixAUDIO_DESCRIPTOR3 0x0004
#define ixAUDIO_DESCRIPTOR4 0x0005
#define ixAUDIO_DESCRIPTOR5 0x0006
#define ixAUDIO_DESCRIPTOR6 0x0007
#define ixAUDIO_DESCRIPTOR7 0x0008
#define ixAUDIO_DESCRIPTOR8 0x0009
#define ixAUDIO_DESCRIPTOR9 0x000a
#define ixAUDIO_DESCRIPTOR10 0x000b
#define ixAUDIO_DESCRIPTOR11 0x000c
#define ixAUDIO_DESCRIPTOR12 0x000d
#define ixAUDIO_DESCRIPTOR13 0x000e
// addressBlock: azendpoint_sinkinfoind
// base address: 0x0
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
#define ixSINK_DESCRIPTION0 0x0005
#define ixSINK_DESCRIPTION1 0x0006
#define ixSINK_DESCRIPTION2 0x0007
#define ixSINK_DESCRIPTION3 0x0008
#define ixSINK_DESCRIPTION4 0x0009
#define ixSINK_DESCRIPTION5 0x000a
#define ixSINK_DESCRIPTION6 0x000b
#define ixSINK_DESCRIPTION7 0x000c
#define ixSINK_DESCRIPTION8 0x000d
#define ixSINK_DESCRIPTION9 0x000e
#define ixSINK_DESCRIPTION10 0x000f
#define ixSINK_DESCRIPTION11 0x0010
#define ixSINK_DESCRIPTION12 0x0011
#define ixSINK_DESCRIPTION13 0x0012
#define ixSINK_DESCRIPTION14 0x0013
#define ixSINK_DESCRIPTION15 0x0014
#define ixSINK_DESCRIPTION16 0x0015
#define ixSINK_DESCRIPTION17 0x0016
// addressBlock: azf0controller_azinputcrc0resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
// addressBlock: azf0controller_azinputcrc1resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
// addressBlock: azf0controller_azcrc0resultind
// base address: 0x0
#define ixAZALIA_CRC0_CHANNEL0 0x0000
#define ixAZALIA_CRC0_CHANNEL1 0x0001
#define ixAZALIA_CRC0_CHANNEL2 0x0002
#define ixAZALIA_CRC0_CHANNEL3 0x0003
#define ixAZALIA_CRC0_CHANNEL4 0x0004
#define ixAZALIA_CRC0_CHANNEL5 0x0005
#define ixAZALIA_CRC0_CHANNEL6 0x0006
#define ixAZALIA_CRC0_CHANNEL7 0x0007
// addressBlock: azf0controller_azcrc1resultind
// base address: 0x0
#define ixAZALIA_CRC1_CHANNEL0 0x0000
#define ixAZALIA_CRC1_CHANNEL1 0x0001
#define ixAZALIA_CRC1_CHANNEL2 0x0002
#define ixAZALIA_CRC1_CHANNEL3 0x0003
#define ixAZALIA_CRC1_CHANNEL4 0x0004
#define ixAZALIA_CRC1_CHANNEL5 0x0005
#define ixAZALIA_CRC1_CHANNEL6 0x0006
#define ixAZALIA_CRC1_CHANNEL7 0x0007
// addressBlock: azinputendpoint_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
// addressBlock: azroot_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
// addressBlock: azf0stream0_streamind
// base address: 0x0
#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream1_streamind
// base address: 0x0
#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream2_streamind
// base address: 0x0
#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream3_streamind
// base address: 0x0
#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream4_streamind
// base address: 0x0
#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream5_streamind
// base address: 0x0
#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream6_streamind
// base address: 0x0
#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream7_streamind
// base address: 0x0
#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream8_streamind
// base address: 0x0
#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream9_streamind
// base address: 0x0
#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream10_streamind
// base address: 0x0
#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream11_streamind
// base address: 0x0
#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream12_streamind
// base address: 0x0
#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream13_streamind
// base address: 0x0
#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream14_streamind
// base address: 0x0
#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream15_streamind
// base address: 0x0
#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0endpoint0_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
#define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070
// addressBlock: azf0endpoint1_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
#define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070
// addressBlock: azf0endpoint2_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
#define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070
// addressBlock: azf0endpoint3_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
#define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070
// addressBlock: azf0endpoint4_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
#define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070
// addressBlock: azf0endpoint5_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
#define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070
// addressBlock: azf0endpoint6_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
#define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070
// addressBlock: azf0endpoint7_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
#define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070
// addressBlock: azf0inputendpoint0_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint1_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint2_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint3_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint4_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint5_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint6_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint7_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
#endif
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