linux/arch/x86/xen/pmu.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/types.h>
#include <linux/interrupt.h>

#include <asm/xen/hypercall.h>
#include <xen/xen.h>
#include <xen/page.h>
#include <xen/interface/xen.h>
#include <xen/interface/vcpu.h>
#include <xen/interface/xenpmu.h>

#include "xen-ops.h"

/* x86_pmu.handle_irq definition */
#include "../events/perf_event.h"

#define XENPMU_IRQ_PROCESSING
struct xenpmu {};
static DEFINE_PER_CPU(struct xenpmu, xenpmu_shared);
#define get_xenpmu_data()
#define get_xenpmu_flags()

/* Macro for computing address of a PMU MSR bank */
#define field_offset(ctxt, field)

/* AMD PMU */
#define F15H_NUM_COUNTERS
#define F10H_NUM_COUNTERS

static __read_mostly uint32_t amd_counters_base;
static __read_mostly uint32_t amd_ctrls_base;
static __read_mostly int amd_msr_step;
static __read_mostly int k7_counters_mirrored;
static __read_mostly int amd_num_counters;

/* Intel PMU */
#define MSR_TYPE_COUNTER
#define MSR_TYPE_CTRL
#define MSR_TYPE_GLOBAL
#define MSR_TYPE_ARCH_COUNTER
#define MSR_TYPE_ARCH_CTRL

/* Number of general pmu registers (CPUID.EAX[0xa].EAX[8..15]) */
#define PMU_GENERAL_NR_SHIFT
#define PMU_GENERAL_NR_BITS
#define PMU_GENERAL_NR_MASK

/* Number of fixed pmu registers (CPUID.EDX[0xa].EDX[0..4]) */
#define PMU_FIXED_NR_SHIFT
#define PMU_FIXED_NR_BITS
#define PMU_FIXED_NR_MASK

/* Alias registers (0x4c1) for full-width writes to PMCs */
#define MSR_PMC_ALIAS_MASK

#define INTEL_PMC_TYPE_SHIFT

static __read_mostly int intel_num_arch_counters, intel_num_fixed_counters;


static void xen_pmu_arch_init(void)
{}

static inline uint32_t get_fam15h_addr(u32 addr)
{}

static inline bool is_amd_pmu_msr(unsigned int msr)
{}

static bool is_intel_pmu_msr(u32 msr_index, int *type, int *index)
{}

static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,
				  int index, bool is_read)
{}

static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
{}

static bool pmu_msr_chk_emulated(unsigned int msr, uint64_t *val, bool is_read,
				 bool *emul)
{}

bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
{}

bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err)
{}

static unsigned long long xen_amd_read_pmc(int counter)
{}

static unsigned long long xen_intel_read_pmc(int counter)
{}

unsigned long long xen_read_pmc(int counter)
{}

int pmu_apic_update(uint32_t val)
{}

/* perf callbacks */
static unsigned int xen_guest_state(void)
{}

static unsigned long xen_get_guest_ip(void)
{}

static struct perf_guest_info_callbacks xen_guest_cbs =;

/* Convert registers from Xen's format to Linux' */
static void xen_convert_regs(const struct xen_pmu_regs *xen_regs,
			     struct pt_regs *regs, uint64_t pmu_flags)
{}

irqreturn_t xen_pmu_irq_handler(int irq, void *dev_id)
{}

bool is_xen_pmu;

void xen_pmu_init(int cpu)
{}

void xen_pmu_finish(int cpu)
{}