/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __X86_MCE_INTERNAL_H__ #define __X86_MCE_INTERNAL_H__ #undef pr_fmt #define pr_fmt(fmt) … #include <linux/device.h> #include <asm/mce.h> enum severity_level { … }; extern struct blocking_notifier_head x86_mce_decoder_chain; #define INITIAL_CHECK_INTERVAL … struct mce_evt_llist { … }; void mce_gen_pool_process(struct work_struct *__unused); bool mce_gen_pool_empty(void); int mce_gen_pool_add(struct mce *mce); int mce_gen_pool_init(void); struct llist_node *mce_gen_pool_prepare_records(void); int mce_severity(struct mce *a, struct pt_regs *regs, char **msg, bool is_excp); struct dentry *mce_get_debugfs_dir(void); extern mce_banks_t mce_banks_ce_disabled; #ifdef CONFIG_X86_MCE_INTEL void mce_intel_handle_storm(int bank, bool on); void cmci_disable_bank(int bank); void intel_init_cmci(void); void intel_init_lmce(void); void intel_clear_lmce(void); bool intel_filter_mce(struct mce *m); bool intel_mce_usable_address(struct mce *m); #else static inline void mce_intel_handle_storm(int bank, bool on) { } static inline void cmci_disable_bank(int bank) { } static inline void intel_init_cmci(void) { } static inline void intel_init_lmce(void) { } static inline void intel_clear_lmce(void) { } static inline bool intel_filter_mce(struct mce *m) { return false; } static inline bool intel_mce_usable_address(struct mce *m) { return false; } #endif void mce_timer_kick(bool storm); #ifdef CONFIG_X86_MCE_THRESHOLD void cmci_storm_begin(unsigned int bank); void cmci_storm_end(unsigned int bank); void mce_track_storm(struct mce *mce); void mce_inherit_storm(unsigned int bank); bool mce_get_storm_mode(void); void mce_set_storm_mode(bool storm); #else static inline void cmci_storm_begin(unsigned int bank) {} static inline void cmci_storm_end(unsigned int bank) {} static inline void mce_track_storm(struct mce *mce) {} static inline void mce_inherit_storm(unsigned int bank) {} static inline bool mce_get_storm_mode(void) { return false; } static inline void mce_set_storm_mode(bool storm) {} #endif /* * history: Bitmask tracking errors occurrence. Each set bit * represents an error seen. * * timestamp: Last time (in jiffies) that the bank was polled. * in_storm_mode: Is this bank in storm mode? * poll_only: Bank does not support CMCI, skip storm tracking. */ struct storm_bank { … }; #define NUM_HISTORY_BITS … /* How many errors within the history buffer mark the start of a storm. */ #define STORM_BEGIN_THRESHOLD … /* * How many polls of machine check bank without an error before declaring * the storm is over. Since it is tracked by the bitmasks in the history * field of struct storm_bank the mask is 30 bits [0 ... 29]. */ #define STORM_END_POLL_THRESHOLD … /* * banks: per-cpu, per-bank details * stormy_bank_count: count of MC banks in storm state * poll_mode: CPU is in poll mode */ struct mca_storm_desc { … }; DECLARE_PER_CPU(struct mca_storm_desc, storm_desc); #ifdef CONFIG_ACPI_APEI int apei_write_mce(struct mce *m); ssize_t apei_read_mce(struct mce *m, u64 *record_id); int apei_check_mce(void); int apei_clear_mce(u64 record_id); #else static inline int apei_write_mce(struct mce *m) { return -EINVAL; } static inline ssize_t apei_read_mce(struct mce *m, u64 *record_id) { return 0; } static inline int apei_check_mce(void) { return 0; } static inline int apei_clear_mce(u64 record_id) { return -EINVAL; } #endif /* * We consider records to be equivalent if bank+status+addr+misc all match. * This is only used when the system is going down because of a fatal error * to avoid cluttering the console log with essentially repeated information. * In normal processing all errors seen are logged. */ static inline bool mce_cmp(struct mce *m1, struct mce *m2) { … } extern struct device_attribute dev_attr_trigger; #ifdef CONFIG_X86_MCELOG_LEGACY void mce_work_trigger(void); void mce_register_injector_chain(struct notifier_block *nb); void mce_unregister_injector_chain(struct notifier_block *nb); #else static inline void mce_work_trigger(void) { } static inline void mce_register_injector_chain(struct notifier_block *nb) { } static inline void mce_unregister_injector_chain(struct notifier_block *nb) { } #endif struct mca_config { … }; extern struct mca_config mca_cfg; DECLARE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); struct mce_vendor_flags { … }; extern struct mce_vendor_flags mce_flags; struct mce_bank { … }; DECLARE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); enum mca_msr { … }; /* Decide whether to add MCE record to MCE event pool or filter it out. */ extern bool filter_mce(struct mce *m); void mce_prep_record_common(struct mce *m); void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m); bool amd_mce_usable_address(struct mce *m); /* * If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits * [56:0] of MCA_STATUS, else in bits [55:0] of MCA_ADDR. */ static __always_inline void smca_extract_err_addr(struct mce *m) { … } #else static inline bool amd_filter_mce(struct mce *m) { return false; } static inline bool amd_mce_usable_address(struct mce *m) { return false; } static inline void smca_extract_err_addr(struct mce *m) { } #endif #ifdef CONFIG_X86_ANCIENT_MCE void intel_p5_mcheck_init(struct cpuinfo_x86 *c); void winchip_mcheck_init(struct cpuinfo_x86 *c); noinstr void pentium_machine_check(struct pt_regs *regs); noinstr void winchip_machine_check(struct pt_regs *regs); static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } #else static __always_inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) { … } static __always_inline void winchip_mcheck_init(struct cpuinfo_x86 *c) { … } static __always_inline void enable_p5_mce(void) { … } static __always_inline void pentium_machine_check(struct pt_regs *regs) { … } static __always_inline void winchip_machine_check(struct pt_regs *regs) { … } #endif noinstr u64 mce_rdmsrl(u32 msr); static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg) { … } extern void (*mc_poll_banks)(void); #endif /* __X86_MCE_INTERNAL_H__ */
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