/* SPDX-License-Identifier: MIT */ /* * Copyright © 2024 Intel Corporation */ #ifndef _XE_PCODE_REGS_H_ #define _XE_PCODE_REGS_H_ #include "regs/xe_reg_defs.h" /* * This file contains addresses of PCODE registers visible through GT MMIO space. */ #define PVC_GT0_PACKAGE_ENERGY_STATUS … #define PVC_GT0_PACKAGE_RAPL_LIMIT … #define PVC_GT0_PACKAGE_POWER_SKU_UNIT … #define PVC_GT0_PLATFORM_ENERGY_STATUS … #define PVC_GT0_PACKAGE_POWER_SKU … #define BMG_PACKAGE_POWER_SKU … #define BMG_PACKAGE_POWER_SKU_UNIT … #define BMG_PACKAGE_ENERGY_STATUS … #define BMG_PACKAGE_RAPL_LIMIT … #define BMG_PLATFORM_ENERGY_STATUS … #define BMG_PLATFORM_POWER_LIMIT … #endif /* _XE_PCODE_REGS_H_ */