// SPDX-License-Identifier: GPL-2.0-only /* * (c) 2005-2016 Advanced Micro Devices, Inc. * * Written by Jacob Shin - AMD, Inc. * Maintained by: Borislav Petkov <[email protected]> * * All MC4_MISCi registers are shared between cores on a node. */ #include <linux/interrupt.h> #include <linux/notifier.h> #include <linux/kobject.h> #include <linux/percpu.h> #include <linux/errno.h> #include <linux/sched.h> #include <linux/sysfs.h> #include <linux/slab.h> #include <linux/init.h> #include <linux/cpu.h> #include <linux/smp.h> #include <linux/string.h> #include <asm/amd_nb.h> #include <asm/traps.h> #include <asm/apic.h> #include <asm/mce.h> #include <asm/msr.h> #include <asm/trace/irq_vectors.h> #include "internal.h" #define NR_BLOCKS … #define THRESHOLD_MAX … #define INT_TYPE_APIC … #define MASK_VALID_HI … #define MASK_CNTP_HI … #define MASK_LOCKED_HI … #define MASK_LVTOFF_HI … #define MASK_COUNT_EN_HI … #define MASK_INT_TYPE_HI … #define MASK_OVERFLOW_HI … #define MASK_ERR_COUNT_HI … #define MASK_BLKPTR_LO … #define MCG_XBLK_ADDR … /* Deferred error settings */ #define MSR_CU_DEF_ERR … #define MASK_DEF_LVTOFF … #define MASK_DEF_INT_TYPE … #define DEF_LVT_OFF … #define DEF_INT_TYPE_APIC … /* Scalable MCA: */ /* Threshold LVT offset is at MSR0xC0000410[15:12] */ #define SMCA_THR_LVT_OFF … static bool thresholding_irq_en; static const char * const th_names[] = …; static const char * const smca_umc_block_names[] = …; #define HWID_MCATYPE(hwid, mcatype) … struct smca_hwid { … }; struct smca_bank { … }; static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); static const char * const smca_names[] = …; static const char *smca_get_name(enum smca_bank_types t) { … } enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) { … } EXPORT_SYMBOL_GPL(…); static const struct smca_hwid smca_hwid_mcatypes[] = …; /* * In SMCA enabled processors, we can have multiple banks for a given IP type. * So to define a unique name for each bank, we use a temp c-string to append * the MCA_IPID[InstanceId] to type's name in get_name(). * * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN * is greater than 8 plus 1 (for underscore) plus length of longest type name. */ #define MAX_MCATYPE_NAME_LEN … static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); /* * A list of the banks enabled on each logical CPU. Controls which respective * descriptors to initialize later in mce_threshold_create_device(). */ static DEFINE_PER_CPU(u64, bank_map); /* Map of banks that have more than MCA_MISC0 available. */ static DEFINE_PER_CPU(u64, smca_misc_banks_map); static void amd_threshold_interrupt(void); static void amd_deferred_error_interrupt(void); static void default_deferred_error_interrupt(void) { … } void (*deferred_error_int_vector)(void) = …; static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) { … } static void smca_configure(unsigned int bank, unsigned int cpu) { … } struct thresh_restart { … }; static inline bool is_shared_bank(int bank) { … } static const char *bank4_names(const struct threshold_block *b) { switch (b->address) { /* MSR4_MISC0 */ case 0x00000413: return "dram"; case 0xc0000408: return "ht_links"; case 0xc0000409: return "l3_cache"; default: WARN(1, "Funny MSR: 0x%08x\n", b->address); return ""; } }; static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) { … } static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) { int msr = (hi & MASK_LVTOFF_HI) >> 20; if (apic < 0) { pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, b->bank, b->block, b->address, hi, lo); return 0; } if (apic != msr) { /* * On SMCA CPUs, LVT offset is programmed at a different MSR, and * the BIOS provides the value. The original field where LVT offset * was set is reserved. Return early here: */ if (mce_flags.smca) return 0; pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); return 0; } return 1; }; /* Reprogram MCx_MISC MSR behind this threshold bank. */ static void threshold_restart_bank(void *_tr) { … } static void mce_threshold_block_init(struct threshold_block *b, int offset) { struct thresh_restart tr = { .b = b, .set_lvt_off = 1, .lvt_off = offset, }; b->threshold_limit = THRESHOLD_MAX; threshold_restart_bank(&tr); }; static int setup_APIC_mce_threshold(int reserved, int new) { … } static int setup_APIC_deferred_error(int reserved, int new) { … } static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) { … } static u32 smca_get_block_address(unsigned int bank, unsigned int block, unsigned int cpu) { … } static u32 get_block_address(u32 current_addr, u32 low, u32 high, unsigned int bank, unsigned int block, unsigned int cpu) { … } static int prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, int offset, u32 misc_high) { … } bool amd_filter_mce(struct mce *m) { … } /* * Turn off thresholding banks for the following conditions: * - MC4_MISC thresholding is not supported on Family 0x15. * - Prevent possible spurious interrupts from the IF bank on Family 0x17 * Models 0x10-0x2F due to Erratum #1114. */ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) { … } /* cpu init entry point, called from mce.c with preempt off */ void mce_amd_feature_init(struct cpuinfo_x86 *c) { … } /* * DRAM ECC errors are reported in the Northbridge (bank 4) with * Extended Error Code 8. */ static bool legacy_mce_is_memory_error(struct mce *m) { … } /* * DRAM ECC errors are reported in Unified Memory Controllers with * Extended Error Code 0. */ static bool smca_mce_is_memory_error(struct mce *m) { … } bool amd_mce_is_memory_error(struct mce *m) { … } /* * AMD systems do not have an explicit indicator that the value in MCA_ADDR is * a system physical address. Therefore, individual cases need to be detected. * Future cases and checks will be added as needed. * * 1) General case * a) Assume address is not usable. * 2) Poison errors * a) Indicated by MCA_STATUS[43]: poison. Defined for all banks except legacy * northbridge (bank 4). * b) Refers to poison consumption in the core. Does not include "no action", * "action optional", or "deferred" error severities. * c) Will include a usable address so that immediate action can be taken. * 3) Northbridge DRAM ECC errors * a) Reported in legacy bank 4 with extended error code (XEC) 8. * b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore, * this bit should not be checked. * * NOTE: SMCA UMC memory errors fall into case #1. */ bool amd_mce_usable_address(struct mce *m) { … } static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) { … } DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) { … } /* * Returns true if the logged error is deferred. False, otherwise. */ static inline bool _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) { … } static bool _log_error_deferred(unsigned int bank, u32 misc) { … } /* * We have three scenarios for checking for Deferred errors: * * 1) Non-SMCA systems check MCA_STATUS and log error if found. * 2) SMCA systems check MCA_STATUS. If error is found then log it and also * clear MCA_DESTAT. * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and * log it. */ static void log_error_deferred(unsigned int bank) { … } /* APIC interrupt handler for deferred errors */ static void amd_deferred_error_interrupt(void) { … } static void log_error_thresholding(unsigned int bank, u64 misc) { … } static void log_and_reset_block(struct threshold_block *block) { … } /* * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt * goes off when error_count reaches threshold_limit. */ static void amd_threshold_interrupt(void) { … } /* * Sysfs Interface */ struct threshold_attr { … }; #define SHOW_FIELDS(name) … SHOW_FIELDS(…) … SHOW_FIELDS(…) … static ssize_t store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) { … } static ssize_t store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) { … } static ssize_t show_error_count(struct threshold_block *b, char *buf) { … } static struct threshold_attr error_count = …; #define RW_ATTR(val) … RW_ATTR(interrupt_enable); RW_ATTR(threshold_limit); static struct attribute *default_attrs[] = …; ATTRIBUTE_GROUPS(…); #define to_block(k) … #define to_attr(a) … static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) { … } static ssize_t store(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) { … } static const struct sysfs_ops threshold_ops = …; static void threshold_block_release(struct kobject *kobj); static const struct kobj_type threshold_ktype = …; static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b) { … } static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, unsigned int bank, unsigned int block, u32 address) { … } static int __threshold_add_blocks(struct threshold_bank *b) { … } static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, unsigned int bank) { … } static void threshold_block_release(struct kobject *kobj) { … } static void deallocate_threshold_blocks(struct threshold_bank *bank) { … } static void __threshold_remove_blocks(struct threshold_bank *b) { … } static void threshold_remove_bank(struct threshold_bank *bank) { … } static void __threshold_remove_device(struct threshold_bank **bp) { … } int mce_threshold_remove_device(unsigned int cpu) { … } /** * mce_threshold_create_device - Create the per-CPU MCE threshold device * @cpu: The plugged in CPU * * Create directories and files for all valid threshold banks. * * This is invoked from the CPU hotplug callback which was installed in * mcheck_init_device(). The invocation happens in context of the hotplug * thread running on @cpu. The callback is invoked on all CPUs which are * online when the callback is installed or during a real hotplug event. */ int mce_threshold_create_device(unsigned int cpu) { … }
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