linux/arch/x86/kernel/cpu/amd.c

// SPDX-License-Identifier: GPL-2.0-only
#include <linux/export.h>
#include <linux/bitops.h>
#include <linux/elf.h>
#include <linux/mm.h>

#include <linux/io.h>
#include <linux/sched.h>
#include <linux/sched/clock.h>
#include <linux/random.h>
#include <linux/topology.h>
#include <asm/processor.h>
#include <asm/apic.h>
#include <asm/cacheinfo.h>
#include <asm/cpu.h>
#include <asm/cpu_device_id.h>
#include <asm/spec-ctrl.h>
#include <asm/smp.h>
#include <asm/numa.h>
#include <asm/pci-direct.h>
#include <asm/delay.h>
#include <asm/debugreg.h>
#include <asm/resctrl.h>
#include <asm/sev.h>

#ifdef CONFIG_X86_64
# include <asm/mmconfig.h>
#endif

#include "cpu.h"

static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
{}

static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
{}

/*
 *	B step AMD K6 before B 9730xxxx have hardware bugs that can cause
 *	misexecution of code under Linux. Owners of such processors should
 *	contact AMD for precise details and a CPU swap.
 *
 *	See	http://www.multimania.com/poulot/k6bug.html
 *	and	section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
 *		(Publication # 21266  Issue Date: August 1998)
 *
 *	The following test is erm.. interesting. AMD neglected to up
 *	the chip setting when fixing the bug but they also tweaked some
 *	performance at the same time..
 */

#ifdef CONFIG_X86_32
extern __visible void vide(void);
__asm__(".text\n"
	".globl vide\n"
	".type vide, @function\n"
	".align 4\n"
	"vide: ret\n");
#endif

static void init_amd_k5(struct cpuinfo_x86 *c)
{}

static void init_amd_k6(struct cpuinfo_x86 *c)
{}

static void init_amd_k7(struct cpuinfo_x86 *c)
{}

#ifdef CONFIG_NUMA
/*
 * To workaround broken NUMA config.  Read the comment in
 * srat_detect_node().
 */
static int nearby_node(int apicid)
{}
#endif

static void srat_detect_node(struct cpuinfo_x86 *c)
{}

static void bsp_determine_snp(struct cpuinfo_x86 *c)
{}

static void bsp_init_amd(struct cpuinfo_x86 *c)
{}

static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
{}

static void early_init_amd(struct cpuinfo_x86 *c)
{}

static void init_amd_k8(struct cpuinfo_x86 *c)
{}

static void init_amd_gh(struct cpuinfo_x86 *c)
{}

static void init_amd_ln(struct cpuinfo_x86 *c)
{}

static bool rdrand_force;

static int __init rdrand_cmdline(char *str)
{}
early_param();

static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
{}

static void init_amd_jg(struct cpuinfo_x86 *c)
{}

static void init_amd_bd(struct cpuinfo_x86 *c)
{}

static const struct x86_cpu_desc erratum_1386_microcode[] =;

static void fix_erratum_1386(struct cpuinfo_x86 *c)
{}

void init_spectral_chicken(struct cpuinfo_x86 *c)
{}

static void init_amd_zen_common(void)
{}

static void init_amd_zen1(struct cpuinfo_x86 *c)
{}

static bool cpu_has_zenbleed_microcode(void)
{}

static void zen2_zenbleed_check(struct cpuinfo_x86 *c)
{}

static void init_amd_zen2(struct cpuinfo_x86 *c)
{}

static void init_amd_zen3(struct cpuinfo_x86 *c)
{}

static void init_amd_zen4(struct cpuinfo_x86 *c)
{}

static void init_amd_zen5(struct cpuinfo_x86 *c)
{}

static void init_amd(struct cpuinfo_x86 *c)
{}

#ifdef CONFIG_X86_32
static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/* AMD errata T13 (order #21922) */
	if (c->x86 == 6) {
		/* Duron Rev A0 */
		if (c->x86_model == 3 && c->x86_stepping == 0)
			size = 64;
		/* Tbird rev A1/A2 */
		if (c->x86_model == 4 &&
			(c->x86_stepping == 0 || c->x86_stepping == 1))
			size = 256;
	}
	return size;
}
#endif

static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
{}

static const struct cpu_dev amd_cpu_dev =;

cpu_dev_register(amd_cpu_dev);

static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask);

static unsigned int amd_msr_dr_addr_masks[] =;

void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr)
{}

unsigned long amd_get_dr_addr_mask(unsigned int dr)
{}
EXPORT_SYMBOL_GPL();

static void zenbleed_check_cpu(void *unused)
{}

void amd_check_microcode(void)
{}